arch/arm/boot/dts/berlin2q.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
   4  */
   5
   6 #include <dt-bindings/clock/berlin2q.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 / {
  10         model = "Marvell Armada 1500 pro (BG2-Q) SoC";
  11         compatible = "marvell,berlin2q", "marvell,berlin";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 enable-method = "marvell,berlin-smp";
  24
  25                 cpu0: cpu@0 {
  26                         compatible = "arm,cortex-a9";
  27                         device_type = "cpu";
  28                         next-level-cache = <&l2>;
  29                         reg = <0>;
  30
  31                         clocks = <&chip_clk CLKID_CPU>;
  32                         clock-latency = <100000>;
  33                         /* Can be modified by the bootloader */
  34                         operating-points = <
  35                                 /* kHz    uV */
  36                                 1200000 1200000
  37                                 1000000 1200000
  38                                 800000  1200000
  39                                 600000  1200000
  40                         >;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         compatible = "arm,cortex-a9";
  45                         device_type = "cpu";
  46                         next-level-cache = <&l2>;
  47                         reg = <1>;
  48                 };
  49
  50                 cpu2: cpu@2 {
  51                         compatible = "arm,cortex-a9";
  52                         device_type = "cpu";
  53                         next-level-cache = <&l2>;
  54                         reg = <2>;
  55                 };
  56
  57                 cpu3: cpu@3 {
  58                         compatible = "arm,cortex-a9";
  59                         device_type = "cpu";
  60                         next-level-cache = <&l2>;
  61                         reg = <3>;
  62                 };
  63         };
  64
  65         pmu {
  66                 compatible = "arm,cortex-a9-pmu";
  67                 interrupt-parent = <&gic>;
  68                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
  69                              <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
  70                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  71                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  72                 interrupt-affinity = <&cpu0>,
  73                                      <&cpu1>,
  74                                      <&cpu2>,
  75                                      <&cpu3>;
  76         };
  77
  78         refclk: oscillator {
  79                 compatible = "fixed-clock";
  80                 #clock-cells = <0>;
  81                 clock-frequency = <25000000>;
  82         };
  83
  84         soc@f7000000 {
  85                 compatible = "simple-bus";
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88
  89                 ranges = <0 0xf7000000 0x1000000>;
  90                 interrupt-parent = <&gic>;
  91
  92                 sdhci0: sdhci@ab0000 {
  93                         compatible = "mrvl,pxav3-mmc";
  94                         reg = <0xab0000 0x200>;
  95                         clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
  96                         clock-names = "io", "core";
  97                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  98                         status = "disabled";
  99                 };
 100
 101                 sdhci1: sdhci@ab0800 {
 102                         compatible = "mrvl,pxav3-mmc";
 103                         reg = <0xab0800 0x200>;
 104                         clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
 105                         clock-names = "io", "core";
 106                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 107                         status = "disabled";
 108                 };
 109
 110                 sdhci2: sdhci@ab1000 {
 111                         compatible = "mrvl,pxav3-mmc";
 112                         reg = <0xab1000 0x200>;
 113                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 114                         clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;
 115                         clock-names = "io", "core";
 116                         status = "disabled";
 117                 };
 118
 119                 l2: l2-cache-controller@ac0000 {
 120                         compatible = "arm,pl310-cache";
 121                         reg = <0xac0000 0x1000>;
 122                         cache-unified;
 123                         cache-level = <2>;
 124                         arm,data-latency = <2 2 2>;
 125                         arm,tag-latency = <2 2 2>;
 126                 };
 127
 128                 scu: snoop-control-unit@ad0000 {
 129                         compatible = "arm,cortex-a9-scu";
 130                         reg = <0xad0000 0x58>;
 131                 };
 132
 133                 local-timer@ad0600 {
 134                         compatible = "arm,cortex-a9-twd-timer";
 135                         reg = <0xad0600 0x20>;
 136                         clocks = <&chip_clk CLKID_TWD>;
 137                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 138                 };
 139
 140                 gic: interrupt-controller@ad1000 {
 141                         compatible = "arm,cortex-a9-gic";
 142                         reg = <0xad1000 0x1000>, <0xad0100 0x100>;
 143                         interrupt-controller;
 144                         #interrupt-cells = <3>;
 145                 };
 146
 147                 usb_phy2: phy@a2f400 {
 148                         compatible = "marvell,berlin2cd-usb-phy";
 149                         reg = <0xa2f400 0x128>;
 150                         #phy-cells = <0>;
 151                         resets = <&chip_rst 0x104 14>;
 152                         status = "disabled";
 153                 };
 154
 155                 usb2: usb@a30000 {
 156                         compatible = "chipidea,usb2";
 157                         reg = <0xa30000 0x10000>;
 158                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&chip_clk CLKID_USB2>;
 160                         phys = <&usb_phy2>;
 161                         phy-names = "usb-phy";
 162                         status = "disabled";
 163                 };
 164
 165                 usb_phy0: phy@b74000 {
 166                         compatible = "marvell,berlin2cd-usb-phy";
 167                         reg = <0xb74000 0x128>;
 168                         #phy-cells = <0>;
 169                         resets = <&chip_rst 0x104 12>;
 170                         status = "disabled";
 171                 };
 172
 173                 usb_phy1: phy@b78000 {
 174                         compatible = "marvell,berlin2cd-usb-phy";
 175                         reg = <0xb78000 0x128>;
 176                         #phy-cells = <0>;
 177                         resets = <&chip_rst 0x104 13>;
 178                         status = "disabled";
 179                 };
 180
 181                 eth0: ethernet@b90000 {
 182                         compatible = "marvell,pxa168-eth";
 183                         reg = <0xb90000 0x10000>;
 184                         clocks = <&chip_clk CLKID_GETH0>;
 185                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 186                         /* set by bootloader */
 187                         local-mac-address = [00 00 00 00 00 00];
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         phy-connection-type = "mii";
 191                         phy-handle = <&ethphy0>;
 192                         status = "disabled";
 193
 194                         ethphy0: ethernet-phy@0 {
 195                                 reg = <0>;
 196                         };
 197                 };
 198
 199                 cpu-ctrl@dd0000 {
 200                         compatible = "marvell,berlin-cpu-ctrl";
 201                         reg = <0xdd0000 0x10000>;
 202                 };
 203
 204                 apb@e80000 {
 205                         compatible = "simple-bus";
 206                         #address-cells = <1>;
 207                         #size-cells = <1>;
 208
 209                         ranges = <0 0xe80000 0x10000>;
 210                         interrupt-parent = <&aic>;
 211
 212                         gpio0: gpio@400 {
 213                                 compatible = "snps,dw-apb-gpio";
 214                                 reg = <0x0400 0x400>;
 215                                 #address-cells = <1>;
 216                                 #size-cells = <0>;
 217
 218                                 porta: gpio-port@0 {
 219                                         compatible = "snps,dw-apb-gpio-port";
 220                                         gpio-controller;
 221                                         #gpio-cells = <2>;
 222                                         snps,nr-gpios = <32>;
 223                                         reg = <0>;
 224                                         interrupt-controller;
 225                                         #interrupt-cells = <2>;
 226                                         interrupts = <0>;
 227                                 };
 228                         };
 229
 230                         gpio1: gpio@800 {
 231                                 compatible = "snps,dw-apb-gpio";
 232                                 reg = <0x0800 0x400>;
 233                                 #address-cells = <1>;
 234                                 #size-cells = <0>;
 235
 236                                 portb: gpio-port@1 {
 237                                         compatible = "snps,dw-apb-gpio-port";
 238                                         gpio-controller;
 239                                         #gpio-cells = <2>;
 240                                         snps,nr-gpios = <32>;
 241                                         reg = <0>;
 242                                         interrupt-controller;
 243                                         #interrupt-cells = <2>;
 244                                         interrupts = <1>;
 245                                 };
 246                         };
 247
 248                         gpio2: gpio@c00 {
 249                                 compatible = "snps,dw-apb-gpio";
 250                                 reg = <0x0c00 0x400>;
 251                                 #address-cells = <1>;
 252                                 #size-cells = <0>;
 253
 254                                 portc: gpio-port@2 {
 255                                         compatible = "snps,dw-apb-gpio-port";
 256                                         gpio-controller;
 257                                         #gpio-cells = <2>;
 258                                         snps,nr-gpios = <32>;
 259                                         reg = <0>;
 260                                         interrupt-controller;
 261                                         #interrupt-cells = <2>;
 262                                         interrupts = <2>;
 263                                 };
 264                         };
 265
 266                         gpio3: gpio@1000 {
 267                                 compatible = "snps,dw-apb-gpio";
 268                                 reg = <0x1000 0x400>;
 269                                 #address-cells = <1>;
 270                                 #size-cells = <0>;
 271
 272                                 portd: gpio-port@3 {
 273                                         compatible = "snps,dw-apb-gpio-port";
 274                                         gpio-controller;
 275                                         #gpio-cells = <2>;
 276                                         snps,nr-gpios = <32>;
 277                                         reg = <0>;
 278                                         interrupt-controller;
 279                                         #interrupt-cells = <2>;
 280                                         interrupts = <3>;
 281                                 };
 282                         };
 283
 284                         i2c0: i2c@1400 {
 285                                 compatible = "snps,designware-i2c";
 286                                 #address-cells = <1>;
 287                                 #size-cells = <0>;
 288                                 reg = <0x1400 0x100>;
 289                                 interrupts = <4>;
 290                                 clocks = <&chip_clk CLKID_CFG>;
 291                                 pinctrl-0 = <&twsi0_pmux>;
 292                                 pinctrl-names = "default";
 293                                 status = "disabled";
 294                         };
 295
 296                         i2c1: i2c@1800 {
 297                                 compatible = "snps,designware-i2c";
 298                                 #address-cells = <1>;
 299                                 #size-cells = <0>;
 300                                 reg = <0x1800 0x100>;
 301                                 interrupts = <5>;
 302                                 clocks = <&chip_clk CLKID_CFG>;
 303                                 pinctrl-0 = <&twsi1_pmux>;
 304                                 pinctrl-names = "default";
 305                                 status = "disabled";
 306                         };
 307
 308                         timer0: timer@2c00 {
 309                                 compatible = "snps,dw-apb-timer";
 310                                 reg = <0x2c00 0x14>;
 311                                 clocks = <&chip_clk CLKID_CFG>;
 312                                 clock-names = "timer";
 313                                 interrupts = <8>;
 314                         };
 315
 316                         timer1: timer@2c14 {
 317                                 compatible = "snps,dw-apb-timer";
 318                                 reg = <0x2c14 0x14>;
 319                                 clocks = <&chip_clk CLKID_CFG>;
 320                                 clock-names = "timer";
 321                         };
 322
 323                         timer2: timer@2c28 {
 324                                 compatible = "snps,dw-apb-timer";
 325                                 reg = <0x2c28 0x14>;
 326                                 clocks = <&chip_clk CLKID_CFG>;
 327                                 clock-names = "timer";
 328                                 status = "disabled";
 329                         };
 330
 331                         timer3: timer@2c3c {
 332                                 compatible = "snps,dw-apb-timer";
 333                                 reg = <0x2c3c 0x14>;
 334                                 clocks = <&chip_clk CLKID_CFG>;
 335                                 clock-names = "timer";
 336                                 status = "disabled";
 337                         };
 338
 339                         timer4: timer@2c50 {
 340                                 compatible = "snps,dw-apb-timer";
 341                                 reg = <0x2c50 0x14>;
 342                                 clocks = <&chip_clk CLKID_CFG>;
 343                                 clock-names = "timer";
 344                                 status = "disabled";
 345                         };
 346
 347                         timer5: timer@2c64 {
 348                                 compatible = "snps,dw-apb-timer";
 349                                 reg = <0x2c64 0x14>;
 350                                 clocks = <&chip_clk CLKID_CFG>;
 351                                 clock-names = "timer";
 352                                 status = "disabled";
 353                         };
 354
 355                         timer6: timer@2c78 {
 356                                 compatible = "snps,dw-apb-timer";
 357                                 reg = <0x2c78 0x14>;
 358                                 clocks = <&chip_clk CLKID_CFG>;
 359                                 clock-names = "timer";
 360                                 status = "disabled";
 361                         };
 362
 363                         timer7: timer@2c8c {
 364                                 compatible = "snps,dw-apb-timer";
 365                                 reg = <0x2c8c 0x14>;
 366                                 clocks = <&chip_clk CLKID_CFG>;
 367                                 clock-names = "timer";
 368                                 status = "disabled";
 369                         };
 370
 371                         aic: interrupt-controller@3800 {
 372                                 compatible = "snps,dw-apb-ictl";
 373                                 reg = <0x3800 0x30>;
 374                                 interrupt-controller;
 375                                 #interrupt-cells = <1>;
 376                                 interrupt-parent = <&gic>;
 377                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 378                         };
 379                 };
 380
 381                 chip: chip-control@ea0000 {
 382                         compatible = "simple-mfd", "syscon";
 383                         reg = <0xea0000 0x400>, <0xdd0170 0x10>;
 384
 385                         chip_clk: clock {
 386                                 compatible = "marvell,berlin2q-clk";
 387                                 #clock-cells = <1>;
 388                                 clocks = <&refclk>;
 389                                 clock-names = "refclk";
 390                         };
 391
 392                         soc_pinctrl: pin-controller {
 393                                 compatible = "marvell,berlin2q-soc-pinctrl";
 394
 395                                 sd1_pmux: sd1-pmux {
 396                                         groups = "G31";
 397                                         function = "sd1";
 398                                 };
 399
 400                                 twsi0_pmux: twsi0-pmux {
 401                                         groups = "G6";
 402                                         function = "twsi0";
 403                                 };
 404
 405                                 twsi1_pmux: twsi1-pmux {
 406                                         groups = "G7";
 407                                         function = "twsi1";
 408                                 };
 409                         };
 410
 411                         chip_rst: reset {
 412                                 compatible = "marvell,berlin2-reset";
 413                                 #reset-cells = <2>;
 414                         };
 415                 };
 416
 417                 ahci: sata@e90000 {
 418                         compatible = "marvell,berlin2q-ahci", "generic-ahci";
 419                         reg = <0xe90000 0x1000>;
 420                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&chip_clk CLKID_SATA>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424
 425                         sata0: sata-port@0 {
 426                                 reg = <0>;
 427                                 phys = <&sata_phy 0>;
 428                                 status = "disabled";
 429                         };
 430
 431                         sata1: sata-port@1 {
 432                                 reg = <1>;
 433                                 phys = <&sata_phy 1>;
 434                                 status = "disabled";
 435                         };
 436                 };
 437
 438                 sata_phy: phy@e900a0 {
 439                         compatible = "marvell,berlin2q-sata-phy";
 440                         reg = <0xe900a0 0x200>;
 441                         clocks = <&chip_clk CLKID_SATA>;
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         #phy-cells = <1>;
 445                         status = "disabled";
 446
 447                         sata-phy@0 {
 448                                 reg = <0>;
 449                         };
 450
 451                         sata-phy@1 {
 452                                 reg = <1>;
 453                         };
 454                 };
 455
 456                 usb0: usb@ed0000 {
 457                         compatible = "chipidea,usb2";
 458                         reg = <0xed0000 0x10000>;
 459                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 460                         clocks = <&chip_clk CLKID_USB0>;
 461                         phys = <&usb_phy0>;
 462                         phy-names = "usb-phy";
 463                         status = "disabled";
 464                 };
 465
 466                 usb1: usb@ee0000 {
 467                         compatible = "chipidea,usb2";
 468                         reg = <0xee0000 0x10000>;
 469                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 470                         clocks = <&chip_clk CLKID_USB1>;
 471                         phys = <&usb_phy1>;
 472                         phy-names = "usb-phy";
 473                         status = "disabled";
 474                 };
 475
 476                 pwm: pwm@f20000 {
 477                         compatible = "marvell,berlin-pwm";
 478                         reg = <0xf20000 0x40>;
 479                         clocks = <&chip_clk CLKID_CFG>;
 480                         #pwm-cells = <3>;
 481                 };
 482
 483                 apb@fc0000 {
 484                         compatible = "simple-bus";
 485                         #address-cells = <1>;
 486                         #size-cells = <1>;
 487
 488                         ranges = <0 0xfc0000 0x10000>;
 489                         interrupt-parent = <&sic>;
 490
 491                         wdt0: watchdog@1000 {
 492                                 compatible = "snps,dw-wdt";
 493                                 reg = <0x1000 0x100>;
 494                                 clocks = <&refclk>;
 495                                 interrupts = <0>;
 496                         };
 497
 498                         wdt1: watchdog@2000 {
 499                                 compatible = "snps,dw-wdt";
 500                                 reg = <0x2000 0x100>;
 501                                 clocks = <&refclk>;
 502                                 interrupts = <1>;
 503                         };
 504
 505                         wdt2: watchdog@3000 {
 506                                 compatible = "snps,dw-wdt";
 507                                 reg = <0x3000 0x100>;
 508                                 clocks = <&refclk>;
 509                                 interrupts = <2>;
 510                         };
 511
 512                         sm_gpio1: gpio@5000 {
 513                                 compatible = "snps,dw-apb-gpio";
 514                                 reg = <0x5000 0x400>;
 515                                 #address-cells = <1>;
 516                                 #size-cells = <0>;
 517
 518                                 portf: gpio-port@5 {
 519                                         compatible = "snps,dw-apb-gpio-port";
 520                                         gpio-controller;
 521                                         #gpio-cells = <2>;
 522                                         snps,nr-gpios = <32>;
 523                                         reg = <0>;
 524                                 };
 525                         };
 526
 527                         i2c2: i2c@7000 {
 528                                 compatible = "snps,designware-i2c";
 529                                 #address-cells = <1>;
 530                                 #size-cells = <0>;
 531                                 reg = <0x7000 0x100>;
 532                                 interrupts = <6>;
 533                                 clocks = <&refclk>;
 534                                 pinctrl-0 = <&twsi2_pmux>;
 535                                 pinctrl-names = "default";
 536                                 status = "disabled";
 537                         };
 538
 539                         i2c3: i2c@8000 {
 540                                 compatible = "snps,designware-i2c";
 541                                 #address-cells = <1>;
 542                                 #size-cells = <0>;
 543                                 reg = <0x8000 0x100>;
 544                                 interrupts = <7>;
 545                                 clocks = <&refclk>;
 546                                 pinctrl-0 = <&twsi3_pmux>;
 547                                 pinctrl-names = "default";
 548                                 status = "disabled";
 549                         };
 550
 551                         uart0: uart@9000 {
 552                                 compatible = "snps,dw-apb-uart";
 553                                 reg = <0x9000 0x100>;
 554                                 interrupts = <8>;
 555                                 clocks = <&refclk>;
 556                                 reg-shift = <2>;
 557                                 pinctrl-0 = <&uart0_pmux>;
 558                                 pinctrl-names = "default";
 559                                 status = "disabled";
 560                         };
 561
 562                         uart1: uart@a000 {
 563                                 compatible = "snps,dw-apb-uart";
 564                                 reg = <0xa000 0x100>;
 565                                 interrupts = <9>;
 566                                 clocks = <&refclk>;
 567                                 reg-shift = <2>;
 568                                 pinctrl-0 = <&uart1_pmux>;
 569                                 pinctrl-names = "default";
 570                                 status = "disabled";
 571                         };
 572
 573                         sm_gpio0: gpio@c000 {
 574                                 compatible = "snps,dw-apb-gpio";
 575                                 reg = <0xc000 0x400>;
 576                                 #address-cells = <1>;
 577                                 #size-cells = <0>;
 578
 579                                 porte: gpio-port@4 {
 580                                         compatible = "snps,dw-apb-gpio-port";
 581                                         gpio-controller;
 582                                         #gpio-cells = <2>;
 583                                         snps,nr-gpios = <32>;
 584                                         reg = <0>;
 585                                 };
 586                         };
 587
 588                         sysctrl: pin-controller@d000 {
 589                                 compatible = "simple-mfd", "syscon";
 590                                 reg = <0xd000 0x100>;
 591
 592                                 sys_pinctrl: pin-controller {
 593                                         compatible = "marvell,berlin2q-system-pinctrl";
 594
 595                                         uart0_pmux: uart0-pmux {
 596                                                 groups = "GSM12";
 597                                                 function = "uart0";
 598                                         };
 599
 600                                         uart1_pmux: uart1-pmux {
 601                                                 groups = "GSM14";
 602                                                 function = "uart1";
 603                                         };
 604
 605                                         twsi2_pmux: twsi2-pmux {
 606                                                 groups = "GSM13";
 607                                                 function = "twsi2";
 608                                         };
 609
 610                                         twsi3_pmux: twsi3-pmux {
 611                                                 groups = "GSM14";
 612                                                 function = "twsi3";
 613                                         };
 614                                 };
 615
 616                                 adc: adc {
 617                                         compatible = "marvell,berlin2-adc";
 618                                         interrupts = <12>, <14>;
 619                                         interrupt-names = "adc", "tsen";
 620                                 };
 621                         };
 622
 623                         sic: interrupt-controller@e000 {
 624                                 compatible = "snps,dw-apb-ictl";
 625                                 reg = <0xe000 0x30>;
 626                                 interrupt-controller;
 627                                 #interrupt-cells = <1>;
 628                                 interrupt-parent = <&gic>;
 629                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 630                         };
 631                 };
 632         };
 633 };