arch/arm/boot/dts/da850-lcdk.dts

   1 /*
   2  * Copyright (c) 2016 BayLibre, Inc.
   3  *
   4  * Licensed under GPLv2.
   5  */
   6 /dts-v1/;
   7 #include "da850.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         model = "DA850/AM1808/OMAP-L138 LCDK";
  12         compatible = "ti,da850-lcdk", "ti,da850";
  13
  14         aliases {
  15                 serial2 = &serial2;
  16                 ethernet0 = &eth0;
  17         };
  18
  19         chosen {
  20                 stdout-path = "serial2:115200n8";
  21         };
  22
  23         memory {
  24                 device_type = "memory";
  25                 reg = <0xc0000000 0x08000000>;
  26         };
  27
  28         sound {
  29                 compatible = "simple-audio-card";
  30                 simple-audio-card,name = "DA850/OMAP-L138 LCDK";
  31                 simple-audio-card,widgets =
  32                         "Line", "Line In",
  33                         "Line", "Line Out";
  34                 simple-audio-card,routing =
  35                         "LINE1L", "Line In",
  36                         "LINE1R", "Line In",
  37                         "Line Out", "LLOUT",
  38                         "Line Out", "RLOUT";
  39                 simple-audio-card,format = "dsp_b";
  40                 simple-audio-card,bitclock-master = <&link0_codec>;
  41                 simple-audio-card,frame-master = <&link0_codec>;
  42                 simple-audio-card,bitclock-inversion;
  43
  44                 simple-audio-card,cpu {
  45                         sound-dai = <&mcasp0>;
  46                         system-clock-frequency = <24576000>;
  47                 };
  48
  49                 link0_codec: simple-audio-card,codec {
  50                         sound-dai = <&tlv320aic3106>;
  51                         system-clock-frequency = <24576000>;
  52                 };
  53         };
  54 };
  55
  56 &pmx_core {
  57         status = "okay";
  58
  59         mcasp0_pins: pinmux_mcasp0_pins {
  60                 pinctrl-single,bits = <
  61                         /* AHCLKX AFSX ACLKX */
  62                         0x00 0x00101010 0x00f0f0f0
  63                         /* ARX13 ARX14 */
  64                         0x04 0x00000110 0x00000ff0
  65                 >;
  66         };
  67
  68         nand_pins: nand_pins {
  69                 pinctrl-single,bits = <
  70                         /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
  71                         0x1c 0x10110010  0xf0ff00f0
  72                         /*
  73                          * EMA_D[0], EMA_D[1], EMA_D[2],
  74                          * EMA_D[3], EMA_D[4], EMA_D[5],
  75                          * EMA_D[6], EMA_D[7]
  76                          */
  77                         0x24 0x11111111  0xffffffff
  78                         /*
  79                          * EMA_D[8],  EMA_D[9],  EMA_D[10],
  80                          * EMA_D[11], EMA_D[12], EMA_D[13],
  81                          * EMA_D[14], EMA_D[15]
  82                          */
  83                         0x20 0x11111111  0xffffffff
  84                         /* EMA_A[1], EMA_A[2] */
  85                         0x30 0x01100000  0x0ff00000
  86                 >;
  87         };
  88 };
  89
  90 &serial2 {
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&serial2_rxtx_pins>;
  93         status = "okay";
  94 };
  95
  96 &wdt {
  97         status = "okay";
  98 };
  99
 100 &rtc0 {
 101         status = "okay";
 102 };
 103
 104 &gpio {
 105         status = "okay";
 106 };
 107
 108 &mdio {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&mdio_pins>;
 111         bus_freq = <2200000>;
 112         status = "okay";
 113 };
 114
 115 &eth0 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&mii_pins>;
 118         status = "okay";
 119 };
 120
 121 &mmc0 {
 122         max-frequency = <50000000>;
 123         bus-width = <4>;
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&mmc0_pins>;
 126         cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
 127         status = "okay";
 128 };
 129
 130 &i2c0 {
 131         pinctrl-names = "default";
 132         pinctrl-0 = <&i2c0_pins>;
 133         clock-frequency = <100000>;
 134         status = "okay";
 135
 136         tlv320aic3106: tlv320aic3106@18 {
 137                 #sound-dai-cells = <0>;
 138                 compatible = "ti,tlv320aic3106";
 139                 reg = <0x18>;
 140                 status = "okay";
 141         };
 142 };
 143
 144 &mcasp0 {
 145         #sound-dai-cells = <0>;
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&mcasp0_pins>;
 148         status = "okay";
 149
 150         op-mode = <0>;   /* DAVINCI_MCASP_IIS_MODE */
 151         tdm-slots = <2>;
 152         serial-dir = <   /* 0: INACTIVE, 1: TX, 2: RX */
 153                 0 0 0 0
 154                 0 0 0 0
 155                 0 0 0 0
 156                 0 1 2 0
 157         >;
 158         tx-num-evt = <32>;
 159         rx-num-evt = <32>;
 160 };
 161
 162 &usb_phy {
 163         status = "okay";
 164 };
 165
 166 &usb0 {
 167         status = "okay";
 168 };
 169
 170 &aemif {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&nand_pins>;
 173         status = "okay";
 174         cs3 {
 175                 #address-cells = <2>;
 176                 #size-cells = <1>;
 177                 clock-ranges;
 178                 ranges;
 179
 180                 ti,cs-chipselect = <3>;
 181
 182                 nand@2000000,0 {
 183                         compatible = "ti,davinci-nand";
 184                         #address-cells = <1>;
 185                         #size-cells = <1>;
 186                         reg = <0 0x02000000 0x02000000
 187                                1 0x00000000 0x00008000>;
 188
 189                         ti,davinci-chipselect = <1>;
 190                         ti,davinci-mask-ale = <0>;
 191                         ti,davinci-mask-cle = <0>;
 192                         ti,davinci-mask-chipsel = <0>;
 193
 194                         ti,davinci-nand-buswidth = <16>;
 195                         ti,davinci-ecc-mode = "hw";
 196                         ti,davinci-ecc-bits = <4>;
 197                         ti,davinci-nand-use-bbt;
 198
 199                         /*
 200                          * The OMAP-L132/L138 Bootloader doc SPRAB41E reads:
 201                          * "To boot from NAND Flash, the AIS should be written
 202                          * to NAND block 1 (NAND block 0 is not used by default)".
 203                          * The same doc mentions that for ROM "Silicon Revision 2.1",
 204                          * "Updated NAND boot mode to offer boot from block 0 or block 1".
 205                          * However the limitaion is left here by default for compatibility
 206                          * with older silicon and because it needs new boot pin settings
 207                          * not possible in stock LCDK.
 208                          */
 209                         partitions {
 210                                 compatible = "fixed-partitions";
 211                                 #address-cells = <1>;
 212                                 #size-cells = <1>;
 213
 214                                 partition@0 {
 215                                         label = "u-boot env";
 216                                         reg = <0 0x020000>;
 217                                 };
 218                                 partition@0x020000 {
 219                                         /* The LCDK defaults to booting from this partition */
 220                                         label = "u-boot";
 221                                         reg = <0x020000 0x080000>;
 222                                 };
 223                                 partition@0x0a0000 {
 224                                         label = "free space";
 225                                         reg = <0x0a0000 0>;
 226                                 };
 227                         };
 228                 };
 229         };
 230 };
 231
 232 &prictrl {
 233         status = "okay";
 234 };
 235
 236 &memctrl {
 237         status = "okay";
 238 };