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ARM: dts: dove: Always include gpio and interrupt-controller headers
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / dove.dtsi
1 /include/ "skeleton.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5
6 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
7
8 / {
9 compatible = "marvell,dove";
10 model = "Marvell Armada 88AP510 SoC";
11 interrupt-parent = <&intc>;
12
13 aliases {
14 gpio0 = &gpio0;
15 gpio1 = &gpio1;
16 gpio2 = &gpio2;
17 };
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu0: cpu@0 {
24 compatible = "marvell,pj4a", "marvell,sheeva-v7";
25 device_type = "cpu";
26 next-level-cache = <&l2>;
27 reg = <0>;
28 };
29 };
30
31 l2: l2-cache {
32 compatible = "marvell,tauros2-cache";
33 marvell,tauros2-cache-features = <0>;
34 };
35
36 mbus {
37 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
38 #address-cells = <2>;
39 #size-cells = <1>;
40 controller = <&mbusc>;
41 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
42 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
43
44 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
45 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
46 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
47 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
48 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
49
50 pcie: pcie-controller {
51 compatible = "marvell,dove-pcie";
52 status = "disabled";
53 device_type = "pci";
54 #address-cells = <3>;
55 #size-cells = <2>;
56
57 msi-parent = <&intc>;
58 bus-range = <0x00 0xff>;
59
60 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
61 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
62 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
63 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
64 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
65 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
66
67 pcie-port@0 {
68 device_type = "pci";
69 status = "disabled";
70 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
71 reg = <0x0800 0 0 0 0>;
72 clocks = <&gate_clk 4>;
73 marvell,pcie-port = <0>;
74
75 #address-cells = <3>;
76 #size-cells = <2>;
77 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
78 0x81000000 0 0 0x81000000 0x1 0 1 0>;
79
80 #interrupt-cells = <1>;
81 interrupt-map-mask = <0 0 0 0>;
82 interrupt-map = <0 0 0 0 &intc 16>;
83 };
84
85 pcie-port@1 {
86 device_type = "pci";
87 status = "disabled";
88 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
89 reg = <0x1000 0 0 0 0>;
90 clocks = <&gate_clk 5>;
91 marvell,pcie-port = <1>;
92
93 #address-cells = <3>;
94 #size-cells = <2>;
95 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
96 0x81000000 0 0 0x81000000 0x2 0 1 0>;
97
98 #interrupt-cells = <1>;
99 interrupt-map-mask = <0 0 0 0>;
100 interrupt-map = <0 0 0 0 &intc 18>;
101 };
102 };
103
104 internal-regs {
105 compatible = "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
109 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
110 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
111 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
112
113 spi0: spi-ctrl@10600 {
114 compatible = "marvell,orion-spi";
115 #address-cells = <1>;
116 #size-cells = <0>;
117 cell-index = <0>;
118 interrupts = <6>;
119 reg = <0x10600 0x28>;
120 clocks = <&core_clk 0>;
121 pinctrl-0 = <&pmx_spi0>;
122 pinctrl-names = "default";
123 status = "disabled";
124 };
125
126 i2c0: i2c-ctrl@11000 {
127 compatible = "marvell,mv64xxx-i2c";
128 reg = <0x11000 0x20>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 interrupts = <11>;
132 clock-frequency = <400000>;
133 timeout-ms = <1000>;
134 clocks = <&core_clk 0>;
135 status = "disabled";
136 };
137
138 uart0: serial@12000 {
139 compatible = "ns16550a";
140 reg = <0x12000 0x100>;
141 reg-shift = <2>;
142 interrupts = <7>;
143 clocks = <&core_clk 0>;
144 status = "disabled";
145 };
146
147 uart1: serial@12100 {
148 compatible = "ns16550a";
149 reg = <0x12100 0x100>;
150 reg-shift = <2>;
151 interrupts = <8>;
152 clocks = <&core_clk 0>;
153 pinctrl-0 = <&pmx_uart1>;
154 pinctrl-names = "default";
155 status = "disabled";
156 };
157
158 uart2: serial@12200 {
159 compatible = "ns16550a";
160 reg = <0x12200 0x100>;
161 reg-shift = <2>;
162 interrupts = <9>;
163 clocks = <&core_clk 0>;
164 status = "disabled";
165 };
166
167 uart3: serial@12300 {
168 compatible = "ns16550a";
169 reg = <0x12300 0x100>;
170 reg-shift = <2>;
171 interrupts = <10>;
172 clocks = <&core_clk 0>;
173 status = "disabled";
174 };
175
176 spi1: spi-ctrl@14600 {
177 compatible = "marvell,orion-spi";
178 #address-cells = <1>;
179 #size-cells = <0>;
180 cell-index = <1>;
181 interrupts = <5>;
182 reg = <0x14600 0x28>;
183 clocks = <&core_clk 0>;
184 status = "disabled";
185 };
186
187 mbusc: mbus-ctrl@20000 {
188 compatible = "marvell,mbus-controller";
189 reg = <0x20000 0x80>, <0x800100 0x8>;
190 };
191
192 sysc: system-ctrl@20000 {
193 compatible = "marvell,orion-system-controller";
194 reg = <0x20000 0x110>;
195 };
196
197 bridge_intc: bridge-interrupt-ctrl@20110 {
198 compatible = "marvell,orion-bridge-intc";
199 interrupt-controller;
200 #interrupt-cells = <1>;
201 reg = <0x20110 0x8>;
202 interrupts = <0>;
203 marvell,#interrupts = <5>;
204 };
205
206 intc: main-interrupt-ctrl@20200 {
207 compatible = "marvell,orion-intc";
208 interrupt-controller;
209 #interrupt-cells = <1>;
210 reg = <0x20200 0x10>, <0x20210 0x10>;
211 };
212
213 timer: timer@20300 {
214 compatible = "marvell,orion-timer";
215 reg = <0x20300 0x20>;
216 interrupt-parent = <&bridge_intc>;
217 interrupts = <1>, <2>;
218 clocks = <&core_clk 0>;
219 };
220
221 watchdog@20300 {
222 compatible = "marvell,orion-wdt";
223 reg = <0x20300 0x28>, <0x20108 0x4>;
224 interrupt-parent = <&bridge_intc>;
225 interrupts = <3>;
226 clocks = <&core_clk 0>;
227 };
228
229 crypto: crypto-engine@30000 {
230 compatible = "marvell,orion-crypto";
231 reg = <0x30000 0x10000>,
232 <0xffffe000 0x800>;
233 reg-names = "regs", "sram";
234 interrupts = <31>;
235 clocks = <&gate_clk 15>;
236 status = "okay";
237 };
238
239 ehci0: usb-host@50000 {
240 compatible = "marvell,orion-ehci";
241 reg = <0x50000 0x1000>;
242 interrupts = <24>;
243 clocks = <&gate_clk 0>;
244 status = "okay";
245 };
246
247 ehci1: usb-host@51000 {
248 compatible = "marvell,orion-ehci";
249 reg = <0x51000 0x1000>;
250 interrupts = <25>;
251 clocks = <&gate_clk 1>;
252 status = "okay";
253 };
254
255 xor0: dma-engine@60800 {
256 compatible = "marvell,orion-xor";
257 reg = <0x60800 0x100
258 0x60a00 0x100>;
259 clocks = <&gate_clk 23>;
260 status = "okay";
261
262 channel0 {
263 interrupts = <39>;
264 dmacap,memcpy;
265 dmacap,xor;
266 };
267
268 channel1 {
269 interrupts = <40>;
270 dmacap,memcpy;
271 dmacap,xor;
272 };
273 };
274
275 xor1: dma-engine@60900 {
276 compatible = "marvell,orion-xor";
277 reg = <0x60900 0x100
278 0x60b00 0x100>;
279 clocks = <&gate_clk 24>;
280 status = "okay";
281
282 channel0 {
283 interrupts = <42>;
284 dmacap,memcpy;
285 dmacap,xor;
286 };
287
288 channel1 {
289 interrupts = <43>;
290 dmacap,memcpy;
291 dmacap,xor;
292 };
293 };
294
295 sdio1: sdio-host@90000 {
296 compatible = "marvell,dove-sdhci";
297 reg = <0x90000 0x100>;
298 interrupts = <36>, <38>;
299 clocks = <&gate_clk 9>;
300 pinctrl-0 = <&pmx_sdio1>;
301 pinctrl-names = "default";
302 status = "disabled";
303 };
304
305 eth: ethernet-ctrl@72000 {
306 compatible = "marvell,orion-eth";
307 #address-cells = <1>;
308 #size-cells = <0>;
309 reg = <0x72000 0x4000>;
310 clocks = <&gate_clk 2>;
311 marvell,tx-checksum-limit = <1600>;
312 status = "disabled";
313
314 ethernet-port@0 {
315 compatible = "marvell,orion-eth-port";
316 reg = <0>;
317 interrupts = <29>;
318 /* overwrite MAC address in bootloader */
319 local-mac-address = [00 00 00 00 00 00];
320 phy-handle = <&ethphy>;
321 };
322 };
323
324 mdio: mdio-bus@72004 {
325 compatible = "marvell,orion-mdio";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 reg = <0x72004 0x84>;
329 interrupts = <30>;
330 clocks = <&gate_clk 2>;
331 status = "disabled";
332
333 ethphy: ethernet-phy {
334 /* set phy address in board file */
335 };
336 };
337
338 sdio0: sdio-host@92000 {
339 compatible = "marvell,dove-sdhci";
340 reg = <0x92000 0x100>;
341 interrupts = <35>, <37>;
342 clocks = <&gate_clk 8>;
343 pinctrl-0 = <&pmx_sdio0>;
344 pinctrl-names = "default";
345 status = "disabled";
346 };
347
348 sata0: sata-host@a0000 {
349 compatible = "marvell,orion-sata";
350 reg = <0xa0000 0x2400>;
351 interrupts = <62>;
352 clocks = <&gate_clk 3>;
353 phys = <&sata_phy0>;
354 phy-names = "port0";
355 nr-ports = <1>;
356 status = "disabled";
357 };
358
359 sata_phy0: sata-phy@a2000 {
360 compatible = "marvell,mvebu-sata-phy";
361 reg = <0xa2000 0x0334>;
362 clocks = <&gate_clk 3>;
363 clock-names = "sata";
364 #phy-cells = <0>;
365 status = "ok";
366 };
367
368 audio0: audio-controller@b0000 {
369 compatible = "marvell,dove-audio";
370 reg = <0xb0000 0x2210>;
371 interrupts = <19>, <20>;
372 clocks = <&gate_clk 12>;
373 clock-names = "internal";
374 status = "disabled";
375 };
376
377 audio1: audio-controller@b4000 {
378 compatible = "marvell,dove-audio";
379 reg = <0xb4000 0x2210>;
380 interrupts = <21>, <22>;
381 clocks = <&gate_clk 13>;
382 clock-names = "internal";
383 status = "disabled";
384 };
385
386 thermal: thermal-diode@d001c {
387 compatible = "marvell,dove-thermal";
388 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
389 };
390
391 gate_clk: clock-gating-ctrl@d0038 {
392 compatible = "marvell,dove-gating-clock";
393 reg = <0xd0038 0x4>;
394 clocks = <&core_clk 0>;
395 #clock-cells = <1>;
396 };
397
398 pinctrl: pin-ctrl@d0200 {
399 compatible = "marvell,dove-pinctrl";
400 reg = <0xd0200 0x14>,
401 <0xd0440 0x04>;
402 clocks = <&gate_clk 22>;
403
404 pmx_gpio_0: pmx-gpio-0 {
405 marvell,pins = "mpp0";
406 marvell,function = "gpio";
407 };
408
409 pmx_gpio_1: pmx-gpio-1 {
410 marvell,pins = "mpp1";
411 marvell,function = "gpio";
412 };
413
414 pmx_gpio_2: pmx-gpio-2 {
415 marvell,pins = "mpp2";
416 marvell,function = "gpio";
417 };
418
419 pmx_gpio_3: pmx-gpio-3 {
420 marvell,pins = "mpp3";
421 marvell,function = "gpio";
422 };
423
424 pmx_gpio_4: pmx-gpio-4 {
425 marvell,pins = "mpp4";
426 marvell,function = "gpio";
427 };
428
429 pmx_gpio_5: pmx-gpio-5 {
430 marvell,pins = "mpp5";
431 marvell,function = "gpio";
432 };
433
434 pmx_gpio_6: pmx-gpio-6 {
435 marvell,pins = "mpp6";
436 marvell,function = "gpio";
437 };
438
439 pmx_gpio_7: pmx-gpio-7 {
440 marvell,pins = "mpp7";
441 marvell,function = "gpio";
442 };
443
444 pmx_gpio_8: pmx-gpio-8 {
445 marvell,pins = "mpp8";
446 marvell,function = "gpio";
447 };
448
449 pmx_gpio_9: pmx-gpio-9 {
450 marvell,pins = "mpp9";
451 marvell,function = "gpio";
452 };
453
454 pmx_gpio_10: pmx-gpio-10 {
455 marvell,pins = "mpp10";
456 marvell,function = "gpio";
457 };
458
459 pmx_gpio_11: pmx-gpio-11 {
460 marvell,pins = "mpp11";
461 marvell,function = "gpio";
462 };
463
464 pmx_gpio_12: pmx-gpio-12 {
465 marvell,pins = "mpp12";
466 marvell,function = "gpio";
467 };
468
469 pmx_gpio_13: pmx-gpio-13 {
470 marvell,pins = "mpp13";
471 marvell,function = "gpio";
472 };
473
474 pmx_audio1_extclk: pmx-audio1-extclk {
475 marvell,pins = "mpp13";
476 marvell,function = "audio1";
477 };
478
479 pmx_gpio_14: pmx-gpio-14 {
480 marvell,pins = "mpp14";
481 marvell,function = "gpio";
482 };
483
484 pmx_gpio_15: pmx-gpio-15 {
485 marvell,pins = "mpp15";
486 marvell,function = "gpio";
487 };
488
489 pmx_gpio_16: pmx-gpio-16 {
490 marvell,pins = "mpp16";
491 marvell,function = "gpio";
492 };
493
494 pmx_gpio_17: pmx-gpio-17 {
495 marvell,pins = "mpp17";
496 marvell,function = "gpio";
497 };
498
499 pmx_gpio_18: pmx-gpio-18 {
500 marvell,pins = "mpp18";
501 marvell,function = "gpio";
502 };
503
504 pmx_gpio_19: pmx-gpio-19 {
505 marvell,pins = "mpp19";
506 marvell,function = "gpio";
507 };
508
509 pmx_gpio_20: pmx-gpio-20 {
510 marvell,pins = "mpp20";
511 marvell,function = "gpio";
512 };
513
514 pmx_gpio_21: pmx-gpio-21 {
515 marvell,pins = "mpp21";
516 marvell,function = "gpio";
517 };
518
519 pmx_camera: pmx-camera {
520 marvell,pins = "mpp_camera";
521 marvell,function = "camera";
522 };
523
524 pmx_camera_gpio: pmx-camera-gpio {
525 marvell,pins = "mpp_camera";
526 marvell,function = "gpio";
527 };
528
529 pmx_sdio0: pmx-sdio0 {
530 marvell,pins = "mpp_sdio0";
531 marvell,function = "sdio0";
532 };
533
534 pmx_sdio0_gpio: pmx-sdio0-gpio {
535 marvell,pins = "mpp_sdio0";
536 marvell,function = "gpio";
537 };
538
539 pmx_sdio1: pmx-sdio1 {
540 marvell,pins = "mpp_sdio1";
541 marvell,function = "sdio1";
542 };
543
544 pmx_sdio1_gpio: pmx-sdio1-gpio {
545 marvell,pins = "mpp_sdio1";
546 marvell,function = "gpio";
547 };
548
549 pmx_audio1_gpio: pmx-audio1-gpio {
550 marvell,pins = "mpp_audio1";
551 marvell,function = "gpio";
552 };
553
554 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
555 marvell,pins = "mpp_audio1";
556 marvell,function = "i2s1/spdifo";
557 };
558
559 pmx_spi0: pmx-spi0 {
560 marvell,pins = "mpp_spi0";
561 marvell,function = "spi0";
562 };
563
564 pmx_spi0_gpio: pmx-spi0-gpio {
565 marvell,pins = "mpp_spi0";
566 marvell,function = "gpio";
567 };
568
569 pmx_uart1: pmx-uart1 {
570 marvell,pins = "mpp_uart1";
571 marvell,function = "uart1";
572 };
573
574 pmx_uart1_gpio: pmx-uart1-gpio {
575 marvell,pins = "mpp_uart1";
576 marvell,function = "gpio";
577 };
578
579 pmx_nand: pmx-nand {
580 marvell,pins = "mpp_nand";
581 marvell,function = "nand";
582 };
583
584 pmx_nand_gpo: pmx-nand-gpo {
585 marvell,pins = "mpp_nand";
586 marvell,function = "gpo";
587 };
588 };
589
590 core_clk: core-clocks@d0214 {
591 compatible = "marvell,dove-core-clock";
592 reg = <0xd0214 0x4>;
593 #clock-cells = <1>;
594 };
595
596 gpio0: gpio-ctrl@d0400 {
597 compatible = "marvell,orion-gpio";
598 #gpio-cells = <2>;
599 gpio-controller;
600 reg = <0xd0400 0x20>;
601 ngpios = <32>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
604 interrupts = <12>, <13>, <14>, <60>;
605 };
606
607 gpio1: gpio-ctrl@d0420 {
608 compatible = "marvell,orion-gpio";
609 #gpio-cells = <2>;
610 gpio-controller;
611 reg = <0xd0420 0x20>;
612 ngpios = <32>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
615 interrupts = <61>;
616 };
617
618 rtc: real-time-clock@d8500 {
619 compatible = "marvell,orion-rtc";
620 reg = <0xd8500 0x20>;
621 };
622
623 gconf: global-config@e802c {
624 compatible = "marvell,dove-global-config",
625 "syscon";
626 reg = <0xe802c 0x14>;
627 };
628
629 gpio2: gpio-ctrl@e8400 {
630 compatible = "marvell,orion-gpio";
631 #gpio-cells = <2>;
632 gpio-controller;
633 reg = <0xe8400 0x0c>;
634 ngpios = <8>;
635 };
636
637 lcd1: lcd-controller@810000 {
638 compatible = "marvell,dove-lcd";
639 reg = <0x810000 0x1000>;
640 interrupts = <46>;
641 status = "disabled";
642 };
643
644 lcd0: lcd-controller@820000 {
645 compatible = "marvell,dove-lcd";
646 reg = <0x820000 0x1000>;
647 interrupts = <47>;
648 status = "disabled";
649 };
650 };
651 };
652 };
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