2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "dra74x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
13 #include <dt-bindings/input/input.h>
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
20 device_type = "memory";
21 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
28 evm_3v3_sd: fixedregulator-sd {
29 compatible = "regulator-fixed";
30 regulator-name = "evm_3v3_sd";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
34 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
37 evm_3v3_sw: fixedregulator-evm_3v3_sw {
38 compatible = "regulator-fixed";
39 regulator-name = "evm_3v3_sw";
40 vin-supply = <&sysen1>;
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
45 aic_dvdd: fixedregulator-aic_dvdd {
47 compatible = "regulator-fixed";
48 regulator-name = "aic_dvdd";
49 vin-supply = <&evm_3v3_sw>;
50 regulator-min-microvolt = <1800000>;
51 regulator-max-microvolt = <1800000>;
54 extcon_usb1: extcon_usb1 {
55 compatible = "linux,extcon-usb-gpio";
56 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
59 extcon_usb2: extcon_usb2 {
60 compatible = "linux,extcon-usb-gpio";
61 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
64 vtt_fixed: fixedregulator-vtt {
65 compatible = "regulator-fixed";
66 regulator-name = "vtt_fixed";
67 regulator-min-microvolt = <1350000>;
68 regulator-max-microvolt = <1350000>;
72 vin-supply = <&sysen2>;
73 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
77 compatible = "simple-audio-card";
78 simple-audio-card,name = "DRA7xx-EVM";
79 simple-audio-card,widgets =
80 "Headphone", "Headphone Jack",
82 "Microphone", "Mic Jack",
84 simple-audio-card,routing =
85 "Headphone Jack", "HPLOUT",
86 "Headphone Jack", "HPROUT",
91 "Mic Jack", "Mic Bias",
94 simple-audio-card,format = "dsp_b";
95 simple-audio-card,bitclock-master = <&sound0_master>;
96 simple-audio-card,frame-master = <&sound0_master>;
97 simple-audio-card,bitclock-inversion;
99 sound0_master: simple-audio-card,cpu {
100 sound-dai = <&mcasp3>;
101 system-clock-frequency = <5644800>;
104 simple-audio-card,codec {
105 sound-dai = <&tlv320aic3106>;
106 clocks = <&atl_clkin2_ck>;
111 compatible = "gpio-leds";
114 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
115 default-state = "off";
120 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
121 default-state = "off";
126 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
127 default-state = "off";
132 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
133 default-state = "off";
138 compatible = "gpio-keys";
139 #address-cells = <1>;
145 linux,code = <BTN_0>;
146 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
151 linux,code = <BTN_1>;
152 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
158 dcan1_pins_default: dcan1_pins_default {
159 pinctrl-single,pins = <
160 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
161 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
165 dcan1_pins_sleep: dcan1_pins_sleep {
166 pinctrl-single,pins = <
167 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
168 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
172 mmc1_pins_default: mmc1_pins_default {
173 pinctrl-single,pins = <
174 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
175 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
176 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
177 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
178 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
179 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
180 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
184 mmc2_pins_default: mmc2_pins_default {
185 pinctrl-single,pins = <
186 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
187 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
188 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
189 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
190 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
191 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
192 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
193 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
194 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
195 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
202 clock-frequency = <400000>;
204 tps659038: tps659038@58 {
205 compatible = "ti,tps659038";
209 compatible = "ti,tps659038-pmic";
212 smps123_reg: smps123 {
214 regulator-name = "smps123";
215 regulator-min-microvolt = < 850000>;
216 regulator-max-microvolt = <1250000>;
223 regulator-name = "smps45";
224 regulator-min-microvolt = < 850000>;
225 regulator-max-microvolt = <1250000>;
231 /* VDD_GPU - over VDD_SMPS6 */
232 regulator-name = "smps6";
233 regulator-min-microvolt = <850000>;
234 regulator-max-microvolt = <1250000>;
241 regulator-name = "smps7";
242 regulator-min-microvolt = <850000>;
243 regulator-max-microvolt = <1150000>;
250 regulator-name = "smps8";
251 regulator-min-microvolt = < 850000>;
252 regulator-max-microvolt = <1250000>;
259 regulator-name = "smps9";
260 regulator-min-microvolt = <1800000>;
261 regulator-max-microvolt = <1800000>;
267 /* LDO1_OUT --> SDIO */
268 regulator-name = "ldo1";
269 regulator-min-microvolt = <1800000>;
270 regulator-max-microvolt = <3300000>;
277 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
278 regulator-name = "ldo2";
279 regulator-min-microvolt = <3300000>;
280 regulator-max-microvolt = <3300000>;
287 regulator-name = "ldo3";
288 regulator-min-microvolt = <1800000>;
289 regulator-max-microvolt = <1800000>;
296 regulator-name = "ldo9";
297 regulator-min-microvolt = <1050000>;
298 regulator-max-microvolt = <1050000>;
301 regulator-allow-bypass;
306 regulator-name = "ldoln";
307 regulator-min-microvolt = <1800000>;
308 regulator-max-microvolt = <1800000>;
314 /* VDDA_3V_USB: VDDA_USBHS33 */
315 regulator-name = "ldousb";
316 regulator-min-microvolt = <3300000>;
317 regulator-max-microvolt = <3300000>;
321 /* REGEN1 is unused */
324 /* Needed for PMIC internal resources */
325 regulator-name = "regen2";
330 /* REGEN3 is unused */
334 regulator-name = "sysen1";
341 regulator-name = "sysen2";
350 compatible = "ti,pcf8575", "nxp,pcf8575";
354 interrupt-parent = <&gpio6>;
355 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
360 pcf_gpio_21: gpio@21 {
361 compatible = "ti,pcf8575", "nxp,pcf8575";
363 lines-initial-states = <0x1408>;
366 interrupt-parent = <&gpio6>;
367 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
372 tlv320aic3106: tlv320aic3106@19 {
373 #sound-dai-cells = <0>;
374 compatible = "ti,tlv320aic3106";
376 adc-settle-ms = <40>;
377 ai3x-micbias-vg = <1>; /* 2.0V */
381 AVDD-supply = <&evm_3v3_sw>;
382 IOVDD-supply = <&evm_3v3_sw>;
383 DRVDD-supply = <&evm_3v3_sw>;
384 DVDD-supply = <&aic_dvdd>;
390 clock-frequency = <400000>;
393 compatible = "ti,pcf8575", "nxp,pcf8575";
398 /* vin6_sel_s0: high: VIN6, low: audio */
400 gpios = <1 GPIO_ACTIVE_HIGH>;
402 line-name = "vin6_sel_s0";
409 clock-frequency = <400000>;
422 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
423 <&dra7_pmx_core 0x3e0>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&mmc1_pins_default>;
438 vmmc-supply = <&evm_3v3_sd>;
439 vmmc_aux-supply = <&ldo1_reg>;
442 * SDCD signal is not being used here - using the fact that GPIO mode
443 * is always hardwired.
445 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&mmc2_pins_default>;
452 vmmc-supply = <&evm_3v3_sw>;
457 cpu0-supply = <&smps123_reg>;
463 spi-max-frequency = <76800000>;
465 compatible = "s25fl256s1";
466 spi-max-frequency = <76800000>;
468 spi-tx-bus-width = <1>;
469 spi-rx-bus-width = <4>;
470 #address-cells = <1>;
473 /* MTD partition table.
474 * The ROM checks the first four physical blocks
475 * for a valid file to boot and the flash here is
480 reg = <0x00000000 0x000010000>;
483 label = "QSPI.SPL.backup1";
484 reg = <0x00010000 0x00010000>;
487 label = "QSPI.SPL.backup2";
488 reg = <0x00020000 0x00010000>;
491 label = "QSPI.SPL.backup3";
492 reg = <0x00030000 0x00010000>;
495 label = "QSPI.u-boot";
496 reg = <0x00040000 0x00100000>;
499 label = "QSPI.u-boot-spl-os";
500 reg = <0x00140000 0x00080000>;
503 label = "QSPI.u-boot-env";
504 reg = <0x001c0000 0x00010000>;
507 label = "QSPI.u-boot-env.backup1";
508 reg = <0x001d0000 0x0010000>;
511 label = "QSPI.kernel";
512 reg = <0x001e0000 0x0800000>;
515 label = "QSPI.file-system";
516 reg = <0x009e0000 0x01620000>;
522 extcon = <&extcon_usb1>;
526 extcon = <&extcon_usb2>;
530 dr_mode = "peripheral";
543 * For the existing IOdelay configuration via U-Boot we don't
544 * support NAND on dra7-evm. Keep it disabled. Enabling it
545 * requires a different configuration by U-Boot.
548 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
550 compatible = "ti,omap2-nand";
551 reg = <0 0 4>; /* device IO registers */
552 interrupt-parent = <&gpmc>;
553 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
554 <1 IRQ_TYPE_NONE>; /* termcount */
555 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
556 ti,nand-ecc-opt = "bch8";
558 nand-bus-width = <16>;
559 gpmc,device-width = <2>;
560 gpmc,sync-clk-ps = <0>;
562 gpmc,cs-rd-off-ns = <80>;
563 gpmc,cs-wr-off-ns = <80>;
564 gpmc,adv-on-ns = <0>;
565 gpmc,adv-rd-off-ns = <60>;
566 gpmc,adv-wr-off-ns = <60>;
567 gpmc,we-on-ns = <10>;
568 gpmc,we-off-ns = <50>;
570 gpmc,oe-off-ns = <40>;
571 gpmc,access-ns = <40>;
572 gpmc,wr-access-ns = <80>;
573 gpmc,rd-cycle-ns = <80>;
574 gpmc,wr-cycle-ns = <80>;
575 gpmc,bus-turnaround-ns = <0>;
576 gpmc,cycle2cycle-delay-ns = <0>;
577 gpmc,clk-activation-ns = <0>;
578 gpmc,wr-data-mux-bus-ns = <0>;
579 /* MTD partition table */
580 /* All SPL-* partitions are sized to minimal length
581 * which can be independently programmable. For
582 * NAND flash this is equal to size of erase-block */
583 #address-cells = <1>;
587 reg = <0x00000000 0x000020000>;
590 label = "NAND.SPL.backup1";
591 reg = <0x00020000 0x00020000>;
594 label = "NAND.SPL.backup2";
595 reg = <0x00040000 0x00020000>;
598 label = "NAND.SPL.backup3";
599 reg = <0x00060000 0x00020000>;
602 label = "NAND.u-boot-spl-os";
603 reg = <0x00080000 0x00040000>;
606 label = "NAND.u-boot";
607 reg = <0x000c0000 0x00100000>;
610 label = "NAND.u-boot-env";
611 reg = <0x001c0000 0x00020000>;
614 label = "NAND.u-boot-env.backup1";
615 reg = <0x001e0000 0x00020000>;
618 label = "NAND.kernel";
619 reg = <0x00200000 0x00800000>;
622 label = "NAND.file-system";
623 reg = <0x00a00000 0x0f600000>;
629 phy-supply = <&ldousb_reg>;
633 phy-supply = <&ldousb_reg>;
647 phy_id = <&davinci_mdio>, <2>;
649 dual_emac_res_vlan = <1>;
653 phy_id = <&davinci_mdio>, <3>;
655 dual_emac_res_vlan = <2>;
660 pinctrl-names = "default", "sleep", "active";
661 pinctrl-0 = <&dcan1_pins_sleep>;
662 pinctrl-1 = <&dcan1_pins_sleep>;
663 pinctrl-2 = <&dcan1_pins_default>;
667 assigned-clocks = <&abe_dpll_sys_clk_mux>,
672 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
673 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
678 bws = <DRA7_ATL_WS_MCASP2_FSX>;
679 aws = <DRA7_ATL_WS_MCASP3_FSX>;
684 #sound-dai-cells = <0>;
686 assigned-clocks = <&mcasp3_ahclkx_mux>;
687 assigned-clock-parents = <&atl_clkin2_ck>;
691 op-mode = <0>; /* MCASP_IIS_MODE */
694 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
703 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
706 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
713 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
716 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {