2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
15 #define MAX_SOURCES 400
16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
22 compatible = "ti,dra7xx";
23 interrupt-parent = <&gic>;
40 compatible = "arm,armv7-timer";
41 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
42 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
43 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
47 gic: interrupt-controller@48211000 {
48 compatible = "arm,cortex-a15-gic";
50 #interrupt-cells = <3>;
51 arm,routable-irqs = <192>;
52 reg = <0x48211000 0x1000>,
56 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
60 * The soc node represents the soc top level view. It is used for IPs
61 * that are not memory mapped in the MPU view or for the MPU itself.
64 compatible = "ti,omap-infra";
66 compatible = "ti,omap5-mpu";
72 * XXX: Use a flat representation of the SOC interconnect.
73 * The real OMAP interconnect network is quite complex.
74 * Since it will not bring real advantage to represent that in DT for
75 * the moment, just use a fake OCP bus entry to represent the whole bus
79 compatible = "ti,dra7-l3-noc", "simple-bus";
83 ti,hwmods = "l3_main_1", "l3_main_2";
84 reg = <0x44000000 0x1000000>,
86 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
90 compatible = "ti,dra7-prm";
91 reg = <0x4ae06000 0x3000>;
98 prm_clockdomains: clockdomains {
103 compatible = "simple-bus";
105 #address-cells = <1>;
106 ranges = <0x51000000 0x51000000 0x3000
107 0x0 0x20000000 0x10000000>;
109 compatible = "ti,dra7-pcie";
110 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
111 reg-names = "rc_dbics", "ti_conf", "config";
112 interrupts = <0 232 0x4>, <0 233 0x4>;
113 #address-cells = <3>;
116 ranges = <0x81000000 0 0 0x03000 0 0x00010000
117 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
118 #interrupt-cells = <1>;
122 phy-names = "pcie-phy0";
123 interrupt-map-mask = <0 0 0 7>;
124 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
125 <0 0 0 2 &pcie1_intc 2>,
126 <0 0 0 3 &pcie1_intc 3>,
127 <0 0 0 4 &pcie1_intc 4>;
128 pcie1_intc: interrupt-controller {
129 interrupt-controller;
130 #address-cells = <0>;
131 #interrupt-cells = <1>;
137 compatible = "simple-bus";
139 #address-cells = <1>;
140 ranges = <0x51800000 0x51800000 0x3000
141 0x0 0x30000000 0x10000000>;
144 compatible = "ti,dra7-pcie";
145 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
146 reg-names = "rc_dbics", "ti_conf", "config";
147 interrupts = <0 355 0x4>, <0 356 0x4>;
148 #address-cells = <3>;
151 ranges = <0x81000000 0 0 0x03000 0 0x00010000
152 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
153 #interrupt-cells = <1>;
157 phy-names = "pcie-phy0";
158 interrupt-map-mask = <0 0 0 7>;
159 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
160 <0 0 0 2 &pcie2_intc 2>,
161 <0 0 0 3 &pcie2_intc 3>,
162 <0 0 0 4 &pcie2_intc 4>;
163 pcie2_intc: interrupt-controller {
164 interrupt-controller;
165 #address-cells = <0>;
166 #interrupt-cells = <1>;
171 cm_core_aon: cm_core_aon@4a005000 {
172 compatible = "ti,dra7-cm-core-aon";
173 reg = <0x4a005000 0x2000>;
175 cm_core_aon_clocks: clocks {
176 #address-cells = <1>;
180 cm_core_aon_clockdomains: clockdomains {
184 cm_core: cm_core@4a008000 {
185 compatible = "ti,dra7-cm-core";
186 reg = <0x4a008000 0x3000>;
188 cm_core_clocks: clocks {
189 #address-cells = <1>;
193 cm_core_clockdomains: clockdomains {
197 counter32k: counter@4ae04000 {
198 compatible = "ti,omap-counter32k";
199 reg = <0x4ae04000 0x40>;
200 ti,hwmods = "counter_32k";
203 dra7_ctrl_general: tisyscon@4a002e00 {
204 compatible = "syscon";
205 reg = <0x4a002e00 0x7c>;
208 pbias_regulator: pbias_regulator {
209 compatible = "ti,pbias-omap";
211 syscon = <&dra7_ctrl_general>;
212 pbias_mmc_reg: pbias_mmc_omap5 {
213 regulator-name = "pbias_mmc_omap5";
214 regulator-min-microvolt = <1800000>;
215 regulator-max-microvolt = <3000000>;
219 dra7_pmx_core: pinmux@4a003400 {
220 compatible = "pinctrl-single";
221 reg = <0x4a003400 0x0464>;
222 #address-cells = <1>;
224 pinctrl-single,register-width = <32>;
225 pinctrl-single,function-mask = <0x3fffffff>;
228 sdma: dma-controller@4a056000 {
229 compatible = "ti,omap4430-sdma";
230 reg = <0x4a056000 0x1000>;
231 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
236 #dma-channels = <32>;
237 #dma-requests = <127>;
240 gpio1: gpio@4ae10000 {
241 compatible = "ti,omap4-gpio";
242 reg = <0x4ae10000 0x200>;
243 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
247 interrupt-controller;
248 #interrupt-cells = <1>;
251 gpio2: gpio@48055000 {
252 compatible = "ti,omap4-gpio";
253 reg = <0x48055000 0x200>;
254 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
258 interrupt-controller;
259 #interrupt-cells = <1>;
262 gpio3: gpio@48057000 {
263 compatible = "ti,omap4-gpio";
264 reg = <0x48057000 0x200>;
265 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-controller;
270 #interrupt-cells = <1>;
273 gpio4: gpio@48059000 {
274 compatible = "ti,omap4-gpio";
275 reg = <0x48059000 0x200>;
276 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-controller;
281 #interrupt-cells = <1>;
284 gpio5: gpio@4805b000 {
285 compatible = "ti,omap4-gpio";
286 reg = <0x4805b000 0x200>;
287 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
291 interrupt-controller;
292 #interrupt-cells = <1>;
295 gpio6: gpio@4805d000 {
296 compatible = "ti,omap4-gpio";
297 reg = <0x4805d000 0x200>;
298 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-controller;
303 #interrupt-cells = <1>;
306 gpio7: gpio@48051000 {
307 compatible = "ti,omap4-gpio";
308 reg = <0x48051000 0x200>;
309 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
313 interrupt-controller;
314 #interrupt-cells = <1>;
317 gpio8: gpio@48053000 {
318 compatible = "ti,omap4-gpio";
319 reg = <0x48053000 0x200>;
320 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
324 interrupt-controller;
325 #interrupt-cells = <1>;
328 uart1: serial@4806a000 {
329 compatible = "ti,omap4-uart";
330 reg = <0x4806a000 0x100>;
331 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
333 clock-frequency = <48000000>;
337 uart2: serial@4806c000 {
338 compatible = "ti,omap4-uart";
339 reg = <0x4806c000 0x100>;
340 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
342 clock-frequency = <48000000>;
346 uart3: serial@48020000 {
347 compatible = "ti,omap4-uart";
348 reg = <0x48020000 0x100>;
349 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
351 clock-frequency = <48000000>;
355 uart4: serial@4806e000 {
356 compatible = "ti,omap4-uart";
357 reg = <0x4806e000 0x100>;
358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
360 clock-frequency = <48000000>;
364 uart5: serial@48066000 {
365 compatible = "ti,omap4-uart";
366 reg = <0x48066000 0x100>;
367 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
369 clock-frequency = <48000000>;
373 uart6: serial@48068000 {
374 compatible = "ti,omap4-uart";
375 reg = <0x48068000 0x100>;
376 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
378 clock-frequency = <48000000>;
382 uart7: serial@48420000 {
383 compatible = "ti,omap4-uart";
384 reg = <0x48420000 0x100>;
385 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
387 clock-frequency = <48000000>;
391 uart8: serial@48422000 {
392 compatible = "ti,omap4-uart";
393 reg = <0x48422000 0x100>;
394 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
396 clock-frequency = <48000000>;
400 uart9: serial@48424000 {
401 compatible = "ti,omap4-uart";
402 reg = <0x48424000 0x100>;
403 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
405 clock-frequency = <48000000>;
409 uart10: serial@4ae2b000 {
410 compatible = "ti,omap4-uart";
411 reg = <0x4ae2b000 0x100>;
412 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
413 ti,hwmods = "uart10";
414 clock-frequency = <48000000>;
418 timer1: timer@4ae18000 {
419 compatible = "ti,omap5430-timer";
420 reg = <0x4ae18000 0x80>;
421 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
422 ti,hwmods = "timer1";
426 timer2: timer@48032000 {
427 compatible = "ti,omap5430-timer";
428 reg = <0x48032000 0x80>;
429 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
430 ti,hwmods = "timer2";
433 timer3: timer@48034000 {
434 compatible = "ti,omap5430-timer";
435 reg = <0x48034000 0x80>;
436 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
437 ti,hwmods = "timer3";
440 timer4: timer@48036000 {
441 compatible = "ti,omap5430-timer";
442 reg = <0x48036000 0x80>;
443 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
444 ti,hwmods = "timer4";
447 timer5: timer@48820000 {
448 compatible = "ti,omap5430-timer";
449 reg = <0x48820000 0x80>;
450 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
451 ti,hwmods = "timer5";
455 timer6: timer@48822000 {
456 compatible = "ti,omap5430-timer";
457 reg = <0x48822000 0x80>;
458 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
459 ti,hwmods = "timer6";
464 timer7: timer@48824000 {
465 compatible = "ti,omap5430-timer";
466 reg = <0x48824000 0x80>;
467 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
468 ti,hwmods = "timer7";
472 timer8: timer@48826000 {
473 compatible = "ti,omap5430-timer";
474 reg = <0x48826000 0x80>;
475 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
476 ti,hwmods = "timer8";
481 timer9: timer@4803e000 {
482 compatible = "ti,omap5430-timer";
483 reg = <0x4803e000 0x80>;
484 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
485 ti,hwmods = "timer9";
488 timer10: timer@48086000 {
489 compatible = "ti,omap5430-timer";
490 reg = <0x48086000 0x80>;
491 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
492 ti,hwmods = "timer10";
495 timer11: timer@48088000 {
496 compatible = "ti,omap5430-timer";
497 reg = <0x48088000 0x80>;
498 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
499 ti,hwmods = "timer11";
503 timer13: timer@48828000 {
504 compatible = "ti,omap5430-timer";
505 reg = <0x48828000 0x80>;
506 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
507 ti,hwmods = "timer13";
511 timer14: timer@4882a000 {
512 compatible = "ti,omap5430-timer";
513 reg = <0x4882a000 0x80>;
514 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
515 ti,hwmods = "timer14";
519 timer15: timer@4882c000 {
520 compatible = "ti,omap5430-timer";
521 reg = <0x4882c000 0x80>;
522 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
523 ti,hwmods = "timer15";
527 timer16: timer@4882e000 {
528 compatible = "ti,omap5430-timer";
529 reg = <0x4882e000 0x80>;
530 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
531 ti,hwmods = "timer16";
536 compatible = "ti,omap4-wdt";
537 reg = <0x4ae14000 0x80>;
538 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
539 ti,hwmods = "wd_timer2";
542 hwspinlock: spinlock@4a0f6000 {
543 compatible = "ti,omap4-hwspinlock";
544 reg = <0x4a0f6000 0x1000>;
545 ti,hwmods = "spinlock";
550 compatible = "ti,omap5-dmm";
551 reg = <0x4e000000 0x800>;
552 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
557 compatible = "ti,omap4-i2c";
558 reg = <0x48070000 0x100>;
559 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>;
567 compatible = "ti,omap4-i2c";
568 reg = <0x48072000 0x100>;
569 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
570 #address-cells = <1>;
577 compatible = "ti,omap4-i2c";
578 reg = <0x48060000 0x100>;
579 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
580 #address-cells = <1>;
587 compatible = "ti,omap4-i2c";
588 reg = <0x4807a000 0x100>;
589 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
590 #address-cells = <1>;
597 compatible = "ti,omap4-i2c";
598 reg = <0x4807c000 0x100>;
599 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
600 #address-cells = <1>;
607 compatible = "ti,omap4-hsmmc";
608 reg = <0x4809c000 0x400>;
609 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
612 ti,needs-special-reset;
613 dmas = <&sdma 61>, <&sdma 62>;
614 dma-names = "tx", "rx";
616 pbias-supply = <&pbias_mmc_reg>;
620 compatible = "ti,omap4-hsmmc";
621 reg = <0x480b4000 0x400>;
622 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
624 ti,needs-special-reset;
625 dmas = <&sdma 47>, <&sdma 48>;
626 dma-names = "tx", "rx";
631 compatible = "ti,omap4-hsmmc";
632 reg = <0x480ad000 0x400>;
633 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
635 ti,needs-special-reset;
636 dmas = <&sdma 77>, <&sdma 78>;
637 dma-names = "tx", "rx";
642 compatible = "ti,omap4-hsmmc";
643 reg = <0x480d1000 0x400>;
644 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
646 ti,needs-special-reset;
647 dmas = <&sdma 57>, <&sdma 58>;
648 dma-names = "tx", "rx";
652 abb_mpu: regulator-abb-mpu {
653 compatible = "ti,abb-v3";
654 regulator-name = "abb_mpu";
655 #address-cells = <0>;
657 clocks = <&sys_clkin1>;
658 ti,settling-time = <50>;
659 ti,clock-cycles = <16>;
661 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
662 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
664 reg-names = "setup-address", "control-address",
665 "int-address", "efuse-address",
667 ti,tranxdone-status-mask = <0x80>;
668 /* LDOVBBMPU_FBB_MUX_CTRL */
669 ti,ldovbb-override-mask = <0x400>;
670 /* LDOVBBMPU_FBB_VSET_OUT */
671 ti,ldovbb-vset-mask = <0x1F>;
674 * NOTE: only FBB mode used but actual vset will
675 * determine final biasing
678 /*uV ABB efuse rbb_m fbb_m vset_m*/
679 1060000 0 0x0 0 0x02000000 0x01F00000
680 1160000 0 0x4 0 0x02000000 0x01F00000
681 1210000 0 0x8 0 0x02000000 0x01F00000
685 abb_ivahd: regulator-abb-ivahd {
686 compatible = "ti,abb-v3";
687 regulator-name = "abb_ivahd";
688 #address-cells = <0>;
690 clocks = <&sys_clkin1>;
691 ti,settling-time = <50>;
692 ti,clock-cycles = <16>;
694 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
695 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
697 reg-names = "setup-address", "control-address",
698 "int-address", "efuse-address",
700 ti,tranxdone-status-mask = <0x40000000>;
701 /* LDOVBBIVA_FBB_MUX_CTRL */
702 ti,ldovbb-override-mask = <0x400>;
703 /* LDOVBBIVA_FBB_VSET_OUT */
704 ti,ldovbb-vset-mask = <0x1F>;
707 * NOTE: only FBB mode used but actual vset will
708 * determine final biasing
711 /*uV ABB efuse rbb_m fbb_m vset_m*/
712 1055000 0 0x0 0 0x02000000 0x01F00000
713 1150000 0 0x4 0 0x02000000 0x01F00000
714 1250000 0 0x8 0 0x02000000 0x01F00000
718 abb_dspeve: regulator-abb-dspeve {
719 compatible = "ti,abb-v3";
720 regulator-name = "abb_dspeve";
721 #address-cells = <0>;
723 clocks = <&sys_clkin1>;
724 ti,settling-time = <50>;
725 ti,clock-cycles = <16>;
727 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
728 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
730 reg-names = "setup-address", "control-address",
731 "int-address", "efuse-address",
733 ti,tranxdone-status-mask = <0x20000000>;
734 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
735 ti,ldovbb-override-mask = <0x400>;
736 /* LDOVBBDSPEVE_FBB_VSET_OUT */
737 ti,ldovbb-vset-mask = <0x1F>;
740 * NOTE: only FBB mode used but actual vset will
741 * determine final biasing
744 /*uV ABB efuse rbb_m fbb_m vset_m*/
745 1055000 0 0x0 0 0x02000000 0x01F00000
746 1150000 0 0x4 0 0x02000000 0x01F00000
747 1250000 0 0x8 0 0x02000000 0x01F00000
751 abb_gpu: regulator-abb-gpu {
752 compatible = "ti,abb-v3";
753 regulator-name = "abb_gpu";
754 #address-cells = <0>;
756 clocks = <&sys_clkin1>;
757 ti,settling-time = <50>;
758 ti,clock-cycles = <16>;
760 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
761 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
763 reg-names = "setup-address", "control-address",
764 "int-address", "efuse-address",
766 ti,tranxdone-status-mask = <0x10000000>;
767 /* LDOVBBGPU_FBB_MUX_CTRL */
768 ti,ldovbb-override-mask = <0x400>;
769 /* LDOVBBGPU_FBB_VSET_OUT */
770 ti,ldovbb-vset-mask = <0x1F>;
773 * NOTE: only FBB mode used but actual vset will
774 * determine final biasing
777 /*uV ABB efuse rbb_m fbb_m vset_m*/
778 1090000 0 0x0 0 0x02000000 0x01F00000
779 1210000 0 0x4 0 0x02000000 0x01F00000
780 1280000 0 0x8 0 0x02000000 0x01F00000
784 mcspi1: spi@48098000 {
785 compatible = "ti,omap4-mcspi";
786 reg = <0x48098000 0x200>;
787 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>;
790 ti,hwmods = "mcspi1";
800 dma-names = "tx0", "rx0", "tx1", "rx1",
801 "tx2", "rx2", "tx3", "rx3";
805 mcspi2: spi@4809a000 {
806 compatible = "ti,omap4-mcspi";
807 reg = <0x4809a000 0x200>;
808 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
809 #address-cells = <1>;
811 ti,hwmods = "mcspi2";
817 dma-names = "tx0", "rx0", "tx1", "rx1";
821 mcspi3: spi@480b8000 {
822 compatible = "ti,omap4-mcspi";
823 reg = <0x480b8000 0x200>;
824 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
825 #address-cells = <1>;
827 ti,hwmods = "mcspi3";
829 dmas = <&sdma 15>, <&sdma 16>;
830 dma-names = "tx0", "rx0";
834 mcspi4: spi@480ba000 {
835 compatible = "ti,omap4-mcspi";
836 reg = <0x480ba000 0x200>;
837 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
838 #address-cells = <1>;
840 ti,hwmods = "mcspi4";
842 dmas = <&sdma 70>, <&sdma 71>;
843 dma-names = "tx0", "rx0";
847 qspi: qspi@4b300000 {
848 compatible = "ti,dra7xxx-qspi";
849 reg = <0x4b300000 0x100>;
850 reg-names = "qspi_base";
851 #address-cells = <1>;
854 clocks = <&qspi_gfclk_div>;
857 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
861 omap_control_sata: control-phy@4a002374 {
862 compatible = "ti,control-phy-pipe3";
863 reg = <0x4a002374 0x4>;
865 clocks = <&sys_clkin1>;
866 clock-names = "sysclk";
871 compatible = "ti,omap-ocp2scp";
872 #address-cells = <1>;
875 reg = <0x4a090000 0x20>;
876 ti,hwmods = "ocp2scp3";
877 sata_phy: phy@4A096000 {
878 compatible = "ti,phy-pipe3-sata";
879 reg = <0x4A096000 0x80>, /* phy_rx */
880 <0x4A096400 0x64>, /* phy_tx */
881 <0x4A096800 0x40>; /* pll_ctrl */
882 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
883 ctrl-module = <&omap_control_sata>;
884 clocks = <&sys_clkin1>;
885 clock-names = "sysclk";
889 pcie1_phy: pciephy@4a094000 {
890 compatible = "ti,phy-pipe3-pcie";
891 reg = <0x4a094000 0x80>, /* phy_rx */
892 <0x4a094400 0x64>; /* phy_tx */
893 reg-names = "phy_rx", "phy_tx";
894 ctrl-module = <&omap_control_pcie1phy>;
895 clocks = <&dpll_pcie_ref_ck>,
896 <&dpll_pcie_ref_m2ldo_ck>,
897 <&optfclk_pciephy1_32khz>,
898 <&optfclk_pciephy1_clk>,
899 <&optfclk_pciephy1_div_clk>,
900 <&optfclk_pciephy_div>;
901 clock-names = "dpll_ref", "dpll_ref_m2",
903 "div-clk", "phy-div";
906 ti,hwmods = "pcie1-phy";
909 pcie2_phy: pciephy@4a095000 {
910 compatible = "ti,phy-pipe3-pcie";
911 reg = <0x4a095000 0x80>, /* phy_rx */
912 <0x4a095400 0x64>; /* phy_tx */
913 reg-names = "phy_rx", "phy_tx";
914 ctrl-module = <&omap_control_pcie2phy>;
915 clocks = <&dpll_pcie_ref_ck>,
916 <&dpll_pcie_ref_m2ldo_ck>,
917 <&optfclk_pciephy2_32khz>,
918 <&optfclk_pciephy2_clk>,
919 <&optfclk_pciephy2_div_clk>,
920 <&optfclk_pciephy_div>;
921 clock-names = "dpll_ref", "dpll_ref_m2",
923 "div-clk", "phy-div";
925 ti,hwmods = "pcie2-phy";
931 sata: sata@4a141100 {
932 compatible = "snps,dwc-ahci";
933 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
934 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
936 phy-names = "sata-phy";
937 clocks = <&sata_ref_clk>;
941 omap_control_pcie1phy: control-phy@0x4a003c40 {
942 compatible = "ti,control-phy-pcie";
943 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
944 reg-names = "power", "control_sma", "pcie_pcs";
945 clocks = <&sys_clkin1>;
946 clock-names = "sysclk";
949 omap_control_pcie2phy: control-pcie@0x4a003c44 {
950 compatible = "ti,control-phy-pcie";
951 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
952 reg-names = "power", "control_sma", "pcie_pcs";
953 clocks = <&sys_clkin1>;
954 clock-names = "sysclk";
958 omap_control_usb2phy1: control-phy@4a002300 {
959 compatible = "ti,control-phy-usb2";
960 reg = <0x4a002300 0x4>;
964 omap_control_usb3phy1: control-phy@4a002370 {
965 compatible = "ti,control-phy-pipe3";
966 reg = <0x4a002370 0x4>;
970 omap_control_usb2phy2: control-phy@0x4a002e74 {
971 compatible = "ti,control-phy-usb2-dra7";
972 reg = <0x4a002e74 0x4>;
978 compatible = "ti,omap-ocp2scp";
979 #address-cells = <1>;
982 reg = <0x4a080000 0x20>;
983 ti,hwmods = "ocp2scp1";
985 usb2_phy1: phy@4a084000 {
986 compatible = "ti,omap-usb2";
987 reg = <0x4a084000 0x400>;
988 ctrl-module = <&omap_control_usb2phy1>;
989 clocks = <&usb_phy1_always_on_clk32k>,
990 <&usb_otg_ss1_refclk960m>;
991 clock-names = "wkupclk",
996 usb2_phy2: phy@4a085000 {
997 compatible = "ti,omap-usb2";
998 reg = <0x4a085000 0x400>;
999 ctrl-module = <&omap_control_usb2phy2>;
1000 clocks = <&usb_phy2_always_on_clk32k>,
1001 <&usb_otg_ss2_refclk960m>;
1002 clock-names = "wkupclk",
1007 usb3_phy1: phy@4a084400 {
1008 compatible = "ti,omap-usb3";
1009 reg = <0x4a084400 0x80>,
1012 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1013 ctrl-module = <&omap_control_usb3phy1>;
1014 clocks = <&usb_phy3_always_on_clk32k>,
1016 <&usb_otg_ss1_refclk960m>;
1017 clock-names = "wkupclk",
1024 omap_dwc3_1@48880000 {
1025 compatible = "ti,dwc3";
1026 ti,hwmods = "usb_otg_ss1";
1027 reg = <0x48880000 0x10000>;
1028 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1029 #address-cells = <1>;
1033 usb1: usb@48890000 {
1034 compatible = "snps,dwc3";
1035 reg = <0x48890000 0x17000>;
1036 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1037 phys = <&usb2_phy1>, <&usb3_phy1>;
1038 phy-names = "usb2-phy", "usb3-phy";
1040 maximum-speed = "super-speed";
1045 omap_dwc3_2@488c0000 {
1046 compatible = "ti,dwc3";
1047 ti,hwmods = "usb_otg_ss2";
1048 reg = <0x488c0000 0x10000>;
1049 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1050 #address-cells = <1>;
1054 usb2: usb@488d0000 {
1055 compatible = "snps,dwc3";
1056 reg = <0x488d0000 0x17000>;
1057 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1058 phys = <&usb2_phy2>;
1059 phy-names = "usb2-phy";
1061 maximum-speed = "high-speed";
1066 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1067 omap_dwc3_3@48900000 {
1068 compatible = "ti,dwc3";
1069 ti,hwmods = "usb_otg_ss3";
1070 reg = <0x48900000 0x10000>;
1071 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1072 #address-cells = <1>;
1076 status = "disabled";
1077 usb3: usb@48910000 {
1078 compatible = "snps,dwc3";
1079 reg = <0x48910000 0x17000>;
1080 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1082 maximum-speed = "high-speed";
1087 omap_dwc3_4@48940000 {
1088 compatible = "ti,dwc3";
1089 ti,hwmods = "usb_otg_ss4";
1090 reg = <0x48940000 0x10000>;
1091 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1092 #address-cells = <1>;
1096 status = "disabled";
1097 usb4: usb@48950000 {
1098 compatible = "snps,dwc3";
1099 reg = <0x48950000 0x17000>;
1100 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1102 maximum-speed = "high-speed";
1108 compatible = "ti,am3352-elm";
1109 reg = <0x48078000 0xfc0>; /* device IO registers */
1110 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1112 status = "disabled";
1115 gpmc: gpmc@50000000 {
1116 compatible = "ti,am3352-gpmc";
1118 reg = <0x50000000 0x37c>; /* device IO registers */
1119 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1121 gpmc,num-waitpins = <2>;
1122 #address-cells = <2>;
1124 status = "disabled";
1128 compatible = "ti,dra7-atl";
1129 reg = <0x4843c000 0x3ff>;
1131 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1132 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1133 clocks = <&atl_gfclk_mux>;
1134 clock-names = "fck";
1135 status = "disabled";
1138 crossbar_mpu: crossbar@4a020000 {
1139 compatible = "ti,irq-crossbar";
1140 reg = <0x4a002a48 0x130>;
1141 ti,max-irqs = <160>;
1142 ti,max-crossbar-sources = <MAX_SOURCES>;
1144 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1145 ti,irqs-skip = <10 133 139 140>;
1146 ti,irqs-safe-map = <0>;
1151 /include/ "dra7xx-clocks.dtsi"