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Merge branch 'for-next' into for-linus
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / dra7.dtsi
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
13
14 #define MAX_SOURCES 400
15
16 / {
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 compatible = "ti,dra7xx";
21 interrupt-parent = <&crossbar_mpu>;
22 chosen { };
23
24 aliases {
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
44 spi0 = &qspi;
45 };
46
47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 interrupt-parent = <&gic>;
54 };
55
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 interrupt-parent = <&gic>;
66 };
67
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
73 interrupt-parent = <&gic>;
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 cpu0: cpu@0 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a15";
83 reg = <0>;
84
85 operating-points-v2 = <&cpu0_opp_table>;
86
87 clocks = <&dpll_mpu_ck>;
88 clock-names = "cpu";
89
90 clock-latency = <300000>; /* From omap-cpufreq driver */
91
92 /* cooling options */
93 #cooling-cells = <2>; /* min followed by max */
94
95 vbb-supply = <&abb_mpu>;
96 };
97 };
98
99 cpu0_opp_table: opp-table {
100 compatible = "operating-points-v2-ti-cpu";
101 syscon = <&scm_wkup>;
102
103 opp_nom-1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <1060000 850000 1150000>,
106 <1060000 850000 1150000>;
107 opp-supported-hw = <0xFF 0x01>;
108 opp-suspend;
109 };
110
111 opp_od-1176000000 {
112 opp-hz = /bits/ 64 <1176000000>;
113 opp-microvolt = <1160000 885000 1160000>,
114 <1160000 885000 1160000>;
115
116 opp-supported-hw = <0xFF 0x02>;
117 };
118
119 opp_high@1500000000 {
120 opp-hz = /bits/ 64 <1500000000>;
121 opp-microvolt = <1210000 950000 1250000>,
122 <1210000 950000 1250000>;
123 opp-supported-hw = <0xFF 0x04>;
124 };
125 };
126
127 /*
128 * The soc node represents the soc top level view. It is used for IPs
129 * that are not memory mapped in the MPU view or for the MPU itself.
130 */
131 soc {
132 compatible = "ti,omap-infra";
133 mpu {
134 compatible = "ti,omap5-mpu";
135 ti,hwmods = "mpu";
136 };
137 };
138
139 /*
140 * XXX: Use a flat representation of the SOC interconnect.
141 * The real OMAP interconnect network is quite complex.
142 * Since it will not bring real advantage to represent that in DT for
143 * the moment, just use a fake OCP bus entry to represent the whole bus
144 * hierarchy.
145 */
146 ocp {
147 compatible = "ti,dra7-l3-noc", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0x0 0x0 0x0 0xc0000000>;
151 ti,hwmods = "l3_main_1", "l3_main_2";
152 reg = <0x0 0x44000000 0x0 0x1000000>,
153 <0x0 0x45000000 0x0 0x1000>;
154 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
155 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
156
157 l4_cfg: interconnect@4a000000 {
158 };
159 l4_wkup: interconnect@4ae00000 {
160 };
161 l4_per1: interconnect@48000000 {
162 };
163 l4_per2: interconnect@48400000 {
164 };
165 l4_per3: interconnect@48800000 {
166 };
167
168 axi@0 {
169 compatible = "simple-bus";
170 #size-cells = <1>;
171 #address-cells = <1>;
172 ranges = <0x51000000 0x51000000 0x3000
173 0x0 0x20000000 0x10000000>;
174 /**
175 * To enable PCI endpoint mode, disable the pcie1_rc
176 * node and enable pcie1_ep mode.
177 */
178 pcie1_rc: pcie@51000000 {
179 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
180 reg-names = "rc_dbics", "ti_conf", "config";
181 interrupts = <0 232 0x4>, <0 233 0x4>;
182 #address-cells = <3>;
183 #size-cells = <2>;
184 device_type = "pci";
185 ranges = <0x81000000 0 0 0x03000 0 0x00010000
186 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
187 bus-range = <0x00 0xff>;
188 #interrupt-cells = <1>;
189 num-lanes = <1>;
190 linux,pci-domain = <0>;
191 ti,hwmods = "pcie1";
192 phys = <&pcie1_phy>;
193 phy-names = "pcie-phy0";
194 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
195 interrupt-map-mask = <0 0 0 7>;
196 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
197 <0 0 0 2 &pcie1_intc 2>,
198 <0 0 0 3 &pcie1_intc 3>,
199 <0 0 0 4 &pcie1_intc 4>;
200 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
201 status = "disabled";
202 pcie1_intc: interrupt-controller {
203 interrupt-controller;
204 #address-cells = <0>;
205 #interrupt-cells = <1>;
206 };
207 };
208
209 pcie1_ep: pcie_ep@51000000 {
210 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
211 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
212 interrupts = <0 232 0x4>;
213 num-lanes = <1>;
214 num-ib-windows = <4>;
215 num-ob-windows = <16>;
216 ti,hwmods = "pcie1";
217 phys = <&pcie1_phy>;
218 phy-names = "pcie-phy0";
219 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
220 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
221 status = "disabled";
222 };
223 };
224
225 axi@1 {
226 compatible = "simple-bus";
227 #size-cells = <1>;
228 #address-cells = <1>;
229 ranges = <0x51800000 0x51800000 0x3000
230 0x0 0x30000000 0x10000000>;
231 status = "disabled";
232 pcie2_rc: pcie@51800000 {
233 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
234 reg-names = "rc_dbics", "ti_conf", "config";
235 interrupts = <0 355 0x4>, <0 356 0x4>;
236 #address-cells = <3>;
237 #size-cells = <2>;
238 device_type = "pci";
239 ranges = <0x81000000 0 0 0x03000 0 0x00010000
240 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
241 bus-range = <0x00 0xff>;
242 #interrupt-cells = <1>;
243 num-lanes = <1>;
244 linux,pci-domain = <1>;
245 ti,hwmods = "pcie2";
246 phys = <&pcie2_phy>;
247 phy-names = "pcie-phy0";
248 interrupt-map-mask = <0 0 0 7>;
249 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
250 <0 0 0 2 &pcie2_intc 2>,
251 <0 0 0 3 &pcie2_intc 3>,
252 <0 0 0 4 &pcie2_intc 4>;
253 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
254 pcie2_intc: interrupt-controller {
255 interrupt-controller;
256 #address-cells = <0>;
257 #interrupt-cells = <1>;
258 };
259 };
260 };
261
262 ocmcram1: ocmcram@40300000 {
263 compatible = "mmio-sram";
264 reg = <0x40300000 0x80000>;
265 ranges = <0x0 0x40300000 0x80000>;
266 #address-cells = <1>;
267 #size-cells = <1>;
268 /*
269 * This is a placeholder for an optional reserved
270 * region for use by secure software. The size
271 * of this region is not known until runtime so it
272 * is set as zero to either be updated to reserve
273 * space or left unchanged to leave all SRAM for use.
274 * On HS parts that that require the reserved region
275 * either the bootloader can update the size to
276 * the required amount or the node can be overridden
277 * from the board dts file for the secure platform.
278 */
279 sram-hs@0 {
280 compatible = "ti,secure-ram";
281 reg = <0x0 0x0>;
282 };
283 };
284
285 /*
286 * NOTE: ocmcram2 and ocmcram3 are not available on all
287 * DRA7xx and AM57xx variants. Confirm availability in
288 * the data manual for the exact part number in use
289 * before enabling these nodes in the board dts file.
290 */
291 ocmcram2: ocmcram@40400000 {
292 status = "disabled";
293 compatible = "mmio-sram";
294 reg = <0x40400000 0x100000>;
295 ranges = <0x0 0x40400000 0x100000>;
296 #address-cells = <1>;
297 #size-cells = <1>;
298 };
299
300 ocmcram3: ocmcram@40500000 {
301 status = "disabled";
302 compatible = "mmio-sram";
303 reg = <0x40500000 0x100000>;
304 ranges = <0x0 0x40500000 0x100000>;
305 #address-cells = <1>;
306 #size-cells = <1>;
307 };
308
309 bandgap: bandgap@4a0021e0 {
310 reg = <0x4a0021e0 0xc
311 0x4a00232c 0xc
312 0x4a002380 0x2c
313 0x4a0023C0 0x3c
314 0x4a002564 0x8
315 0x4a002574 0x50>;
316 compatible = "ti,dra752-bandgap";
317 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
318 #thermal-sensor-cells = <1>;
319 };
320
321 dsp1_system: dsp_system@40d00000 {
322 compatible = "syscon";
323 reg = <0x40d00000 0x100>;
324 };
325
326 dra7_iodelay_core: padconf@4844a000 {
327 compatible = "ti,dra7-iodelay";
328 reg = <0x4844a000 0x0d1c>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 #pinctrl-cells = <2>;
332 };
333
334 edma: edma@43300000 {
335 compatible = "ti,edma3-tpcc";
336 ti,hwmods = "tpcc";
337 reg = <0x43300000 0x100000>;
338 reg-names = "edma3_cc";
339 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "edma3_ccint", "edma3_mperr",
343 "edma3_ccerrint";
344 dma-requests = <64>;
345 #dma-cells = <2>;
346
347 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
348
349 /*
350 * memcpy is disabled, can be enabled with:
351 * ti,edma-memcpy-channels = <20 21>;
352 * for example. Note that these channels need to be
353 * masked in the xbar as well.
354 */
355 };
356
357 edma_tptc0: tptc@43400000 {
358 compatible = "ti,edma3-tptc";
359 ti,hwmods = "tptc0";
360 reg = <0x43400000 0x100000>;
361 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
362 interrupt-names = "edma3_tcerrint";
363 };
364
365 edma_tptc1: tptc@43500000 {
366 compatible = "ti,edma3-tptc";
367 ti,hwmods = "tptc1";
368 reg = <0x43500000 0x100000>;
369 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-names = "edma3_tcerrint";
371 };
372
373 dmm@4e000000 {
374 compatible = "ti,omap5-dmm";
375 reg = <0x4e000000 0x800>;
376 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
377 ti,hwmods = "dmm";
378 };
379
380 target-module@40d01000 {
381 compatible = "ti,sysc-omap2", "ti,sysc";
382 reg = <0x40d01000 0x4>,
383 <0x40d01010 0x4>,
384 <0x40d01014 0x4>;
385 reg-names = "rev", "sysc", "syss";
386 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
387 <SYSC_IDLE_NO>,
388 <SYSC_IDLE_SMART>;
389 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
390 SYSC_OMAP2_SOFTRESET |
391 SYSC_OMAP2_AUTOIDLE)>;
392 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
393 clock-names = "fck";
394 resets = <&prm_dsp1 1>;
395 reset-names = "rstctrl";
396 ranges = <0x0 0x40d01000 0x1000>;
397 #size-cells = <1>;
398 #address-cells = <1>;
399
400 mmu0_dsp1: mmu@0 {
401 compatible = "ti,dra7-dsp-iommu";
402 reg = <0x0 0x100>;
403 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
404 #iommu-cells = <0>;
405 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
406 };
407 };
408
409 target-module@40d02000 {
410 compatible = "ti,sysc-omap2", "ti,sysc";
411 reg = <0x40d02000 0x4>,
412 <0x40d02010 0x4>,
413 <0x40d02014 0x4>;
414 reg-names = "rev", "sysc", "syss";
415 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
416 <SYSC_IDLE_NO>,
417 <SYSC_IDLE_SMART>;
418 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
419 SYSC_OMAP2_SOFTRESET |
420 SYSC_OMAP2_AUTOIDLE)>;
421 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
422 clock-names = "fck";
423 resets = <&prm_dsp1 1>;
424 reset-names = "rstctrl";
425 ranges = <0x0 0x40d02000 0x1000>;
426 #size-cells = <1>;
427 #address-cells = <1>;
428
429 mmu1_dsp1: mmu@0 {
430 compatible = "ti,dra7-dsp-iommu";
431 reg = <0x0 0x100>;
432 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
433 #iommu-cells = <0>;
434 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
435 };
436 };
437
438 target-module@58882000 {
439 compatible = "ti,sysc-omap2", "ti,sysc";
440 reg = <0x58882000 0x4>,
441 <0x58882010 0x4>,
442 <0x58882014 0x4>;
443 reg-names = "rev", "sysc", "syss";
444 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
445 <SYSC_IDLE_NO>,
446 <SYSC_IDLE_SMART>;
447 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
448 SYSC_OMAP2_SOFTRESET |
449 SYSC_OMAP2_AUTOIDLE)>;
450 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
451 clock-names = "fck";
452 resets = <&prm_ipu 2>;
453 reset-names = "rstctrl";
454 #address-cells = <1>;
455 #size-cells = <1>;
456 ranges = <0x0 0x58882000 0x100>;
457
458 mmu_ipu1: mmu@0 {
459 compatible = "ti,dra7-iommu";
460 reg = <0x0 0x100>;
461 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
462 #iommu-cells = <0>;
463 ti,iommu-bus-err-back;
464 };
465 };
466
467 target-module@55082000 {
468 compatible = "ti,sysc-omap2", "ti,sysc";
469 reg = <0x55082000 0x4>,
470 <0x55082010 0x4>,
471 <0x55082014 0x4>;
472 reg-names = "rev", "sysc", "syss";
473 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
474 <SYSC_IDLE_NO>,
475 <SYSC_IDLE_SMART>;
476 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
477 SYSC_OMAP2_SOFTRESET |
478 SYSC_OMAP2_AUTOIDLE)>;
479 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
480 clock-names = "fck";
481 resets = <&prm_core 2>;
482 reset-names = "rstctrl";
483 #address-cells = <1>;
484 #size-cells = <1>;
485 ranges = <0x0 0x55082000 0x100>;
486
487 mmu_ipu2: mmu@0 {
488 compatible = "ti,dra7-iommu";
489 reg = <0x0 0x100>;
490 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
491 #iommu-cells = <0>;
492 ti,iommu-bus-err-back;
493 };
494 };
495
496 abb_mpu: regulator-abb-mpu {
497 compatible = "ti,abb-v3";
498 regulator-name = "abb_mpu";
499 #address-cells = <0>;
500 #size-cells = <0>;
501 clocks = <&sys_clkin1>;
502 ti,settling-time = <50>;
503 ti,clock-cycles = <16>;
504
505 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
506 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
507 <0x4ae0c158 0x4>;
508 reg-names = "setup-address", "control-address",
509 "int-address", "efuse-address",
510 "ldo-address";
511 ti,tranxdone-status-mask = <0x80>;
512 /* LDOVBBMPU_FBB_MUX_CTRL */
513 ti,ldovbb-override-mask = <0x400>;
514 /* LDOVBBMPU_FBB_VSET_OUT */
515 ti,ldovbb-vset-mask = <0x1F>;
516
517 /*
518 * NOTE: only FBB mode used but actual vset will
519 * determine final biasing
520 */
521 ti,abb_info = <
522 /*uV ABB efuse rbb_m fbb_m vset_m*/
523 1060000 0 0x0 0 0x02000000 0x01F00000
524 1160000 0 0x4 0 0x02000000 0x01F00000
525 1210000 0 0x8 0 0x02000000 0x01F00000
526 >;
527 };
528
529 abb_ivahd: regulator-abb-ivahd {
530 compatible = "ti,abb-v3";
531 regulator-name = "abb_ivahd";
532 #address-cells = <0>;
533 #size-cells = <0>;
534 clocks = <&sys_clkin1>;
535 ti,settling-time = <50>;
536 ti,clock-cycles = <16>;
537
538 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
539 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
540 <0x4a002470 0x4>;
541 reg-names = "setup-address", "control-address",
542 "int-address", "efuse-address",
543 "ldo-address";
544 ti,tranxdone-status-mask = <0x40000000>;
545 /* LDOVBBIVA_FBB_MUX_CTRL */
546 ti,ldovbb-override-mask = <0x400>;
547 /* LDOVBBIVA_FBB_VSET_OUT */
548 ti,ldovbb-vset-mask = <0x1F>;
549
550 /*
551 * NOTE: only FBB mode used but actual vset will
552 * determine final biasing
553 */
554 ti,abb_info = <
555 /*uV ABB efuse rbb_m fbb_m vset_m*/
556 1055000 0 0x0 0 0x02000000 0x01F00000
557 1150000 0 0x4 0 0x02000000 0x01F00000
558 1250000 0 0x8 0 0x02000000 0x01F00000
559 >;
560 };
561
562 abb_dspeve: regulator-abb-dspeve {
563 compatible = "ti,abb-v3";
564 regulator-name = "abb_dspeve";
565 #address-cells = <0>;
566 #size-cells = <0>;
567 clocks = <&sys_clkin1>;
568 ti,settling-time = <50>;
569 ti,clock-cycles = <16>;
570
571 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
572 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
573 <0x4a00246c 0x4>;
574 reg-names = "setup-address", "control-address",
575 "int-address", "efuse-address",
576 "ldo-address";
577 ti,tranxdone-status-mask = <0x20000000>;
578 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
579 ti,ldovbb-override-mask = <0x400>;
580 /* LDOVBBDSPEVE_FBB_VSET_OUT */
581 ti,ldovbb-vset-mask = <0x1F>;
582
583 /*
584 * NOTE: only FBB mode used but actual vset will
585 * determine final biasing
586 */
587 ti,abb_info = <
588 /*uV ABB efuse rbb_m fbb_m vset_m*/
589 1055000 0 0x0 0 0x02000000 0x01F00000
590 1150000 0 0x4 0 0x02000000 0x01F00000
591 1250000 0 0x8 0 0x02000000 0x01F00000
592 >;
593 };
594
595 abb_gpu: regulator-abb-gpu {
596 compatible = "ti,abb-v3";
597 regulator-name = "abb_gpu";
598 #address-cells = <0>;
599 #size-cells = <0>;
600 clocks = <&sys_clkin1>;
601 ti,settling-time = <50>;
602 ti,clock-cycles = <16>;
603
604 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
605 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
606 <0x4ae0c154 0x4>;
607 reg-names = "setup-address", "control-address",
608 "int-address", "efuse-address",
609 "ldo-address";
610 ti,tranxdone-status-mask = <0x10000000>;
611 /* LDOVBBGPU_FBB_MUX_CTRL */
612 ti,ldovbb-override-mask = <0x400>;
613 /* LDOVBBGPU_FBB_VSET_OUT */
614 ti,ldovbb-vset-mask = <0x1F>;
615
616 /*
617 * NOTE: only FBB mode used but actual vset will
618 * determine final biasing
619 */
620 ti,abb_info = <
621 /*uV ABB efuse rbb_m fbb_m vset_m*/
622 1090000 0 0x0 0 0x02000000 0x01F00000
623 1210000 0 0x4 0 0x02000000 0x01F00000
624 1280000 0 0x8 0 0x02000000 0x01F00000
625 >;
626 };
627
628 qspi: spi@4b300000 {
629 compatible = "ti,dra7xxx-qspi";
630 reg = <0x4b300000 0x100>,
631 <0x5c000000 0x4000000>;
632 reg-names = "qspi_base", "qspi_mmap";
633 syscon-chipselects = <&scm_conf 0x558>;
634 #address-cells = <1>;
635 #size-cells = <0>;
636 ti,hwmods = "qspi";
637 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
638 clock-names = "fck";
639 num-cs = <4>;
640 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
641 status = "disabled";
642 };
643
644 /* OCP2SCP3 */
645 sata: sata@4a141100 {
646 compatible = "snps,dwc-ahci";
647 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
648 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
649 phys = <&sata_phy>;
650 phy-names = "sata-phy";
651 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
652 ti,hwmods = "sata";
653 ports-implemented = <0x1>;
654 };
655
656 /* OCP2SCP1 */
657 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
658 gpmc: gpmc@50000000 {
659 compatible = "ti,am3352-gpmc";
660 ti,hwmods = "gpmc";
661 reg = <0x50000000 0x37c>; /* device IO registers */
662 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
663 dmas = <&edma_xbar 4 0>;
664 dma-names = "rxtx";
665 gpmc,num-cs = <8>;
666 gpmc,num-waitpins = <2>;
667 #address-cells = <2>;
668 #size-cells = <1>;
669 interrupt-controller;
670 #interrupt-cells = <2>;
671 gpio-controller;
672 #gpio-cells = <2>;
673 status = "disabled";
674 };
675
676 target-module@56000000 {
677 compatible = "ti,sysc-omap4", "ti,sysc";
678 reg = <0x5600fe00 0x4>,
679 <0x5600fe10 0x4>;
680 reg-names = "rev", "sysc";
681 ti,sysc-midle = <SYSC_IDLE_FORCE>,
682 <SYSC_IDLE_NO>,
683 <SYSC_IDLE_SMART>;
684 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
685 <SYSC_IDLE_NO>,
686 <SYSC_IDLE_SMART>;
687 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
688 clock-names = "fck";
689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0 0x56000000 0x2000000>;
692 };
693
694 crossbar_mpu: crossbar@4a002a48 {
695 compatible = "ti,irq-crossbar";
696 reg = <0x4a002a48 0x130>;
697 interrupt-controller;
698 interrupt-parent = <&wakeupgen>;
699 #interrupt-cells = <3>;
700 ti,max-irqs = <160>;
701 ti,max-crossbar-sources = <MAX_SOURCES>;
702 ti,reg-size = <2>;
703 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
704 ti,irqs-skip = <10 133 139 140>;
705 ti,irqs-safe-map = <0>;
706 };
707
708 dss: dss@58000000 {
709 compatible = "ti,dra7-dss";
710 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
711 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
712 status = "disabled";
713 ti,hwmods = "dss_core";
714 /* CTRL_CORE_DSS_PLL_CONTROL */
715 syscon-pll-ctrl = <&scm_conf 0x538>;
716 #address-cells = <1>;
717 #size-cells = <1>;
718 ranges;
719
720 dispc@58001000 {
721 compatible = "ti,dra7-dispc";
722 reg = <0x58001000 0x1000>;
723 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
724 ti,hwmods = "dss_dispc";
725 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
726 clock-names = "fck";
727 /* CTRL_CORE_SMA_SW_1 */
728 syscon-pol = <&scm_conf 0x534>;
729 };
730
731 hdmi: encoder@58060000 {
732 compatible = "ti,dra7-hdmi";
733 reg = <0x58040000 0x200>,
734 <0x58040200 0x80>,
735 <0x58040300 0x80>,
736 <0x58060000 0x19000>;
737 reg-names = "wp", "pll", "phy", "core";
738 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
739 status = "disabled";
740 ti,hwmods = "dss_hdmi";
741 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
742 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
743 clock-names = "fck", "sys_clk";
744 dmas = <&sdma_xbar 76>;
745 dma-names = "audio_tx";
746 };
747 };
748
749 aes1_target: target-module@4b500000 {
750 compatible = "ti,sysc-omap2", "ti,sysc";
751 reg = <0x4b500080 0x4>,
752 <0x4b500084 0x4>,
753 <0x4b500088 0x4>;
754 reg-names = "rev", "sysc", "syss";
755 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
756 SYSC_OMAP2_AUTOIDLE)>;
757 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
758 <SYSC_IDLE_NO>,
759 <SYSC_IDLE_SMART>,
760 <SYSC_IDLE_SMART_WKUP>;
761 ti,syss-mask = <1>;
762 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
763 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
764 clock-names = "fck";
765 #address-cells = <1>;
766 #size-cells = <1>;
767 ranges = <0x0 0x4b500000 0x1000>;
768
769 aes1: aes@0 {
770 compatible = "ti,omap4-aes";
771 reg = <0 0xa0>;
772 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
773 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
774 dma-names = "tx", "rx";
775 clocks = <&l3_iclk_div>;
776 clock-names = "fck";
777 };
778 };
779
780 aes2_target: target-module@4b700000 {
781 compatible = "ti,sysc-omap2", "ti,sysc";
782 reg = <0x4b700080 0x4>,
783 <0x4b700084 0x4>,
784 <0x4b700088 0x4>;
785 reg-names = "rev", "sysc", "syss";
786 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
787 SYSC_OMAP2_AUTOIDLE)>;
788 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
789 <SYSC_IDLE_NO>,
790 <SYSC_IDLE_SMART>,
791 <SYSC_IDLE_SMART_WKUP>;
792 ti,syss-mask = <1>;
793 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
794 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
795 clock-names = "fck";
796 #address-cells = <1>;
797 #size-cells = <1>;
798 ranges = <0x0 0x4b700000 0x1000>;
799
800 aes2: aes@0 {
801 compatible = "ti,omap4-aes";
802 reg = <0 0xa0>;
803 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
804 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
805 dma-names = "tx", "rx";
806 clocks = <&l3_iclk_div>;
807 clock-names = "fck";
808 };
809 };
810
811 sham_target: target-module@4b101000 {
812 compatible = "ti,sysc-omap3-sham", "ti,sysc";
813 reg = <0x4b101100 0x4>,
814 <0x4b101110 0x4>,
815 <0x4b101114 0x4>;
816 reg-names = "rev", "sysc", "syss";
817 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
818 SYSC_OMAP2_AUTOIDLE)>;
819 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
820 <SYSC_IDLE_NO>,
821 <SYSC_IDLE_SMART>;
822 ti,syss-mask = <1>;
823 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
824 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
825 clock-names = "fck";
826 #address-cells = <1>;
827 #size-cells = <1>;
828 ranges = <0x0 0x4b101000 0x1000>;
829
830 sham: sham@0 {
831 compatible = "ti,omap5-sham";
832 reg = <0 0x300>;
833 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
834 dmas = <&edma_xbar 119 0>;
835 dma-names = "rx";
836 clocks = <&l3_iclk_div>;
837 clock-names = "fck";
838 };
839 };
840
841 opp_supply_mpu: opp-supply@4a003b20 {
842 compatible = "ti,omap5-opp-supply";
843 reg = <0x4a003b20 0xc>;
844 ti,efuse-settings = <
845 /* uV offset */
846 1060000 0x0
847 1160000 0x4
848 1210000 0x8
849 >;
850 ti,absolute-max-voltage-uv = <1500000>;
851 };
852
853 };
854
855 thermal_zones: thermal-zones {
856 #include "omap4-cpu-thermal.dtsi"
857 #include "omap5-gpu-thermal.dtsi"
858 #include "omap5-core-thermal.dtsi"
859 #include "dra7-dspeve-thermal.dtsi"
860 #include "dra7-iva-thermal.dtsi"
861 };
862
863 };
864
865 &cpu_thermal {
866 polling-delay = <500>; /* milliseconds */
867 coefficients = <0 2000>;
868 };
869
870 &gpu_thermal {
871 coefficients = <0 2000>;
872 };
873
874 &core_thermal {
875 coefficients = <0 2000>;
876 };
877
878 &dspeve_thermal {
879 coefficients = <0 2000>;
880 };
881
882 &iva_thermal {
883 coefficients = <0 2000>;
884 };
885
886 &cpu_crit {
887 temperature = <120000>; /* milli Celsius */
888 };
889
890 &core_crit {
891 temperature = <120000>; /* milli Celsius */
892 };
893
894 &gpu_crit {
895 temperature = <120000>; /* milli Celsius */
896 };
897
898 &dspeve_crit {
899 temperature = <120000>; /* milli Celsius */
900 };
901
902 &iva_crit {
903 temperature = <120000>; /* milli Celsius */
904 };
905
906 #include "dra7-l4.dtsi"
907 #include "dra7xx-clocks.dtsi"
908
909 &prm {
910 prm_dsp1: prm@400 {
911 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
912 reg = <0x400 0x100>;
913 #reset-cells = <1>;
914 };
915
916 prm_ipu: prm@500 {
917 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
918 reg = <0x500 0x100>;
919 #reset-cells = <1>;
920 };
921
922 prm_core: prm@700 {
923 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
924 reg = <0x700 0x100>;
925 #reset-cells = <1>;
926 };
927
928 prm_iva: prm@f00 {
929 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
930 reg = <0xf00 0x100>;
931 };
932
933 prm_dsp2: prm@1b00 {
934 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
935 reg = <0x1b00 0x40>;
936 #reset-cells = <1>;
937 };
938
939 prm_eve1: prm@1b40 {
940 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
941 reg = <0x1b40 0x40>;
942 };
943
944 prm_eve2: prm@1b80 {
945 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
946 reg = <0x1b80 0x40>;
947 };
948
949 prm_eve3: prm@1bc0 {
950 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
951 reg = <0x1bc0 0x40>;
952 };
953
954 prm_eve4: prm@1c00 {
955 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
956 reg = <0x1c00 0x60>;
957 };
958 };
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