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Merge tag 'at91-ab-4.13-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/abellon...
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / dra7.dtsi
1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12
13 #define MAX_SOURCES 400
14
15 / {
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&crossbar_mpu>;
21 chosen { };
22
23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 ethernet0 = &cpsw_emac0;
40 ethernet1 = &cpsw_emac1;
41 d_can0 = &dcan1;
42 d_can1 = &dcan2;
43 spi0 = &qspi;
44 };
45
46 timer {
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&gic>;
53 };
54
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 reg = <0x0 0x48211000 0x0 0x1000>,
60 <0x0 0x48212000 0x0 0x2000>,
61 <0x0 0x48214000 0x0 0x2000>,
62 <0x0 0x48216000 0x0 0x2000>;
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64 interrupt-parent = <&gic>;
65 };
66
67 wakeupgen: interrupt-controller@48281000 {
68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
69 interrupt-controller;
70 #interrupt-cells = <3>;
71 reg = <0x0 0x48281000 0x0 0x1000>;
72 interrupt-parent = <&gic>;
73 };
74
75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 cpu0: cpu@0 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a15";
82 reg = <0>;
83
84 operating-points-v2 = <&cpu0_opp_table>;
85
86 clocks = <&dpll_mpu_ck>;
87 clock-names = "cpu";
88
89 clock-latency = <300000>; /* From omap-cpufreq driver */
90
91 /* cooling options */
92 cooling-min-level = <0>;
93 cooling-max-level = <2>;
94 #cooling-cells = <2>; /* min followed by max */
95 };
96 };
97
98 cpu0_opp_table: opp-table {
99 compatible = "operating-points-v2-ti-cpu";
100 syscon = <&scm_wkup>;
101
102 opp_nom@1000000000 {
103 opp-hz = /bits/ 64 <1000000000>;
104 opp-microvolt = <1060000 850000 1150000>;
105 opp-supported-hw = <0xFF 0x01>;
106 opp-suspend;
107 };
108
109 opp_od@1176000000 {
110 opp-hz = /bits/ 64 <1176000000>;
111 opp-microvolt = <1160000 885000 1160000>;
112 opp-supported-hw = <0xFF 0x02>;
113 };
114 };
115
116 /*
117 * The soc node represents the soc top level view. It is used for IPs
118 * that are not memory mapped in the MPU view or for the MPU itself.
119 */
120 soc {
121 compatible = "ti,omap-infra";
122 mpu {
123 compatible = "ti,omap5-mpu";
124 ti,hwmods = "mpu";
125 };
126 };
127
128 /*
129 * XXX: Use a flat representation of the SOC interconnect.
130 * The real OMAP interconnect network is quite complex.
131 * Since it will not bring real advantage to represent that in DT for
132 * the moment, just use a fake OCP bus entry to represent the whole bus
133 * hierarchy.
134 */
135 ocp {
136 compatible = "ti,dra7-l3-noc", "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0x0 0x0 0x0 0xc0000000>;
140 ti,hwmods = "l3_main_1", "l3_main_2";
141 reg = <0x0 0x44000000 0x0 0x1000000>,
142 <0x0 0x45000000 0x0 0x1000>;
143 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
144 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
145
146 l4_cfg: l4@4a000000 {
147 compatible = "ti,dra7-l4-cfg", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0 0x4a000000 0x22c000>;
151
152 scm: scm@2000 {
153 compatible = "ti,dra7-scm-core", "simple-bus";
154 reg = <0x2000 0x2000>;
155 #address-cells = <1>;
156 #size-cells = <1>;
157 ranges = <0 0x2000 0x2000>;
158
159 scm_conf: scm_conf@0 {
160 compatible = "syscon", "simple-bus";
161 reg = <0x0 0x1400>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges = <0 0x0 0x1400>;
165
166 pbias_regulator: pbias_regulator@e00 {
167 compatible = "ti,pbias-dra7", "ti,pbias-omap";
168 reg = <0xe00 0x4>;
169 syscon = <&scm_conf>;
170 pbias_mmc_reg: pbias_mmc_omap5 {
171 regulator-name = "pbias_mmc_omap5";
172 regulator-min-microvolt = <1800000>;
173 regulator-max-microvolt = <3000000>;
174 };
175 };
176
177 scm_conf_clocks: clocks {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 };
181 };
182
183 dra7_pmx_core: pinmux@1400 {
184 compatible = "ti,dra7-padconf",
185 "pinctrl-single";
186 reg = <0x1400 0x0468>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189 #pinctrl-cells = <1>;
190 #interrupt-cells = <1>;
191 interrupt-controller;
192 pinctrl-single,register-width = <32>;
193 pinctrl-single,function-mask = <0x3fffffff>;
194 };
195
196 scm_conf1: scm_conf@1c04 {
197 compatible = "syscon";
198 reg = <0x1c04 0x0020>;
199 };
200
201 scm_conf_pcie: scm_conf@1c24 {
202 compatible = "syscon";
203 reg = <0x1c24 0x0024>;
204 };
205
206 sdma_xbar: dma-router@b78 {
207 compatible = "ti,dra7-dma-crossbar";
208 reg = <0xb78 0xfc>;
209 #dma-cells = <1>;
210 dma-requests = <205>;
211 ti,dma-safe-map = <0>;
212 dma-masters = <&sdma>;
213 };
214
215 edma_xbar: dma-router@c78 {
216 compatible = "ti,dra7-dma-crossbar";
217 reg = <0xc78 0x7c>;
218 #dma-cells = <2>;
219 dma-requests = <204>;
220 ti,dma-safe-map = <0>;
221 dma-masters = <&edma>;
222 };
223 };
224
225 cm_core_aon: cm_core_aon@5000 {
226 compatible = "ti,dra7-cm-core-aon";
227 reg = <0x5000 0x2000>;
228
229 cm_core_aon_clocks: clocks {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 };
233
234 cm_core_aon_clockdomains: clockdomains {
235 };
236 };
237
238 cm_core: cm_core@8000 {
239 compatible = "ti,dra7-cm-core";
240 reg = <0x8000 0x3000>;
241
242 cm_core_clocks: clocks {
243 #address-cells = <1>;
244 #size-cells = <0>;
245 };
246
247 cm_core_clockdomains: clockdomains {
248 };
249 };
250 };
251
252 l4_wkup: l4@4ae00000 {
253 compatible = "ti,dra7-l4-wkup", "simple-bus";
254 #address-cells = <1>;
255 #size-cells = <1>;
256 ranges = <0 0x4ae00000 0x3f000>;
257
258 counter32k: counter@4000 {
259 compatible = "ti,omap-counter32k";
260 reg = <0x4000 0x40>;
261 ti,hwmods = "counter_32k";
262 };
263
264 prm: prm@6000 {
265 compatible = "ti,dra7-prm";
266 reg = <0x6000 0x3000>;
267 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
268
269 prm_clocks: clocks {
270 #address-cells = <1>;
271 #size-cells = <0>;
272 };
273
274 prm_clockdomains: clockdomains {
275 };
276 };
277
278 scm_wkup: scm_conf@c000 {
279 compatible = "syscon";
280 reg = <0xc000 0x1000>;
281 };
282 };
283
284 axi@0 {
285 compatible = "simple-bus";
286 #size-cells = <1>;
287 #address-cells = <1>;
288 ranges = <0x51000000 0x51000000 0x3000
289 0x0 0x20000000 0x10000000>;
290 pcie1: pcie@51000000 {
291 compatible = "ti,dra7-pcie";
292 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
293 reg-names = "rc_dbics", "ti_conf", "config";
294 interrupts = <0 232 0x4>, <0 233 0x4>;
295 #address-cells = <3>;
296 #size-cells = <2>;
297 device_type = "pci";
298 ranges = <0x81000000 0 0 0x03000 0 0x00010000
299 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
300 bus-range = <0x00 0xff>;
301 #interrupt-cells = <1>;
302 num-lanes = <1>;
303 linux,pci-domain = <0>;
304 ti,hwmods = "pcie1";
305 phys = <&pcie1_phy>;
306 phy-names = "pcie-phy0";
307 interrupt-map-mask = <0 0 0 7>;
308 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
309 <0 0 0 2 &pcie1_intc 2>,
310 <0 0 0 3 &pcie1_intc 3>,
311 <0 0 0 4 &pcie1_intc 4>;
312 pcie1_intc: interrupt-controller {
313 interrupt-controller;
314 #address-cells = <0>;
315 #interrupt-cells = <1>;
316 };
317 };
318 };
319
320 axi@1 {
321 compatible = "simple-bus";
322 #size-cells = <1>;
323 #address-cells = <1>;
324 ranges = <0x51800000 0x51800000 0x3000
325 0x0 0x30000000 0x10000000>;
326 status = "disabled";
327 pcie@51800000 {
328 compatible = "ti,dra7-pcie";
329 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
330 reg-names = "rc_dbics", "ti_conf", "config";
331 interrupts = <0 355 0x4>, <0 356 0x4>;
332 #address-cells = <3>;
333 #size-cells = <2>;
334 device_type = "pci";
335 ranges = <0x81000000 0 0 0x03000 0 0x00010000
336 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
337 bus-range = <0x00 0xff>;
338 #interrupt-cells = <1>;
339 num-lanes = <1>;
340 linux,pci-domain = <1>;
341 ti,hwmods = "pcie2";
342 phys = <&pcie2_phy>;
343 phy-names = "pcie-phy0";
344 interrupt-map-mask = <0 0 0 7>;
345 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
346 <0 0 0 2 &pcie2_intc 2>,
347 <0 0 0 3 &pcie2_intc 3>,
348 <0 0 0 4 &pcie2_intc 4>;
349 pcie2_intc: interrupt-controller {
350 interrupt-controller;
351 #address-cells = <0>;
352 #interrupt-cells = <1>;
353 };
354 };
355 };
356
357 ocmcram1: ocmcram@40300000 {
358 compatible = "mmio-sram";
359 reg = <0x40300000 0x80000>;
360 ranges = <0x0 0x40300000 0x80000>;
361 #address-cells = <1>;
362 #size-cells = <1>;
363 /*
364 * This is a placeholder for an optional reserved
365 * region for use by secure software. The size
366 * of this region is not known until runtime so it
367 * is set as zero to either be updated to reserve
368 * space or left unchanged to leave all SRAM for use.
369 * On HS parts that that require the reserved region
370 * either the bootloader can update the size to
371 * the required amount or the node can be overridden
372 * from the board dts file for the secure platform.
373 */
374 sram-hs@0 {
375 compatible = "ti,secure-ram";
376 reg = <0x0 0x0>;
377 };
378 };
379
380 /*
381 * NOTE: ocmcram2 and ocmcram3 are not available on all
382 * DRA7xx and AM57xx variants. Confirm availability in
383 * the data manual for the exact part number in use
384 * before enabling these nodes in the board dts file.
385 */
386 ocmcram2: ocmcram@40400000 {
387 status = "disabled";
388 compatible = "mmio-sram";
389 reg = <0x40400000 0x100000>;
390 ranges = <0x0 0x40400000 0x100000>;
391 #address-cells = <1>;
392 #size-cells = <1>;
393 };
394
395 ocmcram3: ocmcram@40500000 {
396 status = "disabled";
397 compatible = "mmio-sram";
398 reg = <0x40500000 0x100000>;
399 ranges = <0x0 0x40500000 0x100000>;
400 #address-cells = <1>;
401 #size-cells = <1>;
402 };
403
404 bandgap: bandgap@4a0021e0 {
405 reg = <0x4a0021e0 0xc
406 0x4a00232c 0xc
407 0x4a002380 0x2c
408 0x4a0023C0 0x3c
409 0x4a002564 0x8
410 0x4a002574 0x50>;
411 compatible = "ti,dra752-bandgap";
412 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
413 #thermal-sensor-cells = <1>;
414 };
415
416 dsp1_system: dsp_system@40d00000 {
417 compatible = "syscon";
418 reg = <0x40d00000 0x100>;
419 };
420
421 sdma: dma-controller@4a056000 {
422 compatible = "ti,omap4430-sdma";
423 reg = <0x4a056000 0x1000>;
424 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
428 #dma-cells = <1>;
429 dma-channels = <32>;
430 dma-requests = <127>;
431 };
432
433 edma: edma@43300000 {
434 compatible = "ti,edma3-tpcc";
435 ti,hwmods = "tpcc";
436 reg = <0x43300000 0x100000>;
437 reg-names = "edma3_cc";
438 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-names = "edma3_ccint", "edma3_mperr",
442 "edma3_ccerrint";
443 dma-requests = <64>;
444 #dma-cells = <2>;
445
446 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
447
448 /*
449 * memcpy is disabled, can be enabled with:
450 * ti,edma-memcpy-channels = <20 21>;
451 * for example. Note that these channels need to be
452 * masked in the xbar as well.
453 */
454 };
455
456 edma_tptc0: tptc@43400000 {
457 compatible = "ti,edma3-tptc";
458 ti,hwmods = "tptc0";
459 reg = <0x43400000 0x100000>;
460 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "edma3_tcerrint";
462 };
463
464 edma_tptc1: tptc@43500000 {
465 compatible = "ti,edma3-tptc";
466 ti,hwmods = "tptc1";
467 reg = <0x43500000 0x100000>;
468 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-names = "edma3_tcerrint";
470 };
471
472 gpio1: gpio@4ae10000 {
473 compatible = "ti,omap4-gpio";
474 reg = <0x4ae10000 0x200>;
475 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
476 ti,hwmods = "gpio1";
477 gpio-controller;
478 #gpio-cells = <2>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 };
482
483 gpio2: gpio@48055000 {
484 compatible = "ti,omap4-gpio";
485 reg = <0x48055000 0x200>;
486 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
487 ti,hwmods = "gpio2";
488 gpio-controller;
489 #gpio-cells = <2>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 };
493
494 gpio3: gpio@48057000 {
495 compatible = "ti,omap4-gpio";
496 reg = <0x48057000 0x200>;
497 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
498 ti,hwmods = "gpio3";
499 gpio-controller;
500 #gpio-cells = <2>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 };
504
505 gpio4: gpio@48059000 {
506 compatible = "ti,omap4-gpio";
507 reg = <0x48059000 0x200>;
508 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
509 ti,hwmods = "gpio4";
510 gpio-controller;
511 #gpio-cells = <2>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 };
515
516 gpio5: gpio@4805b000 {
517 compatible = "ti,omap4-gpio";
518 reg = <0x4805b000 0x200>;
519 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
520 ti,hwmods = "gpio5";
521 gpio-controller;
522 #gpio-cells = <2>;
523 interrupt-controller;
524 #interrupt-cells = <2>;
525 };
526
527 gpio6: gpio@4805d000 {
528 compatible = "ti,omap4-gpio";
529 reg = <0x4805d000 0x200>;
530 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
531 ti,hwmods = "gpio6";
532 gpio-controller;
533 #gpio-cells = <2>;
534 interrupt-controller;
535 #interrupt-cells = <2>;
536 };
537
538 gpio7: gpio@48051000 {
539 compatible = "ti,omap4-gpio";
540 reg = <0x48051000 0x200>;
541 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
542 ti,hwmods = "gpio7";
543 gpio-controller;
544 #gpio-cells = <2>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 };
548
549 gpio8: gpio@48053000 {
550 compatible = "ti,omap4-gpio";
551 reg = <0x48053000 0x200>;
552 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
553 ti,hwmods = "gpio8";
554 gpio-controller;
555 #gpio-cells = <2>;
556 interrupt-controller;
557 #interrupt-cells = <2>;
558 };
559
560 uart1: serial@4806a000 {
561 compatible = "ti,dra742-uart", "ti,omap4-uart";
562 reg = <0x4806a000 0x100>;
563 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
564 ti,hwmods = "uart1";
565 clock-frequency = <48000000>;
566 status = "disabled";
567 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
568 dma-names = "tx", "rx";
569 };
570
571 uart2: serial@4806c000 {
572 compatible = "ti,dra742-uart", "ti,omap4-uart";
573 reg = <0x4806c000 0x100>;
574 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
575 ti,hwmods = "uart2";
576 clock-frequency = <48000000>;
577 status = "disabled";
578 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
579 dma-names = "tx", "rx";
580 };
581
582 uart3: serial@48020000 {
583 compatible = "ti,dra742-uart", "ti,omap4-uart";
584 reg = <0x48020000 0x100>;
585 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
586 ti,hwmods = "uart3";
587 clock-frequency = <48000000>;
588 status = "disabled";
589 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
590 dma-names = "tx", "rx";
591 };
592
593 uart4: serial@4806e000 {
594 compatible = "ti,dra742-uart", "ti,omap4-uart";
595 reg = <0x4806e000 0x100>;
596 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
597 ti,hwmods = "uart4";
598 clock-frequency = <48000000>;
599 status = "disabled";
600 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
601 dma-names = "tx", "rx";
602 };
603
604 uart5: serial@48066000 {
605 compatible = "ti,dra742-uart", "ti,omap4-uart";
606 reg = <0x48066000 0x100>;
607 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
608 ti,hwmods = "uart5";
609 clock-frequency = <48000000>;
610 status = "disabled";
611 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
612 dma-names = "tx", "rx";
613 };
614
615 uart6: serial@48068000 {
616 compatible = "ti,dra742-uart", "ti,omap4-uart";
617 reg = <0x48068000 0x100>;
618 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
619 ti,hwmods = "uart6";
620 clock-frequency = <48000000>;
621 status = "disabled";
622 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
623 dma-names = "tx", "rx";
624 };
625
626 uart7: serial@48420000 {
627 compatible = "ti,dra742-uart", "ti,omap4-uart";
628 reg = <0x48420000 0x100>;
629 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
630 ti,hwmods = "uart7";
631 clock-frequency = <48000000>;
632 status = "disabled";
633 };
634
635 uart8: serial@48422000 {
636 compatible = "ti,dra742-uart", "ti,omap4-uart";
637 reg = <0x48422000 0x100>;
638 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
639 ti,hwmods = "uart8";
640 clock-frequency = <48000000>;
641 status = "disabled";
642 };
643
644 uart9: serial@48424000 {
645 compatible = "ti,dra742-uart", "ti,omap4-uart";
646 reg = <0x48424000 0x100>;
647 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
648 ti,hwmods = "uart9";
649 clock-frequency = <48000000>;
650 status = "disabled";
651 };
652
653 uart10: serial@4ae2b000 {
654 compatible = "ti,dra742-uart", "ti,omap4-uart";
655 reg = <0x4ae2b000 0x100>;
656 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
657 ti,hwmods = "uart10";
658 clock-frequency = <48000000>;
659 status = "disabled";
660 };
661
662 mailbox1: mailbox@4a0f4000 {
663 compatible = "ti,omap4-mailbox";
664 reg = <0x4a0f4000 0x200>;
665 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
668 ti,hwmods = "mailbox1";
669 #mbox-cells = <1>;
670 ti,mbox-num-users = <3>;
671 ti,mbox-num-fifos = <8>;
672 status = "disabled";
673 };
674
675 mailbox2: mailbox@4883a000 {
676 compatible = "ti,omap4-mailbox";
677 reg = <0x4883a000 0x200>;
678 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
682 ti,hwmods = "mailbox2";
683 #mbox-cells = <1>;
684 ti,mbox-num-users = <4>;
685 ti,mbox-num-fifos = <12>;
686 status = "disabled";
687 };
688
689 mailbox3: mailbox@4883c000 {
690 compatible = "ti,omap4-mailbox";
691 reg = <0x4883c000 0x200>;
692 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
696 ti,hwmods = "mailbox3";
697 #mbox-cells = <1>;
698 ti,mbox-num-users = <4>;
699 ti,mbox-num-fifos = <12>;
700 status = "disabled";
701 };
702
703 mailbox4: mailbox@4883e000 {
704 compatible = "ti,omap4-mailbox";
705 reg = <0x4883e000 0x200>;
706 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
710 ti,hwmods = "mailbox4";
711 #mbox-cells = <1>;
712 ti,mbox-num-users = <4>;
713 ti,mbox-num-fifos = <12>;
714 status = "disabled";
715 };
716
717 mailbox5: mailbox@48840000 {
718 compatible = "ti,omap4-mailbox";
719 reg = <0x48840000 0x200>;
720 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
724 ti,hwmods = "mailbox5";
725 #mbox-cells = <1>;
726 ti,mbox-num-users = <4>;
727 ti,mbox-num-fifos = <12>;
728 status = "disabled";
729 };
730
731 mailbox6: mailbox@48842000 {
732 compatible = "ti,omap4-mailbox";
733 reg = <0x48842000 0x200>;
734 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
738 ti,hwmods = "mailbox6";
739 #mbox-cells = <1>;
740 ti,mbox-num-users = <4>;
741 ti,mbox-num-fifos = <12>;
742 status = "disabled";
743 };
744
745 mailbox7: mailbox@48844000 {
746 compatible = "ti,omap4-mailbox";
747 reg = <0x48844000 0x200>;
748 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
752 ti,hwmods = "mailbox7";
753 #mbox-cells = <1>;
754 ti,mbox-num-users = <4>;
755 ti,mbox-num-fifos = <12>;
756 status = "disabled";
757 };
758
759 mailbox8: mailbox@48846000 {
760 compatible = "ti,omap4-mailbox";
761 reg = <0x48846000 0x200>;
762 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
766 ti,hwmods = "mailbox8";
767 #mbox-cells = <1>;
768 ti,mbox-num-users = <4>;
769 ti,mbox-num-fifos = <12>;
770 status = "disabled";
771 };
772
773 mailbox9: mailbox@4885e000 {
774 compatible = "ti,omap4-mailbox";
775 reg = <0x4885e000 0x200>;
776 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
780 ti,hwmods = "mailbox9";
781 #mbox-cells = <1>;
782 ti,mbox-num-users = <4>;
783 ti,mbox-num-fifos = <12>;
784 status = "disabled";
785 };
786
787 mailbox10: mailbox@48860000 {
788 compatible = "ti,omap4-mailbox";
789 reg = <0x48860000 0x200>;
790 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
794 ti,hwmods = "mailbox10";
795 #mbox-cells = <1>;
796 ti,mbox-num-users = <4>;
797 ti,mbox-num-fifos = <12>;
798 status = "disabled";
799 };
800
801 mailbox11: mailbox@48862000 {
802 compatible = "ti,omap4-mailbox";
803 reg = <0x48862000 0x200>;
804 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
808 ti,hwmods = "mailbox11";
809 #mbox-cells = <1>;
810 ti,mbox-num-users = <4>;
811 ti,mbox-num-fifos = <12>;
812 status = "disabled";
813 };
814
815 mailbox12: mailbox@48864000 {
816 compatible = "ti,omap4-mailbox";
817 reg = <0x48864000 0x200>;
818 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
822 ti,hwmods = "mailbox12";
823 #mbox-cells = <1>;
824 ti,mbox-num-users = <4>;
825 ti,mbox-num-fifos = <12>;
826 status = "disabled";
827 };
828
829 mailbox13: mailbox@48802000 {
830 compatible = "ti,omap4-mailbox";
831 reg = <0x48802000 0x200>;
832 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
836 ti,hwmods = "mailbox13";
837 #mbox-cells = <1>;
838 ti,mbox-num-users = <4>;
839 ti,mbox-num-fifos = <12>;
840 status = "disabled";
841 };
842
843 timer1: timer@4ae18000 {
844 compatible = "ti,omap5430-timer";
845 reg = <0x4ae18000 0x80>;
846 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
847 ti,hwmods = "timer1";
848 ti,timer-alwon;
849 };
850
851 timer2: timer@48032000 {
852 compatible = "ti,omap5430-timer";
853 reg = <0x48032000 0x80>;
854 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
855 ti,hwmods = "timer2";
856 };
857
858 timer3: timer@48034000 {
859 compatible = "ti,omap5430-timer";
860 reg = <0x48034000 0x80>;
861 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
862 ti,hwmods = "timer3";
863 };
864
865 timer4: timer@48036000 {
866 compatible = "ti,omap5430-timer";
867 reg = <0x48036000 0x80>;
868 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
869 ti,hwmods = "timer4";
870 };
871
872 timer5: timer@48820000 {
873 compatible = "ti,omap5430-timer";
874 reg = <0x48820000 0x80>;
875 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
876 ti,hwmods = "timer5";
877 };
878
879 timer6: timer@48822000 {
880 compatible = "ti,omap5430-timer";
881 reg = <0x48822000 0x80>;
882 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
883 ti,hwmods = "timer6";
884 };
885
886 timer7: timer@48824000 {
887 compatible = "ti,omap5430-timer";
888 reg = <0x48824000 0x80>;
889 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
890 ti,hwmods = "timer7";
891 };
892
893 timer8: timer@48826000 {
894 compatible = "ti,omap5430-timer";
895 reg = <0x48826000 0x80>;
896 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
897 ti,hwmods = "timer8";
898 };
899
900 timer9: timer@4803e000 {
901 compatible = "ti,omap5430-timer";
902 reg = <0x4803e000 0x80>;
903 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
904 ti,hwmods = "timer9";
905 };
906
907 timer10: timer@48086000 {
908 compatible = "ti,omap5430-timer";
909 reg = <0x48086000 0x80>;
910 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
911 ti,hwmods = "timer10";
912 };
913
914 timer11: timer@48088000 {
915 compatible = "ti,omap5430-timer";
916 reg = <0x48088000 0x80>;
917 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
918 ti,hwmods = "timer11";
919 };
920
921 timer12: timer@4ae20000 {
922 compatible = "ti,omap5430-timer";
923 reg = <0x4ae20000 0x80>;
924 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
925 ti,hwmods = "timer12";
926 ti,timer-alwon;
927 ti,timer-secure;
928 };
929
930 timer13: timer@48828000 {
931 compatible = "ti,omap5430-timer";
932 reg = <0x48828000 0x80>;
933 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
934 ti,hwmods = "timer13";
935 };
936
937 timer14: timer@4882a000 {
938 compatible = "ti,omap5430-timer";
939 reg = <0x4882a000 0x80>;
940 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
941 ti,hwmods = "timer14";
942 };
943
944 timer15: timer@4882c000 {
945 compatible = "ti,omap5430-timer";
946 reg = <0x4882c000 0x80>;
947 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
948 ti,hwmods = "timer15";
949 };
950
951 timer16: timer@4882e000 {
952 compatible = "ti,omap5430-timer";
953 reg = <0x4882e000 0x80>;
954 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
955 ti,hwmods = "timer16";
956 };
957
958 wdt2: wdt@4ae14000 {
959 compatible = "ti,omap3-wdt";
960 reg = <0x4ae14000 0x80>;
961 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
962 ti,hwmods = "wd_timer2";
963 };
964
965 hwspinlock: spinlock@4a0f6000 {
966 compatible = "ti,omap4-hwspinlock";
967 reg = <0x4a0f6000 0x1000>;
968 ti,hwmods = "spinlock";
969 #hwlock-cells = <1>;
970 };
971
972 dmm@4e000000 {
973 compatible = "ti,omap5-dmm";
974 reg = <0x4e000000 0x800>;
975 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
976 ti,hwmods = "dmm";
977 };
978
979 i2c1: i2c@48070000 {
980 compatible = "ti,omap4-i2c";
981 reg = <0x48070000 0x100>;
982 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
983 #address-cells = <1>;
984 #size-cells = <0>;
985 ti,hwmods = "i2c1";
986 status = "disabled";
987 };
988
989 i2c2: i2c@48072000 {
990 compatible = "ti,omap4-i2c";
991 reg = <0x48072000 0x100>;
992 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
993 #address-cells = <1>;
994 #size-cells = <0>;
995 ti,hwmods = "i2c2";
996 status = "disabled";
997 };
998
999 i2c3: i2c@48060000 {
1000 compatible = "ti,omap4-i2c";
1001 reg = <0x48060000 0x100>;
1002 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 ti,hwmods = "i2c3";
1006 status = "disabled";
1007 };
1008
1009 i2c4: i2c@4807a000 {
1010 compatible = "ti,omap4-i2c";
1011 reg = <0x4807a000 0x100>;
1012 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1015 ti,hwmods = "i2c4";
1016 status = "disabled";
1017 };
1018
1019 i2c5: i2c@4807c000 {
1020 compatible = "ti,omap4-i2c";
1021 reg = <0x4807c000 0x100>;
1022 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1025 ti,hwmods = "i2c5";
1026 status = "disabled";
1027 };
1028
1029 mmc1: mmc@4809c000 {
1030 compatible = "ti,omap4-hsmmc";
1031 reg = <0x4809c000 0x400>;
1032 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1033 ti,hwmods = "mmc1";
1034 ti,dual-volt;
1035 ti,needs-special-reset;
1036 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1037 dma-names = "tx", "rx";
1038 status = "disabled";
1039 pbias-supply = <&pbias_mmc_reg>;
1040 };
1041
1042 mmc2: mmc@480b4000 {
1043 compatible = "ti,omap4-hsmmc";
1044 reg = <0x480b4000 0x400>;
1045 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1046 ti,hwmods = "mmc2";
1047 ti,needs-special-reset;
1048 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1049 dma-names = "tx", "rx";
1050 status = "disabled";
1051 };
1052
1053 mmc3: mmc@480ad000 {
1054 compatible = "ti,omap4-hsmmc";
1055 reg = <0x480ad000 0x400>;
1056 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1057 ti,hwmods = "mmc3";
1058 ti,needs-special-reset;
1059 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1060 dma-names = "tx", "rx";
1061 status = "disabled";
1062 };
1063
1064 mmc4: mmc@480d1000 {
1065 compatible = "ti,omap4-hsmmc";
1066 reg = <0x480d1000 0x400>;
1067 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1068 ti,hwmods = "mmc4";
1069 ti,needs-special-reset;
1070 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1071 dma-names = "tx", "rx";
1072 status = "disabled";
1073 };
1074
1075 mmu0_dsp1: mmu@40d01000 {
1076 compatible = "ti,dra7-dsp-iommu";
1077 reg = <0x40d01000 0x100>;
1078 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1079 ti,hwmods = "mmu0_dsp1";
1080 #iommu-cells = <0>;
1081 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1082 status = "disabled";
1083 };
1084
1085 mmu1_dsp1: mmu@40d02000 {
1086 compatible = "ti,dra7-dsp-iommu";
1087 reg = <0x40d02000 0x100>;
1088 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1089 ti,hwmods = "mmu1_dsp1";
1090 #iommu-cells = <0>;
1091 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1092 status = "disabled";
1093 };
1094
1095 mmu_ipu1: mmu@58882000 {
1096 compatible = "ti,dra7-iommu";
1097 reg = <0x58882000 0x100>;
1098 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1099 ti,hwmods = "mmu_ipu1";
1100 #iommu-cells = <0>;
1101 ti,iommu-bus-err-back;
1102 status = "disabled";
1103 };
1104
1105 mmu_ipu2: mmu@55082000 {
1106 compatible = "ti,dra7-iommu";
1107 reg = <0x55082000 0x100>;
1108 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1109 ti,hwmods = "mmu_ipu2";
1110 #iommu-cells = <0>;
1111 ti,iommu-bus-err-back;
1112 status = "disabled";
1113 };
1114
1115 abb_mpu: regulator-abb-mpu {
1116 compatible = "ti,abb-v3";
1117 regulator-name = "abb_mpu";
1118 #address-cells = <0>;
1119 #size-cells = <0>;
1120 clocks = <&sys_clkin1>;
1121 ti,settling-time = <50>;
1122 ti,clock-cycles = <16>;
1123
1124 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1125 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1126 <0x4ae0c158 0x4>;
1127 reg-names = "setup-address", "control-address",
1128 "int-address", "efuse-address",
1129 "ldo-address";
1130 ti,tranxdone-status-mask = <0x80>;
1131 /* LDOVBBMPU_FBB_MUX_CTRL */
1132 ti,ldovbb-override-mask = <0x400>;
1133 /* LDOVBBMPU_FBB_VSET_OUT */
1134 ti,ldovbb-vset-mask = <0x1F>;
1135
1136 /*
1137 * NOTE: only FBB mode used but actual vset will
1138 * determine final biasing
1139 */
1140 ti,abb_info = <
1141 /*uV ABB efuse rbb_m fbb_m vset_m*/
1142 1060000 0 0x0 0 0x02000000 0x01F00000
1143 1160000 0 0x4 0 0x02000000 0x01F00000
1144 1210000 0 0x8 0 0x02000000 0x01F00000
1145 >;
1146 };
1147
1148 abb_ivahd: regulator-abb-ivahd {
1149 compatible = "ti,abb-v3";
1150 regulator-name = "abb_ivahd";
1151 #address-cells = <0>;
1152 #size-cells = <0>;
1153 clocks = <&sys_clkin1>;
1154 ti,settling-time = <50>;
1155 ti,clock-cycles = <16>;
1156
1157 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1158 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1159 <0x4a002470 0x4>;
1160 reg-names = "setup-address", "control-address",
1161 "int-address", "efuse-address",
1162 "ldo-address";
1163 ti,tranxdone-status-mask = <0x40000000>;
1164 /* LDOVBBIVA_FBB_MUX_CTRL */
1165 ti,ldovbb-override-mask = <0x400>;
1166 /* LDOVBBIVA_FBB_VSET_OUT */
1167 ti,ldovbb-vset-mask = <0x1F>;
1168
1169 /*
1170 * NOTE: only FBB mode used but actual vset will
1171 * determine final biasing
1172 */
1173 ti,abb_info = <
1174 /*uV ABB efuse rbb_m fbb_m vset_m*/
1175 1055000 0 0x0 0 0x02000000 0x01F00000
1176 1150000 0 0x4 0 0x02000000 0x01F00000
1177 1250000 0 0x8 0 0x02000000 0x01F00000
1178 >;
1179 };
1180
1181 abb_dspeve: regulator-abb-dspeve {
1182 compatible = "ti,abb-v3";
1183 regulator-name = "abb_dspeve";
1184 #address-cells = <0>;
1185 #size-cells = <0>;
1186 clocks = <&sys_clkin1>;
1187 ti,settling-time = <50>;
1188 ti,clock-cycles = <16>;
1189
1190 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1191 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1192 <0x4a00246c 0x4>;
1193 reg-names = "setup-address", "control-address",
1194 "int-address", "efuse-address",
1195 "ldo-address";
1196 ti,tranxdone-status-mask = <0x20000000>;
1197 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1198 ti,ldovbb-override-mask = <0x400>;
1199 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1200 ti,ldovbb-vset-mask = <0x1F>;
1201
1202 /*
1203 * NOTE: only FBB mode used but actual vset will
1204 * determine final biasing
1205 */
1206 ti,abb_info = <
1207 /*uV ABB efuse rbb_m fbb_m vset_m*/
1208 1055000 0 0x0 0 0x02000000 0x01F00000
1209 1150000 0 0x4 0 0x02000000 0x01F00000
1210 1250000 0 0x8 0 0x02000000 0x01F00000
1211 >;
1212 };
1213
1214 abb_gpu: regulator-abb-gpu {
1215 compatible = "ti,abb-v3";
1216 regulator-name = "abb_gpu";
1217 #address-cells = <0>;
1218 #size-cells = <0>;
1219 clocks = <&sys_clkin1>;
1220 ti,settling-time = <50>;
1221 ti,clock-cycles = <16>;
1222
1223 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1224 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1225 <0x4ae0c154 0x4>;
1226 reg-names = "setup-address", "control-address",
1227 "int-address", "efuse-address",
1228 "ldo-address";
1229 ti,tranxdone-status-mask = <0x10000000>;
1230 /* LDOVBBGPU_FBB_MUX_CTRL */
1231 ti,ldovbb-override-mask = <0x400>;
1232 /* LDOVBBGPU_FBB_VSET_OUT */
1233 ti,ldovbb-vset-mask = <0x1F>;
1234
1235 /*
1236 * NOTE: only FBB mode used but actual vset will
1237 * determine final biasing
1238 */
1239 ti,abb_info = <
1240 /*uV ABB efuse rbb_m fbb_m vset_m*/
1241 1090000 0 0x0 0 0x02000000 0x01F00000
1242 1210000 0 0x4 0 0x02000000 0x01F00000
1243 1280000 0 0x8 0 0x02000000 0x01F00000
1244 >;
1245 };
1246
1247 mcspi1: spi@48098000 {
1248 compatible = "ti,omap4-mcspi";
1249 reg = <0x48098000 0x200>;
1250 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1253 ti,hwmods = "mcspi1";
1254 ti,spi-num-cs = <4>;
1255 dmas = <&sdma_xbar 35>,
1256 <&sdma_xbar 36>,
1257 <&sdma_xbar 37>,
1258 <&sdma_xbar 38>,
1259 <&sdma_xbar 39>,
1260 <&sdma_xbar 40>,
1261 <&sdma_xbar 41>,
1262 <&sdma_xbar 42>;
1263 dma-names = "tx0", "rx0", "tx1", "rx1",
1264 "tx2", "rx2", "tx3", "rx3";
1265 status = "disabled";
1266 };
1267
1268 mcspi2: spi@4809a000 {
1269 compatible = "ti,omap4-mcspi";
1270 reg = <0x4809a000 0x200>;
1271 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1274 ti,hwmods = "mcspi2";
1275 ti,spi-num-cs = <2>;
1276 dmas = <&sdma_xbar 43>,
1277 <&sdma_xbar 44>,
1278 <&sdma_xbar 45>,
1279 <&sdma_xbar 46>;
1280 dma-names = "tx0", "rx0", "tx1", "rx1";
1281 status = "disabled";
1282 };
1283
1284 mcspi3: spi@480b8000 {
1285 compatible = "ti,omap4-mcspi";
1286 reg = <0x480b8000 0x200>;
1287 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1290 ti,hwmods = "mcspi3";
1291 ti,spi-num-cs = <2>;
1292 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1293 dma-names = "tx0", "rx0";
1294 status = "disabled";
1295 };
1296
1297 mcspi4: spi@480ba000 {
1298 compatible = "ti,omap4-mcspi";
1299 reg = <0x480ba000 0x200>;
1300 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1303 ti,hwmods = "mcspi4";
1304 ti,spi-num-cs = <1>;
1305 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1306 dma-names = "tx0", "rx0";
1307 status = "disabled";
1308 };
1309
1310 qspi: qspi@4b300000 {
1311 compatible = "ti,dra7xxx-qspi";
1312 reg = <0x4b300000 0x100>,
1313 <0x5c000000 0x4000000>;
1314 reg-names = "qspi_base", "qspi_mmap";
1315 syscon-chipselects = <&scm_conf 0x558>;
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1318 ti,hwmods = "qspi";
1319 clocks = <&qspi_gfclk_div>;
1320 clock-names = "fck";
1321 num-cs = <4>;
1322 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1323 status = "disabled";
1324 };
1325
1326 /* OCP2SCP3 */
1327 ocp2scp@4a090000 {
1328 compatible = "ti,omap-ocp2scp";
1329 #address-cells = <1>;
1330 #size-cells = <1>;
1331 ranges;
1332 reg = <0x4a090000 0x20>;
1333 ti,hwmods = "ocp2scp3";
1334 sata_phy: phy@4A096000 {
1335 compatible = "ti,phy-pipe3-sata";
1336 reg = <0x4A096000 0x80>, /* phy_rx */
1337 <0x4A096400 0x64>, /* phy_tx */
1338 <0x4A096800 0x40>; /* pll_ctrl */
1339 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1340 syscon-phy-power = <&scm_conf 0x374>;
1341 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1342 clock-names = "sysclk", "refclk";
1343 syscon-pllreset = <&scm_conf 0x3fc>;
1344 #phy-cells = <0>;
1345 };
1346
1347 pcie1_phy: pciephy@4a094000 {
1348 compatible = "ti,phy-pipe3-pcie";
1349 reg = <0x4a094000 0x80>, /* phy_rx */
1350 <0x4a094400 0x64>; /* phy_tx */
1351 reg-names = "phy_rx", "phy_tx";
1352 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1353 syscon-pcs = <&scm_conf_pcie 0x10>;
1354 clocks = <&dpll_pcie_ref_ck>,
1355 <&dpll_pcie_ref_m2ldo_ck>,
1356 <&optfclk_pciephy1_32khz>,
1357 <&optfclk_pciephy1_clk>,
1358 <&optfclk_pciephy1_div_clk>,
1359 <&optfclk_pciephy_div>,
1360 <&sys_clkin1>;
1361 clock-names = "dpll_ref", "dpll_ref_m2",
1362 "wkupclk", "refclk",
1363 "div-clk", "phy-div", "sysclk";
1364 #phy-cells = <0>;
1365 };
1366
1367 pcie2_phy: pciephy@4a095000 {
1368 compatible = "ti,phy-pipe3-pcie";
1369 reg = <0x4a095000 0x80>, /* phy_rx */
1370 <0x4a095400 0x64>; /* phy_tx */
1371 reg-names = "phy_rx", "phy_tx";
1372 syscon-phy-power = <&scm_conf_pcie 0x20>;
1373 syscon-pcs = <&scm_conf_pcie 0x10>;
1374 clocks = <&dpll_pcie_ref_ck>,
1375 <&dpll_pcie_ref_m2ldo_ck>,
1376 <&optfclk_pciephy2_32khz>,
1377 <&optfclk_pciephy2_clk>,
1378 <&optfclk_pciephy2_div_clk>,
1379 <&optfclk_pciephy_div>,
1380 <&sys_clkin1>;
1381 clock-names = "dpll_ref", "dpll_ref_m2",
1382 "wkupclk", "refclk",
1383 "div-clk", "phy-div", "sysclk";
1384 #phy-cells = <0>;
1385 status = "disabled";
1386 };
1387 };
1388
1389 sata: sata@4a141100 {
1390 compatible = "snps,dwc-ahci";
1391 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1392 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1393 phys = <&sata_phy>;
1394 phy-names = "sata-phy";
1395 clocks = <&sata_ref_clk>;
1396 ti,hwmods = "sata";
1397 ports-implemented = <0x1>;
1398 };
1399
1400 rtc: rtc@48838000 {
1401 compatible = "ti,am3352-rtc";
1402 reg = <0x48838000 0x100>;
1403 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1405 ti,hwmods = "rtcss";
1406 clocks = <&sys_32k_ck>;
1407 };
1408
1409 /* OCP2SCP1 */
1410 ocp2scp@4a080000 {
1411 compatible = "ti,omap-ocp2scp";
1412 #address-cells = <1>;
1413 #size-cells = <1>;
1414 ranges;
1415 reg = <0x4a080000 0x20>;
1416 ti,hwmods = "ocp2scp1";
1417
1418 usb2_phy1: phy@4a084000 {
1419 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1420 reg = <0x4a084000 0x400>;
1421 syscon-phy-power = <&scm_conf 0x300>;
1422 clocks = <&usb_phy1_always_on_clk32k>,
1423 <&usb_otg_ss1_refclk960m>;
1424 clock-names = "wkupclk",
1425 "refclk";
1426 #phy-cells = <0>;
1427 };
1428
1429 usb2_phy2: phy@4a085000 {
1430 compatible = "ti,dra7x-usb2-phy2",
1431 "ti,omap-usb2";
1432 reg = <0x4a085000 0x400>;
1433 syscon-phy-power = <&scm_conf 0xe74>;
1434 clocks = <&usb_phy2_always_on_clk32k>,
1435 <&usb_otg_ss2_refclk960m>;
1436 clock-names = "wkupclk",
1437 "refclk";
1438 #phy-cells = <0>;
1439 };
1440
1441 usb3_phy1: phy@4a084400 {
1442 compatible = "ti,omap-usb3";
1443 reg = <0x4a084400 0x80>,
1444 <0x4a084800 0x64>,
1445 <0x4a084c00 0x40>;
1446 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1447 syscon-phy-power = <&scm_conf 0x370>;
1448 clocks = <&usb_phy3_always_on_clk32k>,
1449 <&sys_clkin1>,
1450 <&usb_otg_ss1_refclk960m>;
1451 clock-names = "wkupclk",
1452 "sysclk",
1453 "refclk";
1454 #phy-cells = <0>;
1455 };
1456 };
1457
1458 omap_dwc3_1: omap_dwc3_1@48880000 {
1459 compatible = "ti,dwc3";
1460 ti,hwmods = "usb_otg_ss1";
1461 reg = <0x48880000 0x10000>;
1462 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1463 #address-cells = <1>;
1464 #size-cells = <1>;
1465 utmi-mode = <2>;
1466 ranges;
1467 usb1: usb@48890000 {
1468 compatible = "snps,dwc3";
1469 reg = <0x48890000 0x17000>;
1470 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1473 interrupt-names = "peripheral",
1474 "host",
1475 "otg";
1476 phys = <&usb2_phy1>, <&usb3_phy1>;
1477 phy-names = "usb2-phy", "usb3-phy";
1478 maximum-speed = "super-speed";
1479 dr_mode = "otg";
1480 snps,dis_u3_susphy_quirk;
1481 snps,dis_u2_susphy_quirk;
1482 };
1483 };
1484
1485 omap_dwc3_2: omap_dwc3_2@488c0000 {
1486 compatible = "ti,dwc3";
1487 ti,hwmods = "usb_otg_ss2";
1488 reg = <0x488c0000 0x10000>;
1489 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1490 #address-cells = <1>;
1491 #size-cells = <1>;
1492 utmi-mode = <2>;
1493 ranges;
1494 usb2: usb@488d0000 {
1495 compatible = "snps,dwc3";
1496 reg = <0x488d0000 0x17000>;
1497 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1498 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1499 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1500 interrupt-names = "peripheral",
1501 "host",
1502 "otg";
1503 phys = <&usb2_phy2>;
1504 phy-names = "usb2-phy";
1505 maximum-speed = "high-speed";
1506 dr_mode = "otg";
1507 snps,dis_u3_susphy_quirk;
1508 snps,dis_u2_susphy_quirk;
1509 };
1510 };
1511
1512 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1513 omap_dwc3_3: omap_dwc3_3@48900000 {
1514 compatible = "ti,dwc3";
1515 ti,hwmods = "usb_otg_ss3";
1516 reg = <0x48900000 0x10000>;
1517 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1518 #address-cells = <1>;
1519 #size-cells = <1>;
1520 utmi-mode = <2>;
1521 ranges;
1522 status = "disabled";
1523 usb3: usb@48910000 {
1524 compatible = "snps,dwc3";
1525 reg = <0x48910000 0x17000>;
1526 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1529 interrupt-names = "peripheral",
1530 "host",
1531 "otg";
1532 maximum-speed = "high-speed";
1533 dr_mode = "otg";
1534 snps,dis_u3_susphy_quirk;
1535 snps,dis_u2_susphy_quirk;
1536 };
1537 };
1538
1539 elm: elm@48078000 {
1540 compatible = "ti,am3352-elm";
1541 reg = <0x48078000 0xfc0>; /* device IO registers */
1542 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1543 ti,hwmods = "elm";
1544 status = "disabled";
1545 };
1546
1547 gpmc: gpmc@50000000 {
1548 compatible = "ti,am3352-gpmc";
1549 ti,hwmods = "gpmc";
1550 reg = <0x50000000 0x37c>; /* device IO registers */
1551 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1552 dmas = <&edma_xbar 4 0>;
1553 dma-names = "rxtx";
1554 gpmc,num-cs = <8>;
1555 gpmc,num-waitpins = <2>;
1556 #address-cells = <2>;
1557 #size-cells = <1>;
1558 interrupt-controller;
1559 #interrupt-cells = <2>;
1560 gpio-controller;
1561 #gpio-cells = <2>;
1562 status = "disabled";
1563 };
1564
1565 atl: atl@4843c000 {
1566 compatible = "ti,dra7-atl";
1567 reg = <0x4843c000 0x3ff>;
1568 ti,hwmods = "atl";
1569 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1570 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1571 clocks = <&atl_gfclk_mux>;
1572 clock-names = "fck";
1573 status = "disabled";
1574 };
1575
1576 mcasp1: mcasp@48460000 {
1577 compatible = "ti,dra7-mcasp-audio";
1578 ti,hwmods = "mcasp1";
1579 reg = <0x48460000 0x2000>,
1580 <0x45800000 0x1000>;
1581 reg-names = "mpu","dat";
1582 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1583 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1584 interrupt-names = "tx", "rx";
1585 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1586 dma-names = "tx", "rx";
1587 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1588 <&mcasp1_ahclkr_mux>;
1589 clock-names = "fck", "ahclkx", "ahclkr";
1590 status = "disabled";
1591 };
1592
1593 mcasp2: mcasp@48464000 {
1594 compatible = "ti,dra7-mcasp-audio";
1595 ti,hwmods = "mcasp2";
1596 reg = <0x48464000 0x2000>,
1597 <0x45c00000 0x1000>;
1598 reg-names = "mpu","dat";
1599 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1600 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1601 interrupt-names = "tx", "rx";
1602 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1603 dma-names = "tx", "rx";
1604 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1605 <&mcasp2_ahclkr_mux>;
1606 clock-names = "fck", "ahclkx", "ahclkr";
1607 status = "disabled";
1608 };
1609
1610 mcasp3: mcasp@48468000 {
1611 compatible = "ti,dra7-mcasp-audio";
1612 ti,hwmods = "mcasp3";
1613 reg = <0x48468000 0x2000>,
1614 <0x46000000 0x1000>;
1615 reg-names = "mpu","dat";
1616 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1617 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1618 interrupt-names = "tx", "rx";
1619 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1620 dma-names = "tx", "rx";
1621 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1622 clock-names = "fck", "ahclkx";
1623 status = "disabled";
1624 };
1625
1626 mcasp4: mcasp@4846c000 {
1627 compatible = "ti,dra7-mcasp-audio";
1628 ti,hwmods = "mcasp4";
1629 reg = <0x4846c000 0x2000>,
1630 <0x48436000 0x1000>;
1631 reg-names = "mpu","dat";
1632 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1633 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1634 interrupt-names = "tx", "rx";
1635 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1636 dma-names = "tx", "rx";
1637 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1638 clock-names = "fck", "ahclkx";
1639 status = "disabled";
1640 };
1641
1642 mcasp5: mcasp@48470000 {
1643 compatible = "ti,dra7-mcasp-audio";
1644 ti,hwmods = "mcasp5";
1645 reg = <0x48470000 0x2000>,
1646 <0x4843a000 0x1000>;
1647 reg-names = "mpu","dat";
1648 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1649 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1650 interrupt-names = "tx", "rx";
1651 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1652 dma-names = "tx", "rx";
1653 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1654 clock-names = "fck", "ahclkx";
1655 status = "disabled";
1656 };
1657
1658 mcasp6: mcasp@48474000 {
1659 compatible = "ti,dra7-mcasp-audio";
1660 ti,hwmods = "mcasp6";
1661 reg = <0x48474000 0x2000>,
1662 <0x4844c000 0x1000>;
1663 reg-names = "mpu","dat";
1664 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1665 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1666 interrupt-names = "tx", "rx";
1667 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1668 dma-names = "tx", "rx";
1669 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1670 clock-names = "fck", "ahclkx";
1671 status = "disabled";
1672 };
1673
1674 mcasp7: mcasp@48478000 {
1675 compatible = "ti,dra7-mcasp-audio";
1676 ti,hwmods = "mcasp7";
1677 reg = <0x48478000 0x2000>,
1678 <0x48450000 0x1000>;
1679 reg-names = "mpu","dat";
1680 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1681 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1682 interrupt-names = "tx", "rx";
1683 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1684 dma-names = "tx", "rx";
1685 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1686 clock-names = "fck", "ahclkx";
1687 status = "disabled";
1688 };
1689
1690 mcasp8: mcasp@4847c000 {
1691 compatible = "ti,dra7-mcasp-audio";
1692 ti,hwmods = "mcasp8";
1693 reg = <0x4847c000 0x2000>,
1694 <0x48454000 0x1000>;
1695 reg-names = "mpu","dat";
1696 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1697 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1698 interrupt-names = "tx", "rx";
1699 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1700 dma-names = "tx", "rx";
1701 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1702 clock-names = "fck", "ahclkx";
1703 status = "disabled";
1704 };
1705
1706 crossbar_mpu: crossbar@4a002a48 {
1707 compatible = "ti,irq-crossbar";
1708 reg = <0x4a002a48 0x130>;
1709 interrupt-controller;
1710 interrupt-parent = <&wakeupgen>;
1711 #interrupt-cells = <3>;
1712 ti,max-irqs = <160>;
1713 ti,max-crossbar-sources = <MAX_SOURCES>;
1714 ti,reg-size = <2>;
1715 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1716 ti,irqs-skip = <10 133 139 140>;
1717 ti,irqs-safe-map = <0>;
1718 };
1719
1720 mac: ethernet@48484000 {
1721 compatible = "ti,dra7-cpsw","ti,cpsw";
1722 ti,hwmods = "gmac";
1723 clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
1724 clock-names = "fck", "cpts";
1725 cpdma_channels = <8>;
1726 ale_entries = <1024>;
1727 bd_ram_size = <0x2000>;
1728 mac_control = <0x20>;
1729 slaves = <2>;
1730 active_slave = <0>;
1731 cpts_clock_mult = <0x784CFE14>;
1732 cpts_clock_shift = <29>;
1733 reg = <0x48484000 0x1000
1734 0x48485200 0x2E00>;
1735 #address-cells = <1>;
1736 #size-cells = <1>;
1737
1738 /*
1739 * Do not allow gating of cpsw clock as workaround
1740 * for errata i877. Keeping internal clock disabled
1741 * causes the device switching characteristics
1742 * to degrade over time and eventually fail to meet
1743 * the data manual delay time/skew specs.
1744 */
1745 ti,no-idle;
1746
1747 /*
1748 * rx_thresh_pend
1749 * rx_pend
1750 * tx_pend
1751 * misc_pend
1752 */
1753 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1754 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1755 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1756 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1757 ranges;
1758 syscon = <&scm_conf>;
1759 status = "disabled";
1760
1761 davinci_mdio: mdio@48485000 {
1762 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1765 ti,hwmods = "davinci_mdio";
1766 bus_freq = <1000000>;
1767 reg = <0x48485000 0x100>;
1768 };
1769
1770 cpsw_emac0: slave@48480200 {
1771 /* Filled in by U-Boot */
1772 mac-address = [ 00 00 00 00 00 00 ];
1773 };
1774
1775 cpsw_emac1: slave@48480300 {
1776 /* Filled in by U-Boot */
1777 mac-address = [ 00 00 00 00 00 00 ];
1778 };
1779
1780 phy_sel: cpsw-phy-sel@4a002554 {
1781 compatible = "ti,dra7xx-cpsw-phy-sel";
1782 reg= <0x4a002554 0x4>;
1783 reg-names = "gmii-sel";
1784 };
1785 };
1786
1787 dcan1: can@481cc000 {
1788 compatible = "ti,dra7-d_can";
1789 ti,hwmods = "dcan1";
1790 reg = <0x4ae3c000 0x2000>;
1791 syscon-raminit = <&scm_conf 0x558 0>;
1792 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1793 clocks = <&dcan1_sys_clk_mux>;
1794 status = "disabled";
1795 };
1796
1797 dcan2: can@481d0000 {
1798 compatible = "ti,dra7-d_can";
1799 ti,hwmods = "dcan2";
1800 reg = <0x48480000 0x2000>;
1801 syscon-raminit = <&scm_conf 0x558 1>;
1802 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1803 clocks = <&sys_clkin1>;
1804 status = "disabled";
1805 };
1806
1807 dss: dss@58000000 {
1808 compatible = "ti,dra7-dss";
1809 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1810 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1811 status = "disabled";
1812 ti,hwmods = "dss_core";
1813 /* CTRL_CORE_DSS_PLL_CONTROL */
1814 syscon-pll-ctrl = <&scm_conf 0x538>;
1815 #address-cells = <1>;
1816 #size-cells = <1>;
1817 ranges;
1818
1819 dispc@58001000 {
1820 compatible = "ti,dra7-dispc";
1821 reg = <0x58001000 0x1000>;
1822 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1823 ti,hwmods = "dss_dispc";
1824 clocks = <&dss_dss_clk>;
1825 clock-names = "fck";
1826 /* CTRL_CORE_SMA_SW_1 */
1827 syscon-pol = <&scm_conf 0x534>;
1828 };
1829
1830 hdmi: encoder@58060000 {
1831 compatible = "ti,dra7-hdmi";
1832 reg = <0x58040000 0x200>,
1833 <0x58040200 0x80>,
1834 <0x58040300 0x80>,
1835 <0x58060000 0x19000>;
1836 reg-names = "wp", "pll", "phy", "core";
1837 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1838 status = "disabled";
1839 ti,hwmods = "dss_hdmi";
1840 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1841 clock-names = "fck", "sys_clk";
1842 };
1843 };
1844
1845 epwmss0: epwmss@4843e000 {
1846 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1847 reg = <0x4843e000 0x30>;
1848 ti,hwmods = "epwmss0";
1849 #address-cells = <1>;
1850 #size-cells = <1>;
1851 status = "disabled";
1852 ranges;
1853
1854 ehrpwm0: pwm@4843e200 {
1855 compatible = "ti,dra746-ehrpwm",
1856 "ti,am3352-ehrpwm";
1857 #pwm-cells = <3>;
1858 reg = <0x4843e200 0x80>;
1859 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1860 clock-names = "tbclk", "fck";
1861 status = "disabled";
1862 };
1863
1864 ecap0: ecap@4843e100 {
1865 compatible = "ti,dra746-ecap",
1866 "ti,am3352-ecap";
1867 #pwm-cells = <3>;
1868 reg = <0x4843e100 0x80>;
1869 clocks = <&l4_root_clk_div>;
1870 clock-names = "fck";
1871 status = "disabled";
1872 };
1873 };
1874
1875 epwmss1: epwmss@48440000 {
1876 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1877 reg = <0x48440000 0x30>;
1878 ti,hwmods = "epwmss1";
1879 #address-cells = <1>;
1880 #size-cells = <1>;
1881 status = "disabled";
1882 ranges;
1883
1884 ehrpwm1: pwm@48440200 {
1885 compatible = "ti,dra746-ehrpwm",
1886 "ti,am3352-ehrpwm";
1887 #pwm-cells = <3>;
1888 reg = <0x48440200 0x80>;
1889 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1890 clock-names = "tbclk", "fck";
1891 status = "disabled";
1892 };
1893
1894 ecap1: ecap@48440100 {
1895 compatible = "ti,dra746-ecap",
1896 "ti,am3352-ecap";
1897 #pwm-cells = <3>;
1898 reg = <0x48440100 0x80>;
1899 clocks = <&l4_root_clk_div>;
1900 clock-names = "fck";
1901 status = "disabled";
1902 };
1903 };
1904
1905 epwmss2: epwmss@48442000 {
1906 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1907 reg = <0x48442000 0x30>;
1908 ti,hwmods = "epwmss2";
1909 #address-cells = <1>;
1910 #size-cells = <1>;
1911 status = "disabled";
1912 ranges;
1913
1914 ehrpwm2: pwm@48442200 {
1915 compatible = "ti,dra746-ehrpwm",
1916 "ti,am3352-ehrpwm";
1917 #pwm-cells = <3>;
1918 reg = <0x48442200 0x80>;
1919 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1920 clock-names = "tbclk", "fck";
1921 status = "disabled";
1922 };
1923
1924 ecap2: ecap@48442100 {
1925 compatible = "ti,dra746-ecap",
1926 "ti,am3352-ecap";
1927 #pwm-cells = <3>;
1928 reg = <0x48442100 0x80>;
1929 clocks = <&l4_root_clk_div>;
1930 clock-names = "fck";
1931 status = "disabled";
1932 };
1933 };
1934
1935 aes1: aes@4b500000 {
1936 compatible = "ti,omap4-aes";
1937 ti,hwmods = "aes1";
1938 reg = <0x4b500000 0xa0>;
1939 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1940 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1941 dma-names = "tx", "rx";
1942 clocks = <&l3_iclk_div>;
1943 clock-names = "fck";
1944 };
1945
1946 aes2: aes@4b700000 {
1947 compatible = "ti,omap4-aes";
1948 ti,hwmods = "aes2";
1949 reg = <0x4b700000 0xa0>;
1950 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1951 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1952 dma-names = "tx", "rx";
1953 clocks = <&l3_iclk_div>;
1954 clock-names = "fck";
1955 };
1956
1957 des: des@480a5000 {
1958 compatible = "ti,omap4-des";
1959 ti,hwmods = "des";
1960 reg = <0x480a5000 0xa0>;
1961 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1962 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
1963 dma-names = "tx", "rx";
1964 clocks = <&l3_iclk_div>;
1965 clock-names = "fck";
1966 };
1967
1968 sham: sham@53100000 {
1969 compatible = "ti,omap5-sham";
1970 ti,hwmods = "sham";
1971 reg = <0x4b101000 0x300>;
1972 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1973 dmas = <&edma_xbar 119 0>;
1974 dma-names = "rx";
1975 clocks = <&l3_iclk_div>;
1976 clock-names = "fck";
1977 };
1978
1979 rng: rng@48090000 {
1980 compatible = "ti,omap4-rng";
1981 ti,hwmods = "rng";
1982 reg = <0x48090000 0x2000>;
1983 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1984 clocks = <&l3_iclk_div>;
1985 clock-names = "fck";
1986 };
1987 };
1988
1989 thermal_zones: thermal-zones {
1990 #include "omap4-cpu-thermal.dtsi"
1991 #include "omap5-gpu-thermal.dtsi"
1992 #include "omap5-core-thermal.dtsi"
1993 #include "dra7-dspeve-thermal.dtsi"
1994 #include "dra7-iva-thermal.dtsi"
1995 };
1996
1997 };
1998
1999 &cpu_thermal {
2000 polling-delay = <500>; /* milliseconds */
2001 coefficients = <0 2000>;
2002 };
2003
2004 &gpu_thermal {
2005 coefficients = <0 2000>;
2006 };
2007
2008 &core_thermal {
2009 coefficients = <0 2000>;
2010 };
2011
2012 &dspeve_thermal {
2013 coefficients = <0 2000>;
2014 };
2015
2016 &iva_thermal {
2017 coefficients = <0 2000>;
2018 };
2019
2020 &cpu_crit {
2021 temperature = <120000>; /* milli Celsius */
2022 };
2023
2024 /include/ "dra7xx-clocks.dtsi"
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