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Merge branch 'x86-asm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / dra7.dtsi
1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12
13 #include "skeleton.dtsi"
14
15 #define MAX_SOURCES 400
16
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 compatible = "ti,dra7xx";
22 interrupt-parent = <&crossbar_mpu>;
23
24 aliases {
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
44 spi0 = &qspi;
45 };
46
47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 interrupt-parent = <&gic>;
54 };
55
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
60 reg = <0x48211000 0x1000>,
61 <0x48212000 0x1000>,
62 <0x48214000 0x2000>,
63 <0x48216000 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 interrupt-parent = <&gic>;
66 };
67
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 reg = <0x48281000 0x1000>;
73 interrupt-parent = <&gic>;
74 };
75
76 /*
77 * The soc node represents the soc top level view. It is used for IPs
78 * that are not memory mapped in the MPU view or for the MPU itself.
79 */
80 soc {
81 compatible = "ti,omap-infra";
82 mpu {
83 compatible = "ti,omap5-mpu";
84 ti,hwmods = "mpu";
85 };
86 };
87
88 /*
89 * XXX: Use a flat representation of the SOC interconnect.
90 * The real OMAP interconnect network is quite complex.
91 * Since it will not bring real advantage to represent that in DT for
92 * the moment, just use a fake OCP bus entry to represent the whole bus
93 * hierarchy.
94 */
95 ocp {
96 compatible = "ti,dra7-l3-noc", "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
100 ti,hwmods = "l3_main_1", "l3_main_2";
101 reg = <0x44000000 0x1000000>,
102 <0x45000000 0x1000>;
103 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
104 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
105
106 l4_cfg: l4@4a000000 {
107 compatible = "ti,dra7-l4-cfg", "simple-bus";
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0 0x4a000000 0x22c000>;
111
112 scm: scm@2000 {
113 compatible = "ti,dra7-scm-core", "simple-bus";
114 reg = <0x2000 0x2000>;
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges = <0 0x2000 0x2000>;
118
119 scm_conf: scm_conf@0 {
120 compatible = "syscon", "simple-bus";
121 reg = <0x0 0x1400>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges = <0 0x0 0x1400>;
125
126 pbias_regulator: pbias_regulator {
127 compatible = "ti,pbias-dra7", "ti,pbias-omap";
128 reg = <0xe00 0x4>;
129 syscon = <&scm_conf>;
130 pbias_mmc_reg: pbias_mmc_omap5 {
131 regulator-name = "pbias_mmc_omap5";
132 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <3000000>;
134 };
135 };
136
137 scm_conf_clocks: clocks {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 };
141 };
142
143 dra7_pmx_core: pinmux@1400 {
144 compatible = "ti,dra7-padconf",
145 "pinctrl-single";
146 reg = <0x1400 0x0468>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
151 pinctrl-single,register-width = <32>;
152 pinctrl-single,function-mask = <0x3fffffff>;
153 };
154
155 scm_conf1: scm_conf@1c04 {
156 compatible = "syscon";
157 reg = <0x1c04 0x0020>;
158 };
159 };
160
161 cm_core_aon: cm_core_aon@5000 {
162 compatible = "ti,dra7-cm-core-aon";
163 reg = <0x5000 0x2000>;
164
165 cm_core_aon_clocks: clocks {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 };
169
170 cm_core_aon_clockdomains: clockdomains {
171 };
172 };
173
174 cm_core: cm_core@8000 {
175 compatible = "ti,dra7-cm-core";
176 reg = <0x8000 0x3000>;
177
178 cm_core_clocks: clocks {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 };
182
183 cm_core_clockdomains: clockdomains {
184 };
185 };
186 };
187
188 l4_wkup: l4@4ae00000 {
189 compatible = "ti,dra7-l4-wkup", "simple-bus";
190 #address-cells = <1>;
191 #size-cells = <1>;
192 ranges = <0 0x4ae00000 0x3f000>;
193
194 counter32k: counter@4000 {
195 compatible = "ti,omap-counter32k";
196 reg = <0x4000 0x40>;
197 ti,hwmods = "counter_32k";
198 };
199
200 prm: prm@6000 {
201 compatible = "ti,dra7-prm";
202 reg = <0x6000 0x3000>;
203 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
204
205 prm_clocks: clocks {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 };
209
210 prm_clockdomains: clockdomains {
211 };
212 };
213 };
214
215 axi@0 {
216 compatible = "simple-bus";
217 #size-cells = <1>;
218 #address-cells = <1>;
219 ranges = <0x51000000 0x51000000 0x3000
220 0x0 0x20000000 0x10000000>;
221 pcie1: pcie@51000000 {
222 compatible = "ti,dra7-pcie";
223 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
224 reg-names = "rc_dbics", "ti_conf", "config";
225 interrupts = <0 232 0x4>, <0 233 0x4>;
226 #address-cells = <3>;
227 #size-cells = <2>;
228 device_type = "pci";
229 ranges = <0x81000000 0 0 0x03000 0 0x00010000
230 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
231 #interrupt-cells = <1>;
232 num-lanes = <1>;
233 ti,hwmods = "pcie1";
234 phys = <&pcie1_phy>;
235 phy-names = "pcie-phy0";
236 interrupt-map-mask = <0 0 0 7>;
237 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
238 <0 0 0 2 &pcie1_intc 2>,
239 <0 0 0 3 &pcie1_intc 3>,
240 <0 0 0 4 &pcie1_intc 4>;
241 pcie1_intc: interrupt-controller {
242 interrupt-controller;
243 #address-cells = <0>;
244 #interrupt-cells = <1>;
245 };
246 };
247 };
248
249 axi@1 {
250 compatible = "simple-bus";
251 #size-cells = <1>;
252 #address-cells = <1>;
253 ranges = <0x51800000 0x51800000 0x3000
254 0x0 0x30000000 0x10000000>;
255 status = "disabled";
256 pcie@51000000 {
257 compatible = "ti,dra7-pcie";
258 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
259 reg-names = "rc_dbics", "ti_conf", "config";
260 interrupts = <0 355 0x4>, <0 356 0x4>;
261 #address-cells = <3>;
262 #size-cells = <2>;
263 device_type = "pci";
264 ranges = <0x81000000 0 0 0x03000 0 0x00010000
265 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
266 #interrupt-cells = <1>;
267 num-lanes = <1>;
268 ti,hwmods = "pcie2";
269 phys = <&pcie2_phy>;
270 phy-names = "pcie-phy0";
271 interrupt-map-mask = <0 0 0 7>;
272 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
273 <0 0 0 2 &pcie2_intc 2>,
274 <0 0 0 3 &pcie2_intc 3>,
275 <0 0 0 4 &pcie2_intc 4>;
276 pcie2_intc: interrupt-controller {
277 interrupt-controller;
278 #address-cells = <0>;
279 #interrupt-cells = <1>;
280 };
281 };
282 };
283
284 bandgap: bandgap@4a0021e0 {
285 reg = <0x4a0021e0 0xc
286 0x4a00232c 0xc
287 0x4a002380 0x2c
288 0x4a0023C0 0x3c
289 0x4a002564 0x8
290 0x4a002574 0x50>;
291 compatible = "ti,dra752-bandgap";
292 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
293 #thermal-sensor-cells = <1>;
294 };
295
296 dsp1_system: dsp_system@40d00000 {
297 compatible = "syscon";
298 reg = <0x40d00000 0x100>;
299 };
300
301 sdma: dma-controller@4a056000 {
302 compatible = "ti,omap4430-sdma";
303 reg = <0x4a056000 0x1000>;
304 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
308 #dma-cells = <1>;
309 dma-channels = <32>;
310 dma-requests = <127>;
311 };
312
313 sdma_xbar: dma-router@4a002b78 {
314 compatible = "ti,dra7-dma-crossbar";
315 reg = <0x4a002b78 0xfc>;
316 #dma-cells = <1>;
317 dma-requests = <205>;
318 ti,dma-safe-map = <0>;
319 dma-masters = <&sdma>;
320 };
321
322 gpio1: gpio@4ae10000 {
323 compatible = "ti,omap4-gpio";
324 reg = <0x4ae10000 0x200>;
325 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
326 ti,hwmods = "gpio1";
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 };
332
333 gpio2: gpio@48055000 {
334 compatible = "ti,omap4-gpio";
335 reg = <0x48055000 0x200>;
336 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
337 ti,hwmods = "gpio2";
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 };
343
344 gpio3: gpio@48057000 {
345 compatible = "ti,omap4-gpio";
346 reg = <0x48057000 0x200>;
347 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
348 ti,hwmods = "gpio3";
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
354
355 gpio4: gpio@48059000 {
356 compatible = "ti,omap4-gpio";
357 reg = <0x48059000 0x200>;
358 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
359 ti,hwmods = "gpio4";
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 };
365
366 gpio5: gpio@4805b000 {
367 compatible = "ti,omap4-gpio";
368 reg = <0x4805b000 0x200>;
369 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
370 ti,hwmods = "gpio5";
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 };
376
377 gpio6: gpio@4805d000 {
378 compatible = "ti,omap4-gpio";
379 reg = <0x4805d000 0x200>;
380 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
381 ti,hwmods = "gpio6";
382 gpio-controller;
383 #gpio-cells = <2>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 };
387
388 gpio7: gpio@48051000 {
389 compatible = "ti,omap4-gpio";
390 reg = <0x48051000 0x200>;
391 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
392 ti,hwmods = "gpio7";
393 gpio-controller;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 };
398
399 gpio8: gpio@48053000 {
400 compatible = "ti,omap4-gpio";
401 reg = <0x48053000 0x200>;
402 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
403 ti,hwmods = "gpio8";
404 gpio-controller;
405 #gpio-cells = <2>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 };
409
410 uart1: serial@4806a000 {
411 compatible = "ti,dra742-uart", "ti,omap4-uart";
412 reg = <0x4806a000 0x100>;
413 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "uart1";
415 clock-frequency = <48000000>;
416 status = "disabled";
417 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
418 dma-names = "tx", "rx";
419 };
420
421 uart2: serial@4806c000 {
422 compatible = "ti,dra742-uart", "ti,omap4-uart";
423 reg = <0x4806c000 0x100>;
424 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
425 ti,hwmods = "uart2";
426 clock-frequency = <48000000>;
427 status = "disabled";
428 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
429 dma-names = "tx", "rx";
430 };
431
432 uart3: serial@48020000 {
433 compatible = "ti,dra742-uart", "ti,omap4-uart";
434 reg = <0x48020000 0x100>;
435 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
436 ti,hwmods = "uart3";
437 clock-frequency = <48000000>;
438 status = "disabled";
439 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
440 dma-names = "tx", "rx";
441 };
442
443 uart4: serial@4806e000 {
444 compatible = "ti,dra742-uart", "ti,omap4-uart";
445 reg = <0x4806e000 0x100>;
446 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
447 ti,hwmods = "uart4";
448 clock-frequency = <48000000>;
449 status = "disabled";
450 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
451 dma-names = "tx", "rx";
452 };
453
454 uart5: serial@48066000 {
455 compatible = "ti,dra742-uart", "ti,omap4-uart";
456 reg = <0x48066000 0x100>;
457 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
458 ti,hwmods = "uart5";
459 clock-frequency = <48000000>;
460 status = "disabled";
461 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
462 dma-names = "tx", "rx";
463 };
464
465 uart6: serial@48068000 {
466 compatible = "ti,dra742-uart", "ti,omap4-uart";
467 reg = <0x48068000 0x100>;
468 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
469 ti,hwmods = "uart6";
470 clock-frequency = <48000000>;
471 status = "disabled";
472 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
473 dma-names = "tx", "rx";
474 };
475
476 uart7: serial@48420000 {
477 compatible = "ti,dra742-uart", "ti,omap4-uart";
478 reg = <0x48420000 0x100>;
479 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
480 ti,hwmods = "uart7";
481 clock-frequency = <48000000>;
482 status = "disabled";
483 };
484
485 uart8: serial@48422000 {
486 compatible = "ti,dra742-uart", "ti,omap4-uart";
487 reg = <0x48422000 0x100>;
488 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
489 ti,hwmods = "uart8";
490 clock-frequency = <48000000>;
491 status = "disabled";
492 };
493
494 uart9: serial@48424000 {
495 compatible = "ti,dra742-uart", "ti,omap4-uart";
496 reg = <0x48424000 0x100>;
497 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
498 ti,hwmods = "uart9";
499 clock-frequency = <48000000>;
500 status = "disabled";
501 };
502
503 uart10: serial@4ae2b000 {
504 compatible = "ti,dra742-uart", "ti,omap4-uart";
505 reg = <0x4ae2b000 0x100>;
506 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
507 ti,hwmods = "uart10";
508 clock-frequency = <48000000>;
509 status = "disabled";
510 };
511
512 mailbox1: mailbox@4a0f4000 {
513 compatible = "ti,omap4-mailbox";
514 reg = <0x4a0f4000 0x200>;
515 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
518 ti,hwmods = "mailbox1";
519 #mbox-cells = <1>;
520 ti,mbox-num-users = <3>;
521 ti,mbox-num-fifos = <8>;
522 status = "disabled";
523 };
524
525 mailbox2: mailbox@4883a000 {
526 compatible = "ti,omap4-mailbox";
527 reg = <0x4883a000 0x200>;
528 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
532 ti,hwmods = "mailbox2";
533 #mbox-cells = <1>;
534 ti,mbox-num-users = <4>;
535 ti,mbox-num-fifos = <12>;
536 status = "disabled";
537 };
538
539 mailbox3: mailbox@4883c000 {
540 compatible = "ti,omap4-mailbox";
541 reg = <0x4883c000 0x200>;
542 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
546 ti,hwmods = "mailbox3";
547 #mbox-cells = <1>;
548 ti,mbox-num-users = <4>;
549 ti,mbox-num-fifos = <12>;
550 status = "disabled";
551 };
552
553 mailbox4: mailbox@4883e000 {
554 compatible = "ti,omap4-mailbox";
555 reg = <0x4883e000 0x200>;
556 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
560 ti,hwmods = "mailbox4";
561 #mbox-cells = <1>;
562 ti,mbox-num-users = <4>;
563 ti,mbox-num-fifos = <12>;
564 status = "disabled";
565 };
566
567 mailbox5: mailbox@48840000 {
568 compatible = "ti,omap4-mailbox";
569 reg = <0x48840000 0x200>;
570 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
574 ti,hwmods = "mailbox5";
575 #mbox-cells = <1>;
576 ti,mbox-num-users = <4>;
577 ti,mbox-num-fifos = <12>;
578 status = "disabled";
579 };
580
581 mailbox6: mailbox@48842000 {
582 compatible = "ti,omap4-mailbox";
583 reg = <0x48842000 0x200>;
584 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
588 ti,hwmods = "mailbox6";
589 #mbox-cells = <1>;
590 ti,mbox-num-users = <4>;
591 ti,mbox-num-fifos = <12>;
592 status = "disabled";
593 };
594
595 mailbox7: mailbox@48844000 {
596 compatible = "ti,omap4-mailbox";
597 reg = <0x48844000 0x200>;
598 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
602 ti,hwmods = "mailbox7";
603 #mbox-cells = <1>;
604 ti,mbox-num-users = <4>;
605 ti,mbox-num-fifos = <12>;
606 status = "disabled";
607 };
608
609 mailbox8: mailbox@48846000 {
610 compatible = "ti,omap4-mailbox";
611 reg = <0x48846000 0x200>;
612 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
616 ti,hwmods = "mailbox8";
617 #mbox-cells = <1>;
618 ti,mbox-num-users = <4>;
619 ti,mbox-num-fifos = <12>;
620 status = "disabled";
621 };
622
623 mailbox9: mailbox@4885e000 {
624 compatible = "ti,omap4-mailbox";
625 reg = <0x4885e000 0x200>;
626 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
630 ti,hwmods = "mailbox9";
631 #mbox-cells = <1>;
632 ti,mbox-num-users = <4>;
633 ti,mbox-num-fifos = <12>;
634 status = "disabled";
635 };
636
637 mailbox10: mailbox@48860000 {
638 compatible = "ti,omap4-mailbox";
639 reg = <0x48860000 0x200>;
640 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
644 ti,hwmods = "mailbox10";
645 #mbox-cells = <1>;
646 ti,mbox-num-users = <4>;
647 ti,mbox-num-fifos = <12>;
648 status = "disabled";
649 };
650
651 mailbox11: mailbox@48862000 {
652 compatible = "ti,omap4-mailbox";
653 reg = <0x48862000 0x200>;
654 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
658 ti,hwmods = "mailbox11";
659 #mbox-cells = <1>;
660 ti,mbox-num-users = <4>;
661 ti,mbox-num-fifos = <12>;
662 status = "disabled";
663 };
664
665 mailbox12: mailbox@48864000 {
666 compatible = "ti,omap4-mailbox";
667 reg = <0x48864000 0x200>;
668 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
672 ti,hwmods = "mailbox12";
673 #mbox-cells = <1>;
674 ti,mbox-num-users = <4>;
675 ti,mbox-num-fifos = <12>;
676 status = "disabled";
677 };
678
679 mailbox13: mailbox@48802000 {
680 compatible = "ti,omap4-mailbox";
681 reg = <0x48802000 0x200>;
682 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
686 ti,hwmods = "mailbox13";
687 #mbox-cells = <1>;
688 ti,mbox-num-users = <4>;
689 ti,mbox-num-fifos = <12>;
690 status = "disabled";
691 };
692
693 timer1: timer@4ae18000 {
694 compatible = "ti,omap5430-timer";
695 reg = <0x4ae18000 0x80>;
696 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
697 ti,hwmods = "timer1";
698 ti,timer-alwon;
699 };
700
701 timer2: timer@48032000 {
702 compatible = "ti,omap5430-timer";
703 reg = <0x48032000 0x80>;
704 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
705 ti,hwmods = "timer2";
706 };
707
708 timer3: timer@48034000 {
709 compatible = "ti,omap5430-timer";
710 reg = <0x48034000 0x80>;
711 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
712 ti,hwmods = "timer3";
713 };
714
715 timer4: timer@48036000 {
716 compatible = "ti,omap5430-timer";
717 reg = <0x48036000 0x80>;
718 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
719 ti,hwmods = "timer4";
720 };
721
722 timer5: timer@48820000 {
723 compatible = "ti,omap5430-timer";
724 reg = <0x48820000 0x80>;
725 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
726 ti,hwmods = "timer5";
727 };
728
729 timer6: timer@48822000 {
730 compatible = "ti,omap5430-timer";
731 reg = <0x48822000 0x80>;
732 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
733 ti,hwmods = "timer6";
734 };
735
736 timer7: timer@48824000 {
737 compatible = "ti,omap5430-timer";
738 reg = <0x48824000 0x80>;
739 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
740 ti,hwmods = "timer7";
741 };
742
743 timer8: timer@48826000 {
744 compatible = "ti,omap5430-timer";
745 reg = <0x48826000 0x80>;
746 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
747 ti,hwmods = "timer8";
748 };
749
750 timer9: timer@4803e000 {
751 compatible = "ti,omap5430-timer";
752 reg = <0x4803e000 0x80>;
753 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
754 ti,hwmods = "timer9";
755 };
756
757 timer10: timer@48086000 {
758 compatible = "ti,omap5430-timer";
759 reg = <0x48086000 0x80>;
760 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
761 ti,hwmods = "timer10";
762 };
763
764 timer11: timer@48088000 {
765 compatible = "ti,omap5430-timer";
766 reg = <0x48088000 0x80>;
767 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
768 ti,hwmods = "timer11";
769 };
770
771 timer13: timer@48828000 {
772 compatible = "ti,omap5430-timer";
773 reg = <0x48828000 0x80>;
774 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
775 ti,hwmods = "timer13";
776 status = "disabled";
777 };
778
779 timer14: timer@4882a000 {
780 compatible = "ti,omap5430-timer";
781 reg = <0x4882a000 0x80>;
782 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
783 ti,hwmods = "timer14";
784 status = "disabled";
785 };
786
787 timer15: timer@4882c000 {
788 compatible = "ti,omap5430-timer";
789 reg = <0x4882c000 0x80>;
790 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
791 ti,hwmods = "timer15";
792 status = "disabled";
793 };
794
795 timer16: timer@4882e000 {
796 compatible = "ti,omap5430-timer";
797 reg = <0x4882e000 0x80>;
798 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
799 ti,hwmods = "timer16";
800 status = "disabled";
801 };
802
803 wdt2: wdt@4ae14000 {
804 compatible = "ti,omap3-wdt";
805 reg = <0x4ae14000 0x80>;
806 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
807 ti,hwmods = "wd_timer2";
808 };
809
810 hwspinlock: spinlock@4a0f6000 {
811 compatible = "ti,omap4-hwspinlock";
812 reg = <0x4a0f6000 0x1000>;
813 ti,hwmods = "spinlock";
814 #hwlock-cells = <1>;
815 };
816
817 dmm@4e000000 {
818 compatible = "ti,omap5-dmm";
819 reg = <0x4e000000 0x800>;
820 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
821 ti,hwmods = "dmm";
822 };
823
824 i2c1: i2c@48070000 {
825 compatible = "ti,omap4-i2c";
826 reg = <0x48070000 0x100>;
827 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
828 #address-cells = <1>;
829 #size-cells = <0>;
830 ti,hwmods = "i2c1";
831 status = "disabled";
832 };
833
834 i2c2: i2c@48072000 {
835 compatible = "ti,omap4-i2c";
836 reg = <0x48072000 0x100>;
837 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
838 #address-cells = <1>;
839 #size-cells = <0>;
840 ti,hwmods = "i2c2";
841 status = "disabled";
842 };
843
844 i2c3: i2c@48060000 {
845 compatible = "ti,omap4-i2c";
846 reg = <0x48060000 0x100>;
847 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
848 #address-cells = <1>;
849 #size-cells = <0>;
850 ti,hwmods = "i2c3";
851 status = "disabled";
852 };
853
854 i2c4: i2c@4807a000 {
855 compatible = "ti,omap4-i2c";
856 reg = <0x4807a000 0x100>;
857 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
858 #address-cells = <1>;
859 #size-cells = <0>;
860 ti,hwmods = "i2c4";
861 status = "disabled";
862 };
863
864 i2c5: i2c@4807c000 {
865 compatible = "ti,omap4-i2c";
866 reg = <0x4807c000 0x100>;
867 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
868 #address-cells = <1>;
869 #size-cells = <0>;
870 ti,hwmods = "i2c5";
871 status = "disabled";
872 };
873
874 mmc1: mmc@4809c000 {
875 compatible = "ti,omap4-hsmmc";
876 reg = <0x4809c000 0x400>;
877 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
878 ti,hwmods = "mmc1";
879 ti,dual-volt;
880 ti,needs-special-reset;
881 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
882 dma-names = "tx", "rx";
883 status = "disabled";
884 pbias-supply = <&pbias_mmc_reg>;
885 };
886
887 mmc2: mmc@480b4000 {
888 compatible = "ti,omap4-hsmmc";
889 reg = <0x480b4000 0x400>;
890 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
891 ti,hwmods = "mmc2";
892 ti,needs-special-reset;
893 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
894 dma-names = "tx", "rx";
895 status = "disabled";
896 };
897
898 mmc3: mmc@480ad000 {
899 compatible = "ti,omap4-hsmmc";
900 reg = <0x480ad000 0x400>;
901 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
902 ti,hwmods = "mmc3";
903 ti,needs-special-reset;
904 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
905 dma-names = "tx", "rx";
906 status = "disabled";
907 };
908
909 mmc4: mmc@480d1000 {
910 compatible = "ti,omap4-hsmmc";
911 reg = <0x480d1000 0x400>;
912 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
913 ti,hwmods = "mmc4";
914 ti,needs-special-reset;
915 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
916 dma-names = "tx", "rx";
917 status = "disabled";
918 };
919
920 mmu0_dsp1: mmu@40d01000 {
921 compatible = "ti,dra7-dsp-iommu";
922 reg = <0x40d01000 0x100>;
923 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
924 ti,hwmods = "mmu0_dsp1";
925 #iommu-cells = <0>;
926 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
927 status = "disabled";
928 };
929
930 mmu1_dsp1: mmu@40d02000 {
931 compatible = "ti,dra7-dsp-iommu";
932 reg = <0x40d02000 0x100>;
933 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
934 ti,hwmods = "mmu1_dsp1";
935 #iommu-cells = <0>;
936 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
937 status = "disabled";
938 };
939
940 mmu_ipu1: mmu@58882000 {
941 compatible = "ti,dra7-iommu";
942 reg = <0x58882000 0x100>;
943 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
944 ti,hwmods = "mmu_ipu1";
945 #iommu-cells = <0>;
946 ti,iommu-bus-err-back;
947 status = "disabled";
948 };
949
950 mmu_ipu2: mmu@55082000 {
951 compatible = "ti,dra7-iommu";
952 reg = <0x55082000 0x100>;
953 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
954 ti,hwmods = "mmu_ipu2";
955 #iommu-cells = <0>;
956 ti,iommu-bus-err-back;
957 status = "disabled";
958 };
959
960 abb_mpu: regulator-abb-mpu {
961 compatible = "ti,abb-v3";
962 regulator-name = "abb_mpu";
963 #address-cells = <0>;
964 #size-cells = <0>;
965 clocks = <&sys_clkin1>;
966 ti,settling-time = <50>;
967 ti,clock-cycles = <16>;
968
969 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
970 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
971 <0x4ae0c158 0x4>;
972 reg-names = "setup-address", "control-address",
973 "int-address", "efuse-address",
974 "ldo-address";
975 ti,tranxdone-status-mask = <0x80>;
976 /* LDOVBBMPU_FBB_MUX_CTRL */
977 ti,ldovbb-override-mask = <0x400>;
978 /* LDOVBBMPU_FBB_VSET_OUT */
979 ti,ldovbb-vset-mask = <0x1F>;
980
981 /*
982 * NOTE: only FBB mode used but actual vset will
983 * determine final biasing
984 */
985 ti,abb_info = <
986 /*uV ABB efuse rbb_m fbb_m vset_m*/
987 1060000 0 0x0 0 0x02000000 0x01F00000
988 1160000 0 0x4 0 0x02000000 0x01F00000
989 1210000 0 0x8 0 0x02000000 0x01F00000
990 >;
991 };
992
993 abb_ivahd: regulator-abb-ivahd {
994 compatible = "ti,abb-v3";
995 regulator-name = "abb_ivahd";
996 #address-cells = <0>;
997 #size-cells = <0>;
998 clocks = <&sys_clkin1>;
999 ti,settling-time = <50>;
1000 ti,clock-cycles = <16>;
1001
1002 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1003 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1004 <0x4a002470 0x4>;
1005 reg-names = "setup-address", "control-address",
1006 "int-address", "efuse-address",
1007 "ldo-address";
1008 ti,tranxdone-status-mask = <0x40000000>;
1009 /* LDOVBBIVA_FBB_MUX_CTRL */
1010 ti,ldovbb-override-mask = <0x400>;
1011 /* LDOVBBIVA_FBB_VSET_OUT */
1012 ti,ldovbb-vset-mask = <0x1F>;
1013
1014 /*
1015 * NOTE: only FBB mode used but actual vset will
1016 * determine final biasing
1017 */
1018 ti,abb_info = <
1019 /*uV ABB efuse rbb_m fbb_m vset_m*/
1020 1055000 0 0x0 0 0x02000000 0x01F00000
1021 1150000 0 0x4 0 0x02000000 0x01F00000
1022 1250000 0 0x8 0 0x02000000 0x01F00000
1023 >;
1024 };
1025
1026 abb_dspeve: regulator-abb-dspeve {
1027 compatible = "ti,abb-v3";
1028 regulator-name = "abb_dspeve";
1029 #address-cells = <0>;
1030 #size-cells = <0>;
1031 clocks = <&sys_clkin1>;
1032 ti,settling-time = <50>;
1033 ti,clock-cycles = <16>;
1034
1035 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1036 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1037 <0x4a00246c 0x4>;
1038 reg-names = "setup-address", "control-address",
1039 "int-address", "efuse-address",
1040 "ldo-address";
1041 ti,tranxdone-status-mask = <0x20000000>;
1042 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1043 ti,ldovbb-override-mask = <0x400>;
1044 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1045 ti,ldovbb-vset-mask = <0x1F>;
1046
1047 /*
1048 * NOTE: only FBB mode used but actual vset will
1049 * determine final biasing
1050 */
1051 ti,abb_info = <
1052 /*uV ABB efuse rbb_m fbb_m vset_m*/
1053 1055000 0 0x0 0 0x02000000 0x01F00000
1054 1150000 0 0x4 0 0x02000000 0x01F00000
1055 1250000 0 0x8 0 0x02000000 0x01F00000
1056 >;
1057 };
1058
1059 abb_gpu: regulator-abb-gpu {
1060 compatible = "ti,abb-v3";
1061 regulator-name = "abb_gpu";
1062 #address-cells = <0>;
1063 #size-cells = <0>;
1064 clocks = <&sys_clkin1>;
1065 ti,settling-time = <50>;
1066 ti,clock-cycles = <16>;
1067
1068 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1069 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1070 <0x4ae0c154 0x4>;
1071 reg-names = "setup-address", "control-address",
1072 "int-address", "efuse-address",
1073 "ldo-address";
1074 ti,tranxdone-status-mask = <0x10000000>;
1075 /* LDOVBBGPU_FBB_MUX_CTRL */
1076 ti,ldovbb-override-mask = <0x400>;
1077 /* LDOVBBGPU_FBB_VSET_OUT */
1078 ti,ldovbb-vset-mask = <0x1F>;
1079
1080 /*
1081 * NOTE: only FBB mode used but actual vset will
1082 * determine final biasing
1083 */
1084 ti,abb_info = <
1085 /*uV ABB efuse rbb_m fbb_m vset_m*/
1086 1090000 0 0x0 0 0x02000000 0x01F00000
1087 1210000 0 0x4 0 0x02000000 0x01F00000
1088 1280000 0 0x8 0 0x02000000 0x01F00000
1089 >;
1090 };
1091
1092 mcspi1: spi@48098000 {
1093 compatible = "ti,omap4-mcspi";
1094 reg = <0x48098000 0x200>;
1095 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1096 #address-cells = <1>;
1097 #size-cells = <0>;
1098 ti,hwmods = "mcspi1";
1099 ti,spi-num-cs = <4>;
1100 dmas = <&sdma_xbar 35>,
1101 <&sdma_xbar 36>,
1102 <&sdma_xbar 37>,
1103 <&sdma_xbar 38>,
1104 <&sdma_xbar 39>,
1105 <&sdma_xbar 40>,
1106 <&sdma_xbar 41>,
1107 <&sdma_xbar 42>;
1108 dma-names = "tx0", "rx0", "tx1", "rx1",
1109 "tx2", "rx2", "tx3", "rx3";
1110 status = "disabled";
1111 };
1112
1113 mcspi2: spi@4809a000 {
1114 compatible = "ti,omap4-mcspi";
1115 reg = <0x4809a000 0x200>;
1116 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 ti,hwmods = "mcspi2";
1120 ti,spi-num-cs = <2>;
1121 dmas = <&sdma_xbar 43>,
1122 <&sdma_xbar 44>,
1123 <&sdma_xbar 45>,
1124 <&sdma_xbar 46>;
1125 dma-names = "tx0", "rx0", "tx1", "rx1";
1126 status = "disabled";
1127 };
1128
1129 mcspi3: spi@480b8000 {
1130 compatible = "ti,omap4-mcspi";
1131 reg = <0x480b8000 0x200>;
1132 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1135 ti,hwmods = "mcspi3";
1136 ti,spi-num-cs = <2>;
1137 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1138 dma-names = "tx0", "rx0";
1139 status = "disabled";
1140 };
1141
1142 mcspi4: spi@480ba000 {
1143 compatible = "ti,omap4-mcspi";
1144 reg = <0x480ba000 0x200>;
1145 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1146 #address-cells = <1>;
1147 #size-cells = <0>;
1148 ti,hwmods = "mcspi4";
1149 ti,spi-num-cs = <1>;
1150 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1151 dma-names = "tx0", "rx0";
1152 status = "disabled";
1153 };
1154
1155 qspi: qspi@4b300000 {
1156 compatible = "ti,dra7xxx-qspi";
1157 reg = <0x4b300000 0x100>,
1158 <0x5c000000 0x4000000>;
1159 reg-names = "qspi_base", "qspi_mmap";
1160 syscon-chipselects = <&scm_conf 0x558>;
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1163 ti,hwmods = "qspi";
1164 clocks = <&qspi_gfclk_div>;
1165 clock-names = "fck";
1166 num-cs = <4>;
1167 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1168 status = "disabled";
1169 };
1170
1171 omap_control_sata: control-phy@4a002374 {
1172 compatible = "ti,control-phy-pipe3";
1173 reg = <0x4a002374 0x4>;
1174 reg-names = "power";
1175 clocks = <&sys_clkin1>;
1176 clock-names = "sysclk";
1177 };
1178
1179 /* OCP2SCP3 */
1180 ocp2scp@4a090000 {
1181 compatible = "ti,omap-ocp2scp";
1182 #address-cells = <1>;
1183 #size-cells = <1>;
1184 ranges;
1185 reg = <0x4a090000 0x20>;
1186 ti,hwmods = "ocp2scp3";
1187 sata_phy: phy@4A096000 {
1188 compatible = "ti,phy-pipe3-sata";
1189 reg = <0x4A096000 0x80>, /* phy_rx */
1190 <0x4A096400 0x64>, /* phy_tx */
1191 <0x4A096800 0x40>; /* pll_ctrl */
1192 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1193 ctrl-module = <&omap_control_sata>;
1194 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1195 clock-names = "sysclk", "refclk";
1196 syscon-pllreset = <&scm_conf 0x3fc>;
1197 #phy-cells = <0>;
1198 };
1199
1200 pcie1_phy: pciephy@4a094000 {
1201 compatible = "ti,phy-pipe3-pcie";
1202 reg = <0x4a094000 0x80>, /* phy_rx */
1203 <0x4a094400 0x64>; /* phy_tx */
1204 reg-names = "phy_rx", "phy_tx";
1205 ctrl-module = <&omap_control_pcie1phy>;
1206 clocks = <&dpll_pcie_ref_ck>,
1207 <&dpll_pcie_ref_m2ldo_ck>,
1208 <&optfclk_pciephy1_32khz>,
1209 <&optfclk_pciephy1_clk>,
1210 <&optfclk_pciephy1_div_clk>,
1211 <&optfclk_pciephy_div>;
1212 clock-names = "dpll_ref", "dpll_ref_m2",
1213 "wkupclk", "refclk",
1214 "div-clk", "phy-div";
1215 #phy-cells = <0>;
1216 };
1217
1218 pcie2_phy: pciephy@4a095000 {
1219 compatible = "ti,phy-pipe3-pcie";
1220 reg = <0x4a095000 0x80>, /* phy_rx */
1221 <0x4a095400 0x64>; /* phy_tx */
1222 reg-names = "phy_rx", "phy_tx";
1223 ctrl-module = <&omap_control_pcie2phy>;
1224 clocks = <&dpll_pcie_ref_ck>,
1225 <&dpll_pcie_ref_m2ldo_ck>,
1226 <&optfclk_pciephy2_32khz>,
1227 <&optfclk_pciephy2_clk>,
1228 <&optfclk_pciephy2_div_clk>,
1229 <&optfclk_pciephy_div>;
1230 clock-names = "dpll_ref", "dpll_ref_m2",
1231 "wkupclk", "refclk",
1232 "div-clk", "phy-div";
1233 #phy-cells = <0>;
1234 status = "disabled";
1235 };
1236 };
1237
1238 sata: sata@4a141100 {
1239 compatible = "snps,dwc-ahci";
1240 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1241 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1242 phys = <&sata_phy>;
1243 phy-names = "sata-phy";
1244 clocks = <&sata_ref_clk>;
1245 ti,hwmods = "sata";
1246 };
1247
1248 omap_control_pcie1phy: control-phy@0x4a003c40 {
1249 compatible = "ti,control-phy-pcie";
1250 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1251 reg-names = "power", "control_sma", "pcie_pcs";
1252 clocks = <&sys_clkin1>;
1253 clock-names = "sysclk";
1254 };
1255
1256 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1257 compatible = "ti,control-phy-pcie";
1258 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1259 reg-names = "power", "control_sma", "pcie_pcs";
1260 clocks = <&sys_clkin1>;
1261 clock-names = "sysclk";
1262 status = "disabled";
1263 };
1264
1265 rtc: rtc@48838000 {
1266 compatible = "ti,am3352-rtc";
1267 reg = <0x48838000 0x100>;
1268 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1270 ti,hwmods = "rtcss";
1271 clocks = <&sys_32k_ck>;
1272 };
1273
1274 omap_control_usb2phy1: control-phy@4a002300 {
1275 compatible = "ti,control-phy-usb2";
1276 reg = <0x4a002300 0x4>;
1277 reg-names = "power";
1278 };
1279
1280 omap_control_usb3phy1: control-phy@4a002370 {
1281 compatible = "ti,control-phy-pipe3";
1282 reg = <0x4a002370 0x4>;
1283 reg-names = "power";
1284 };
1285
1286 omap_control_usb2phy2: control-phy@0x4a002e74 {
1287 compatible = "ti,control-phy-usb2-dra7";
1288 reg = <0x4a002e74 0x4>;
1289 reg-names = "power";
1290 };
1291
1292 /* OCP2SCP1 */
1293 ocp2scp@4a080000 {
1294 compatible = "ti,omap-ocp2scp";
1295 #address-cells = <1>;
1296 #size-cells = <1>;
1297 ranges;
1298 reg = <0x4a080000 0x20>;
1299 ti,hwmods = "ocp2scp1";
1300
1301 usb2_phy1: phy@4a084000 {
1302 compatible = "ti,omap-usb2";
1303 reg = <0x4a084000 0x400>;
1304 ctrl-module = <&omap_control_usb2phy1>;
1305 clocks = <&usb_phy1_always_on_clk32k>,
1306 <&usb_otg_ss1_refclk960m>;
1307 clock-names = "wkupclk",
1308 "refclk";
1309 #phy-cells = <0>;
1310 };
1311
1312 usb2_phy2: phy@4a085000 {
1313 compatible = "ti,omap-usb2";
1314 reg = <0x4a085000 0x400>;
1315 ctrl-module = <&omap_control_usb2phy2>;
1316 clocks = <&usb_phy2_always_on_clk32k>,
1317 <&usb_otg_ss2_refclk960m>;
1318 clock-names = "wkupclk",
1319 "refclk";
1320 #phy-cells = <0>;
1321 };
1322
1323 usb3_phy1: phy@4a084400 {
1324 compatible = "ti,omap-usb3";
1325 reg = <0x4a084400 0x80>,
1326 <0x4a084800 0x64>,
1327 <0x4a084c00 0x40>;
1328 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1329 ctrl-module = <&omap_control_usb3phy1>;
1330 clocks = <&usb_phy3_always_on_clk32k>,
1331 <&sys_clkin1>,
1332 <&usb_otg_ss1_refclk960m>;
1333 clock-names = "wkupclk",
1334 "sysclk",
1335 "refclk";
1336 #phy-cells = <0>;
1337 };
1338 };
1339
1340 omap_dwc3_1: omap_dwc3_1@48880000 {
1341 compatible = "ti,dwc3";
1342 ti,hwmods = "usb_otg_ss1";
1343 reg = <0x48880000 0x10000>;
1344 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1345 #address-cells = <1>;
1346 #size-cells = <1>;
1347 utmi-mode = <2>;
1348 ranges;
1349 usb1: usb@48890000 {
1350 compatible = "snps,dwc3";
1351 reg = <0x48890000 0x17000>;
1352 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1355 interrupt-names = "peripheral",
1356 "host",
1357 "otg";
1358 phys = <&usb2_phy1>, <&usb3_phy1>;
1359 phy-names = "usb2-phy", "usb3-phy";
1360 tx-fifo-resize;
1361 maximum-speed = "super-speed";
1362 dr_mode = "otg";
1363 snps,dis_u3_susphy_quirk;
1364 snps,dis_u2_susphy_quirk;
1365 };
1366 };
1367
1368 omap_dwc3_2: omap_dwc3_2@488c0000 {
1369 compatible = "ti,dwc3";
1370 ti,hwmods = "usb_otg_ss2";
1371 reg = <0x488c0000 0x10000>;
1372 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1373 #address-cells = <1>;
1374 #size-cells = <1>;
1375 utmi-mode = <2>;
1376 ranges;
1377 usb2: usb@488d0000 {
1378 compatible = "snps,dwc3";
1379 reg = <0x488d0000 0x17000>;
1380 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1383 interrupt-names = "peripheral",
1384 "host",
1385 "otg";
1386 phys = <&usb2_phy2>;
1387 phy-names = "usb2-phy";
1388 tx-fifo-resize;
1389 maximum-speed = "high-speed";
1390 dr_mode = "otg";
1391 snps,dis_u3_susphy_quirk;
1392 snps,dis_u2_susphy_quirk;
1393 };
1394 };
1395
1396 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1397 omap_dwc3_3: omap_dwc3_3@48900000 {
1398 compatible = "ti,dwc3";
1399 ti,hwmods = "usb_otg_ss3";
1400 reg = <0x48900000 0x10000>;
1401 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1402 #address-cells = <1>;
1403 #size-cells = <1>;
1404 utmi-mode = <2>;
1405 ranges;
1406 status = "disabled";
1407 usb3: usb@48910000 {
1408 compatible = "snps,dwc3";
1409 reg = <0x48910000 0x17000>;
1410 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1413 interrupt-names = "peripheral",
1414 "host",
1415 "otg";
1416 tx-fifo-resize;
1417 maximum-speed = "high-speed";
1418 dr_mode = "otg";
1419 snps,dis_u3_susphy_quirk;
1420 snps,dis_u2_susphy_quirk;
1421 };
1422 };
1423
1424 elm: elm@48078000 {
1425 compatible = "ti,am3352-elm";
1426 reg = <0x48078000 0xfc0>; /* device IO registers */
1427 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1428 ti,hwmods = "elm";
1429 status = "disabled";
1430 };
1431
1432 gpmc: gpmc@50000000 {
1433 compatible = "ti,am3352-gpmc";
1434 ti,hwmods = "gpmc";
1435 reg = <0x50000000 0x37c>; /* device IO registers */
1436 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1437 gpmc,num-cs = <8>;
1438 gpmc,num-waitpins = <2>;
1439 #address-cells = <2>;
1440 #size-cells = <1>;
1441 status = "disabled";
1442 };
1443
1444 atl: atl@4843c000 {
1445 compatible = "ti,dra7-atl";
1446 reg = <0x4843c000 0x3ff>;
1447 ti,hwmods = "atl";
1448 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1449 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1450 clocks = <&atl_gfclk_mux>;
1451 clock-names = "fck";
1452 status = "disabled";
1453 };
1454
1455 mcasp3: mcasp@48468000 {
1456 compatible = "ti,dra7-mcasp-audio";
1457 ti,hwmods = "mcasp3";
1458 reg = <0x48468000 0x2000>;
1459 reg-names = "mpu";
1460 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1462 interrupt-names = "tx", "rx";
1463 dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
1464 dma-names = "tx", "rx";
1465 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1466 clock-names = "fck", "ahclkx";
1467 status = "disabled";
1468 };
1469
1470 crossbar_mpu: crossbar@4a002a48 {
1471 compatible = "ti,irq-crossbar";
1472 reg = <0x4a002a48 0x130>;
1473 interrupt-controller;
1474 interrupt-parent = <&wakeupgen>;
1475 #interrupt-cells = <3>;
1476 ti,max-irqs = <160>;
1477 ti,max-crossbar-sources = <MAX_SOURCES>;
1478 ti,reg-size = <2>;
1479 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1480 ti,irqs-skip = <10 133 139 140>;
1481 ti,irqs-safe-map = <0>;
1482 };
1483
1484 mac: ethernet@48484000 {
1485 compatible = "ti,dra7-cpsw","ti,cpsw";
1486 ti,hwmods = "gmac";
1487 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1488 clock-names = "fck", "cpts";
1489 cpdma_channels = <8>;
1490 ale_entries = <1024>;
1491 bd_ram_size = <0x2000>;
1492 no_bd_ram = <0>;
1493 rx_descs = <64>;
1494 mac_control = <0x20>;
1495 slaves = <2>;
1496 active_slave = <0>;
1497 cpts_clock_mult = <0x80000000>;
1498 cpts_clock_shift = <29>;
1499 reg = <0x48484000 0x1000
1500 0x48485200 0x2E00>;
1501 #address-cells = <1>;
1502 #size-cells = <1>;
1503
1504 /*
1505 * Do not allow gating of cpsw clock as workaround
1506 * for errata i877. Keeping internal clock disabled
1507 * causes the device switching characteristics
1508 * to degrade over time and eventually fail to meet
1509 * the data manual delay time/skew specs.
1510 */
1511 ti,no-idle;
1512
1513 /*
1514 * rx_thresh_pend
1515 * rx_pend
1516 * tx_pend
1517 * misc_pend
1518 */
1519 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1522 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1523 ranges;
1524 syscon = <&scm_conf>;
1525 status = "disabled";
1526
1527 davinci_mdio: mdio@48485000 {
1528 compatible = "ti,davinci_mdio";
1529 #address-cells = <1>;
1530 #size-cells = <0>;
1531 ti,hwmods = "davinci_mdio";
1532 bus_freq = <1000000>;
1533 reg = <0x48485000 0x100>;
1534 };
1535
1536 cpsw_emac0: slave@48480200 {
1537 /* Filled in by U-Boot */
1538 mac-address = [ 00 00 00 00 00 00 ];
1539 };
1540
1541 cpsw_emac1: slave@48480300 {
1542 /* Filled in by U-Boot */
1543 mac-address = [ 00 00 00 00 00 00 ];
1544 };
1545
1546 phy_sel: cpsw-phy-sel@4a002554 {
1547 compatible = "ti,dra7xx-cpsw-phy-sel";
1548 reg= <0x4a002554 0x4>;
1549 reg-names = "gmii-sel";
1550 };
1551 };
1552
1553 dcan1: can@481cc000 {
1554 compatible = "ti,dra7-d_can";
1555 ti,hwmods = "dcan1";
1556 reg = <0x4ae3c000 0x2000>;
1557 syscon-raminit = <&scm_conf 0x558 0>;
1558 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1559 clocks = <&dcan1_sys_clk_mux>;
1560 status = "disabled";
1561 };
1562
1563 dcan2: can@481d0000 {
1564 compatible = "ti,dra7-d_can";
1565 ti,hwmods = "dcan2";
1566 reg = <0x48480000 0x2000>;
1567 syscon-raminit = <&scm_conf 0x558 1>;
1568 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1569 clocks = <&sys_clkin1>;
1570 status = "disabled";
1571 };
1572
1573 dss: dss@58000000 {
1574 compatible = "ti,dra7-dss";
1575 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1576 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1577 status = "disabled";
1578 ti,hwmods = "dss_core";
1579 /* CTRL_CORE_DSS_PLL_CONTROL */
1580 syscon-pll-ctrl = <&scm_conf 0x538>;
1581 #address-cells = <1>;
1582 #size-cells = <1>;
1583 ranges;
1584
1585 dispc@58001000 {
1586 compatible = "ti,dra7-dispc";
1587 reg = <0x58001000 0x1000>;
1588 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1589 ti,hwmods = "dss_dispc";
1590 clocks = <&dss_dss_clk>;
1591 clock-names = "fck";
1592 /* CTRL_CORE_SMA_SW_1 */
1593 syscon-pol = <&scm_conf 0x534>;
1594 };
1595
1596 hdmi: encoder@58060000 {
1597 compatible = "ti,dra7-hdmi";
1598 reg = <0x58040000 0x200>,
1599 <0x58040200 0x80>,
1600 <0x58040300 0x80>,
1601 <0x58060000 0x19000>;
1602 reg-names = "wp", "pll", "phy", "core";
1603 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1604 status = "disabled";
1605 ti,hwmods = "dss_hdmi";
1606 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1607 clock-names = "fck", "sys_clk";
1608 };
1609 };
1610 };
1611
1612 thermal_zones: thermal-zones {
1613 #include "omap4-cpu-thermal.dtsi"
1614 #include "omap5-gpu-thermal.dtsi"
1615 #include "omap5-core-thermal.dtsi"
1616 };
1617
1618 };
1619
1620 &cpu_thermal {
1621 polling-delay = <500>; /* milliseconds */
1622 };
1623
1624 /include/ "dra7xx-clocks.dtsi"
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