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[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / exynos3250.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos3250 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file.
15 */
16
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
21
22 / {
23 compatible = "samsung,exynos3250";
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 mshc0 = &mshc_0;
32 mshc1 = &mshc_1;
33 mshc2 = &mshc_2;
34 spi0 = &spi_0;
35 spi1 = &spi_1;
36 i2c0 = &i2c_0;
37 i2c1 = &i2c_1;
38 i2c2 = &i2c_2;
39 i2c3 = &i2c_3;
40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
44 serial0 = &serial_0;
45 serial1 = &serial_1;
46 serial2 = &serial_2;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 reg = <0>;
57 clock-frequency = <1000000000>;
58 clocks = <&cmu CLK_ARM_CLK>;
59 clock-names = "cpu";
60 #cooling-cells = <2>;
61
62 operating-points = <
63 1000000 1150000
64 900000 1112500
65 800000 1075000
66 700000 1037500
67 600000 1000000
68 500000 962500
69 400000 925000
70 300000 887500
71 200000 850000
72 100000 850000
73 >;
74 };
75
76 cpu1: cpu@1 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a7";
79 reg = <1>;
80 clock-frequency = <1000000000>;
81 clocks = <&cmu CLK_ARM_CLK>;
82 clock-names = "cpu";
83 #cooling-cells = <2>;
84
85 operating-points = <
86 1000000 1150000
87 900000 1112500
88 800000 1075000
89 700000 1037500
90 600000 1000000
91 500000 962500
92 400000 925000
93 300000 887500
94 200000 850000
95 100000 850000
96 >;
97 };
98 };
99
100 fixed-rate-clocks {
101 #address-cells = <1>;
102 #size-cells = <0>;
103
104 xusbxti: clock@0 {
105 compatible = "fixed-clock";
106 reg = <0>;
107 clock-frequency = <0>;
108 #clock-cells = <0>;
109 clock-output-names = "xusbxti";
110 };
111
112 xxti: clock@1 {
113 compatible = "fixed-clock";
114 reg = <1>;
115 clock-frequency = <0>;
116 #clock-cells = <0>;
117 clock-output-names = "xxti";
118 };
119
120 xtcxo: clock@2 {
121 compatible = "fixed-clock";
122 reg = <2>;
123 clock-frequency = <0>;
124 #clock-cells = <0>;
125 clock-output-names = "xtcxo";
126 };
127 };
128
129 pmu {
130 compatible = "arm,cortex-a7-pmu";
131 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
133 };
134
135 soc: soc {
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges;
140
141 sysram@2020000 {
142 compatible = "mmio-sram";
143 reg = <0x02020000 0x40000>;
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0 0x02020000 0x40000>;
147
148 smp-sysram@0 {
149 compatible = "samsung,exynos4210-sysram";
150 reg = <0x0 0x1000>;
151 };
152
153 smp-sysram@3f000 {
154 compatible = "samsung,exynos4210-sysram-ns";
155 reg = <0x3f000 0x1000>;
156 };
157 };
158
159 chipid@10000000 {
160 compatible = "samsung,exynos4210-chipid";
161 reg = <0x10000000 0x100>;
162 };
163
164 sys_reg: syscon@10010000 {
165 compatible = "samsung,exynos3-sysreg", "syscon";
166 reg = <0x10010000 0x400>;
167 };
168
169 pmu_system_controller: system-controller@10020000 {
170 compatible = "samsung,exynos3250-pmu", "syscon";
171 reg = <0x10020000 0x4000>;
172 interrupt-controller;
173 #interrupt-cells = <3>;
174 interrupt-parent = <&gic>;
175 clock-names = "clkout8";
176 clocks = <&cmu CLK_FIN_PLL>;
177 #clock-cells = <1>;
178 };
179
180 mipi_phy: video-phy {
181 compatible = "samsung,s5pv210-mipi-video-phy";
182 #phy-cells = <1>;
183 syscon = <&pmu_system_controller>;
184 };
185
186 pd_cam: power-domain@10023c00 {
187 compatible = "samsung,exynos4210-pd";
188 reg = <0x10023C00 0x20>;
189 #power-domain-cells = <0>;
190 label = "CAM";
191 };
192
193 pd_mfc: power-domain@10023c40 {
194 compatible = "samsung,exynos4210-pd";
195 reg = <0x10023C40 0x20>;
196 #power-domain-cells = <0>;
197 label = "MFC";
198 };
199
200 pd_g3d: power-domain@10023c60 {
201 compatible = "samsung,exynos4210-pd";
202 reg = <0x10023C60 0x20>;
203 #power-domain-cells = <0>;
204 label = "G3D";
205 };
206
207 pd_lcd0: power-domain@10023c80 {
208 compatible = "samsung,exynos4210-pd";
209 reg = <0x10023C80 0x20>;
210 #power-domain-cells = <0>;
211 label = "LCD0";
212 };
213
214 pd_isp: power-domain@10023ca0 {
215 compatible = "samsung,exynos4210-pd";
216 reg = <0x10023CA0 0x20>;
217 #power-domain-cells = <0>;
218 label = "ISP";
219 };
220
221 cmu: clock-controller@10030000 {
222 compatible = "samsung,exynos3250-cmu";
223 reg = <0x10030000 0x20000>;
224 #clock-cells = <1>;
225 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
226 <&cmu CLK_MOUT_ACLK_266_SUB>;
227 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
228 <&cmu CLK_FIN_PLL>;
229 };
230
231 cmu_dmc: clock-controller@105c0000 {
232 compatible = "samsung,exynos3250-cmu-dmc";
233 reg = <0x105C0000 0x2000>;
234 #clock-cells = <1>;
235 };
236
237 rtc: rtc@10070000 {
238 compatible = "samsung,s3c6410-rtc";
239 reg = <0x10070000 0x100>;
240 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-parent = <&pmu_system_controller>;
243 status = "disabled";
244 };
245
246 tmu: tmu@100c0000 {
247 compatible = "samsung,exynos3250-tmu";
248 reg = <0x100C0000 0x100>;
249 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cmu CLK_TMU_APBIF>;
251 clock-names = "tmu_apbif";
252 #thermal-sensor-cells = <0>;
253 status = "disabled";
254 };
255
256 gic: interrupt-controller@10481000 {
257 compatible = "arm,cortex-a15-gic";
258 #interrupt-cells = <3>;
259 interrupt-controller;
260 reg = <0x10481000 0x1000>,
261 <0x10482000 0x2000>,
262 <0x10484000 0x2000>,
263 <0x10486000 0x2000>;
264 interrupts = <GIC_PPI 9
265 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
266 };
267
268 mct@10050000 {
269 compatible = "samsung,exynos4210-mct";
270 reg = <0x10050000 0x800>;
271 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
280 clock-names = "fin_pll", "mct";
281 };
282
283 pinctrl_1: pinctrl@11000000 {
284 compatible = "samsung,exynos3250-pinctrl";
285 reg = <0x11000000 0x1000>;
286 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
287
288 wakeup-interrupt-controller {
289 compatible = "samsung,exynos4210-wakeup-eint";
290 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
291 };
292 };
293
294 pinctrl_0: pinctrl@11400000 {
295 compatible = "samsung,exynos3250-pinctrl";
296 reg = <0x11400000 0x1000>;
297 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
298 };
299
300 jpeg: codec@11830000 {
301 compatible = "samsung,exynos3250-jpeg";
302 reg = <0x11830000 0x1000>;
303 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
305 clock-names = "jpeg", "sclk";
306 power-domains = <&pd_cam>;
307 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
308 assigned-clock-rates = <0>, <150000000>;
309 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
310 iommus = <&sysmmu_jpeg>;
311 status = "disabled";
312 };
313
314 sysmmu_jpeg: sysmmu@11a60000 {
315 compatible = "samsung,exynos-sysmmu";
316 reg = <0x11a60000 0x1000>;
317 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
319 clock-names = "sysmmu", "master";
320 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
321 power-domains = <&pd_cam>;
322 #iommu-cells = <0>;
323 };
324
325 fimd: fimd@11c00000 {
326 compatible = "samsung,exynos3250-fimd";
327 reg = <0x11c00000 0x30000>;
328 interrupt-names = "fifo", "vsync", "lcd_sys";
329 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
333 clock-names = "sclk_fimd", "fimd";
334 power-domains = <&pd_lcd0>;
335 iommus = <&sysmmu_fimd0>;
336 samsung,sysreg = <&sys_reg>;
337 status = "disabled";
338 };
339
340 dsi_0: dsi@11c80000 {
341 compatible = "samsung,exynos3250-mipi-dsi";
342 reg = <0x11C80000 0x10000>;
343 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
344 samsung,phy-type = <0>;
345 power-domains = <&pd_lcd0>;
346 phys = <&mipi_phy 1>;
347 phy-names = "dsim";
348 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
349 clock-names = "bus_clk", "pll_clk";
350 #address-cells = <1>;
351 #size-cells = <0>;
352 status = "disabled";
353 };
354
355 sysmmu_fimd0: sysmmu@11e20000 {
356 compatible = "samsung,exynos-sysmmu";
357 reg = <0x11e20000 0x1000>;
358 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
360 clock-names = "sysmmu", "master";
361 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
362 power-domains = <&pd_lcd0>;
363 #iommu-cells = <0>;
364 };
365
366 hsotg: hsotg@12480000 {
367 compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
368 reg = <0x12480000 0x20000>;
369 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&cmu CLK_USBOTG>;
371 clock-names = "otg";
372 phys = <&exynos_usbphy 0>;
373 phy-names = "usb2-phy";
374 status = "disabled";
375 };
376
377 mshc_0: mshc@12510000 {
378 compatible = "samsung,exynos5420-dw-mshc";
379 reg = <0x12510000 0x1000>;
380 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
382 clock-names = "biu", "ciu";
383 fifo-depth = <0x80>;
384 #address-cells = <1>;
385 #size-cells = <0>;
386 status = "disabled";
387 };
388
389 mshc_1: mshc@12520000 {
390 compatible = "samsung,exynos5420-dw-mshc";
391 reg = <0x12520000 0x1000>;
392 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
394 clock-names = "biu", "ciu";
395 fifo-depth = <0x80>;
396 #address-cells = <1>;
397 #size-cells = <0>;
398 status = "disabled";
399 };
400
401 mshc_2: mshc@12530000 {
402 compatible = "samsung,exynos5250-dw-mshc";
403 reg = <0x12530000 0x1000>;
404 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
406 clock-names = "biu", "ciu";
407 fifo-depth = <0x80>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 status = "disabled";
411 };
412
413 exynos_usbphy: exynos-usbphy@125b0000 {
414 compatible = "samsung,exynos3250-usb2-phy";
415 reg = <0x125B0000 0x100>;
416 samsung,pmureg-phandle = <&pmu_system_controller>;
417 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
418 clock-names = "phy", "ref";
419 #phy-cells = <1>;
420 status = "disabled";
421 };
422
423 amba {
424 compatible = "simple-bus";
425 #address-cells = <1>;
426 #size-cells = <1>;
427 ranges;
428
429 pdma0: pdma@12680000 {
430 compatible = "arm,pl330", "arm,primecell";
431 reg = <0x12680000 0x1000>;
432 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cmu CLK_PDMA0>;
434 clock-names = "apb_pclk";
435 #dma-cells = <1>;
436 #dma-channels = <8>;
437 #dma-requests = <32>;
438 };
439
440 pdma1: pdma@12690000 {
441 compatible = "arm,pl330", "arm,primecell";
442 reg = <0x12690000 0x1000>;
443 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&cmu CLK_PDMA1>;
445 clock-names = "apb_pclk";
446 #dma-cells = <1>;
447 #dma-channels = <8>;
448 #dma-requests = <32>;
449 };
450 };
451
452 adc: adc@126c0000 {
453 compatible = "samsung,exynos3250-adc",
454 "samsung,exynos-adc-v2";
455 reg = <0x126C0000 0x100>;
456 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
457 clock-names = "adc", "sclk";
458 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
459 #io-channel-cells = <1>;
460 io-channel-ranges;
461 samsung,syscon-phandle = <&pmu_system_controller>;
462 status = "disabled";
463 };
464
465 gpu: gpu@13000000 {
466 compatible = "samsung,exynos4210-mali", "arm,mali-400";
467 reg = <0x13000000 0x10000>;
468 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
479 interrupt-names = "gp",
480 "gpmmu",
481 "pp0",
482 "ppmmu0",
483 "pp1",
484 "ppmmu1",
485 "pp2",
486 "ppmmu2",
487 "pp3",
488 "ppmmu3",
489 "pmu";
490 clocks = <&cmu CLK_G3D>,
491 <&cmu CLK_SCLK_G3D>;
492 clock-names = "bus", "core";
493 power-domains = <&pd_g3d>;
494 status = "disabled";
495 /* TODO: operating points for DVFS, assigned clock as 134 MHz */
496 };
497
498 mfc: codec@13400000 {
499 compatible = "samsung,mfc-v7";
500 reg = <0x13400000 0x10000>;
501 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
502 clock-names = "mfc", "sclk_mfc";
503 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
504 power-domains = <&pd_mfc>;
505 iommus = <&sysmmu_mfc>;
506 };
507
508 sysmmu_mfc: sysmmu@13620000 {
509 compatible = "samsung,exynos-sysmmu";
510 reg = <0x13620000 0x1000>;
511 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
513 clock-names = "sysmmu", "master";
514 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
515 power-domains = <&pd_mfc>;
516 #iommu-cells = <0>;
517 };
518
519 serial_0: serial@13800000 {
520 compatible = "samsung,exynos4210-uart";
521 reg = <0x13800000 0x100>;
522 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
524 clock-names = "uart", "clk_uart_baud0";
525 pinctrl-names = "default";
526 pinctrl-0 = <&uart0_data &uart0_fctl>;
527 status = "disabled";
528 };
529
530 serial_1: serial@13810000 {
531 compatible = "samsung,exynos4210-uart";
532 reg = <0x13810000 0x100>;
533 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
535 clock-names = "uart", "clk_uart_baud0";
536 pinctrl-names = "default";
537 pinctrl-0 = <&uart1_data>;
538 status = "disabled";
539 };
540
541 serial_2: serial@13820000 {
542 compatible = "samsung,exynos4210-uart";
543 reg = <0x13820000 0x100>;
544 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
546 clock-names = "uart", "clk_uart_baud0";
547 pinctrl-names = "default";
548 pinctrl-0 = <&uart2_data>;
549 status = "disabled";
550 };
551
552 i2c_0: i2c@13860000 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 compatible = "samsung,s3c2440-i2c";
556 reg = <0x13860000 0x100>;
557 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cmu CLK_I2C0>;
559 clock-names = "i2c";
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c0_bus>;
562 status = "disabled";
563 };
564
565 i2c_1: i2c@13870000 {
566 #address-cells = <1>;
567 #size-cells = <0>;
568 compatible = "samsung,s3c2440-i2c";
569 reg = <0x13870000 0x100>;
570 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cmu CLK_I2C1>;
572 clock-names = "i2c";
573 pinctrl-names = "default";
574 pinctrl-0 = <&i2c1_bus>;
575 status = "disabled";
576 };
577
578 i2c_2: i2c@13880000 {
579 #address-cells = <1>;
580 #size-cells = <0>;
581 compatible = "samsung,s3c2440-i2c";
582 reg = <0x13880000 0x100>;
583 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cmu CLK_I2C2>;
585 clock-names = "i2c";
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c2_bus>;
588 status = "disabled";
589 };
590
591 i2c_3: i2c@13890000 {
592 #address-cells = <1>;
593 #size-cells = <0>;
594 compatible = "samsung,s3c2440-i2c";
595 reg = <0x13890000 0x100>;
596 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cmu CLK_I2C3>;
598 clock-names = "i2c";
599 pinctrl-names = "default";
600 pinctrl-0 = <&i2c3_bus>;
601 status = "disabled";
602 };
603
604 i2c_4: i2c@138a0000 {
605 #address-cells = <1>;
606 #size-cells = <0>;
607 compatible = "samsung,s3c2440-i2c";
608 reg = <0x138A0000 0x100>;
609 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&cmu CLK_I2C4>;
611 clock-names = "i2c";
612 pinctrl-names = "default";
613 pinctrl-0 = <&i2c4_bus>;
614 status = "disabled";
615 };
616
617 i2c_5: i2c@138b0000 {
618 #address-cells = <1>;
619 #size-cells = <0>;
620 compatible = "samsung,s3c2440-i2c";
621 reg = <0x138B0000 0x100>;
622 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&cmu CLK_I2C5>;
624 clock-names = "i2c";
625 pinctrl-names = "default";
626 pinctrl-0 = <&i2c5_bus>;
627 status = "disabled";
628 };
629
630 i2c_6: i2c@138c0000 {
631 #address-cells = <1>;
632 #size-cells = <0>;
633 compatible = "samsung,s3c2440-i2c";
634 reg = <0x138C0000 0x100>;
635 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&cmu CLK_I2C6>;
637 clock-names = "i2c";
638 pinctrl-names = "default";
639 pinctrl-0 = <&i2c6_bus>;
640 status = "disabled";
641 };
642
643 i2c_7: i2c@138d0000 {
644 #address-cells = <1>;
645 #size-cells = <0>;
646 compatible = "samsung,s3c2440-i2c";
647 reg = <0x138D0000 0x100>;
648 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&cmu CLK_I2C7>;
650 clock-names = "i2c";
651 pinctrl-names = "default";
652 pinctrl-0 = <&i2c7_bus>;
653 status = "disabled";
654 };
655
656 spi_0: spi@13920000 {
657 compatible = "samsung,exynos4210-spi";
658 reg = <0x13920000 0x100>;
659 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
660 dmas = <&pdma0 7>, <&pdma0 6>;
661 dma-names = "tx", "rx";
662 #address-cells = <1>;
663 #size-cells = <0>;
664 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
665 clock-names = "spi", "spi_busclk0";
666 samsung,spi-src-clk = <0>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&spi0_bus>;
669 status = "disabled";
670 };
671
672 spi_1: spi@13930000 {
673 compatible = "samsung,exynos4210-spi";
674 reg = <0x13930000 0x100>;
675 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
676 dmas = <&pdma1 7>, <&pdma1 6>;
677 dma-names = "tx", "rx";
678 #address-cells = <1>;
679 #size-cells = <0>;
680 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
681 clock-names = "spi", "spi_busclk0";
682 samsung,spi-src-clk = <0>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&spi1_bus>;
685 status = "disabled";
686 };
687
688 i2s2: i2s@13970000 {
689 compatible = "samsung,s3c6410-i2s";
690 reg = <0x13970000 0x100>;
691 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
693 clock-names = "iis", "i2s_opclk0";
694 dmas = <&pdma0 14>, <&pdma0 13>;
695 dma-names = "tx", "rx";
696 pinctrl-0 = <&i2s2_bus>;
697 pinctrl-names = "default";
698 status = "disabled";
699 };
700
701 pwm: pwm@139d0000 {
702 compatible = "samsung,exynos4210-pwm";
703 reg = <0x139D0000 0x1000>;
704 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
709 #pwm-cells = <3>;
710 status = "disabled";
711 };
712
713 ppmu_dmc0: ppmu_dmc0@106a0000 {
714 compatible = "samsung,exynos-ppmu";
715 reg = <0x106a0000 0x2000>;
716 status = "disabled";
717 };
718
719 ppmu_dmc1: ppmu_dmc1@106b0000 {
720 compatible = "samsung,exynos-ppmu";
721 reg = <0x106b0000 0x2000>;
722 status = "disabled";
723 };
724
725 ppmu_cpu: ppmu_cpu@106c0000 {
726 compatible = "samsung,exynos-ppmu";
727 reg = <0x106c0000 0x2000>;
728 status = "disabled";
729 };
730
731 ppmu_rightbus: ppmu_rightbus@112a0000 {
732 compatible = "samsung,exynos-ppmu";
733 reg = <0x112a0000 0x2000>;
734 clocks = <&cmu CLK_PPMURIGHT>;
735 clock-names = "ppmu";
736 status = "disabled";
737 };
738
739 ppmu_leftbus: ppmu_leftbus0@116a0000 {
740 compatible = "samsung,exynos-ppmu";
741 reg = <0x116a0000 0x2000>;
742 clocks = <&cmu CLK_PPMULEFT>;
743 clock-names = "ppmu";
744 status = "disabled";
745 };
746
747 ppmu_camif: ppmu_camif@11ac0000 {
748 compatible = "samsung,exynos-ppmu";
749 reg = <0x11ac0000 0x2000>;
750 clocks = <&cmu CLK_PPMUCAMIF>;
751 clock-names = "ppmu";
752 status = "disabled";
753 };
754
755 ppmu_lcd0: ppmu_lcd0@11e40000 {
756 compatible = "samsung,exynos-ppmu";
757 reg = <0x11e40000 0x2000>;
758 clocks = <&cmu CLK_PPMULCD0>;
759 clock-names = "ppmu";
760 status = "disabled";
761 };
762
763 ppmu_fsys: ppmu_fsys@12630000 {
764 compatible = "samsung,exynos-ppmu";
765 reg = <0x12630000 0x2000>;
766 clocks = <&cmu CLK_PPMUFILE>;
767 clock-names = "ppmu";
768 status = "disabled";
769 };
770
771 ppmu_g3d: ppmu_g3d@13220000 {
772 compatible = "samsung,exynos-ppmu";
773 reg = <0x13220000 0x2000>;
774 clocks = <&cmu CLK_PPMUG3D>;
775 clock-names = "ppmu";
776 status = "disabled";
777 };
778
779 ppmu_mfc: ppmu_mfc@13660000 {
780 compatible = "samsung,exynos-ppmu";
781 reg = <0x13660000 0x2000>;
782 clocks = <&cmu CLK_PPMUMFC_L>;
783 clock-names = "ppmu";
784 status = "disabled";
785 };
786
787 bus_dmc: bus_dmc {
788 compatible = "samsung,exynos-bus";
789 clocks = <&cmu_dmc CLK_DIV_DMC>;
790 clock-names = "bus";
791 operating-points-v2 = <&bus_dmc_opp_table>;
792 status = "disabled";
793 };
794
795 bus_dmc_opp_table: opp_table1 {
796 compatible = "operating-points-v2";
797 opp-shared;
798
799 opp-50000000 {
800 opp-hz = /bits/ 64 <50000000>;
801 opp-microvolt = <800000>;
802 };
803 opp-100000000 {
804 opp-hz = /bits/ 64 <100000000>;
805 opp-microvolt = <800000>;
806 };
807 opp-134000000 {
808 opp-hz = /bits/ 64 <134000000>;
809 opp-microvolt = <800000>;
810 };
811 opp-200000000 {
812 opp-hz = /bits/ 64 <200000000>;
813 opp-microvolt = <825000>;
814 };
815 opp-400000000 {
816 opp-hz = /bits/ 64 <400000000>;
817 opp-microvolt = <875000>;
818 };
819 };
820
821 bus_leftbus: bus_leftbus {
822 compatible = "samsung,exynos-bus";
823 clocks = <&cmu CLK_DIV_GDL>;
824 clock-names = "bus";
825 operating-points-v2 = <&bus_leftbus_opp_table>;
826 status = "disabled";
827 };
828
829 bus_rightbus: bus_rightbus {
830 compatible = "samsung,exynos-bus";
831 clocks = <&cmu CLK_DIV_GDR>;
832 clock-names = "bus";
833 operating-points-v2 = <&bus_leftbus_opp_table>;
834 status = "disabled";
835 };
836
837 bus_lcd0: bus_lcd0 {
838 compatible = "samsung,exynos-bus";
839 clocks = <&cmu CLK_DIV_ACLK_160>;
840 clock-names = "bus";
841 operating-points-v2 = <&bus_leftbus_opp_table>;
842 status = "disabled";
843 };
844
845 bus_fsys: bus_fsys {
846 compatible = "samsung,exynos-bus";
847 clocks = <&cmu CLK_DIV_ACLK_200>;
848 clock-names = "bus";
849 operating-points-v2 = <&bus_leftbus_opp_table>;
850 status = "disabled";
851 };
852
853 bus_mcuisp: bus_mcuisp {
854 compatible = "samsung,exynos-bus";
855 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
856 clock-names = "bus";
857 operating-points-v2 = <&bus_mcuisp_opp_table>;
858 status = "disabled";
859 };
860
861 bus_isp: bus_isp {
862 compatible = "samsung,exynos-bus";
863 clocks = <&cmu CLK_DIV_ACLK_266>;
864 clock-names = "bus";
865 operating-points-v2 = <&bus_isp_opp_table>;
866 status = "disabled";
867 };
868
869 bus_peril: bus_peril {
870 compatible = "samsung,exynos-bus";
871 clocks = <&cmu CLK_DIV_ACLK_100>;
872 clock-names = "bus";
873 operating-points-v2 = <&bus_peril_opp_table>;
874 status = "disabled";
875 };
876
877 bus_mfc: bus_mfc {
878 compatible = "samsung,exynos-bus";
879 clocks = <&cmu CLK_SCLK_MFC>;
880 clock-names = "bus";
881 operating-points-v2 = <&bus_leftbus_opp_table>;
882 status = "disabled";
883 };
884
885 bus_leftbus_opp_table: opp_table2 {
886 compatible = "operating-points-v2";
887 opp-shared;
888
889 opp-50000000 {
890 opp-hz = /bits/ 64 <50000000>;
891 opp-microvolt = <900000>;
892 };
893 opp-80000000 {
894 opp-hz = /bits/ 64 <80000000>;
895 opp-microvolt = <900000>;
896 };
897 opp-100000000 {
898 opp-hz = /bits/ 64 <100000000>;
899 opp-microvolt = <1000000>;
900 };
901 opp-134000000 {
902 opp-hz = /bits/ 64 <134000000>;
903 opp-microvolt = <1000000>;
904 };
905 opp-200000000 {
906 opp-hz = /bits/ 64 <200000000>;
907 opp-microvolt = <1000000>;
908 };
909 };
910
911 bus_mcuisp_opp_table: opp_table3 {
912 compatible = "operating-points-v2";
913 opp-shared;
914
915 opp-50000000 {
916 opp-hz = /bits/ 64 <50000000>;
917 };
918 opp-80000000 {
919 opp-hz = /bits/ 64 <80000000>;
920 };
921 opp-100000000 {
922 opp-hz = /bits/ 64 <100000000>;
923 };
924 opp-200000000 {
925 opp-hz = /bits/ 64 <200000000>;
926 };
927 opp-400000000 {
928 opp-hz = /bits/ 64 <400000000>;
929 };
930 };
931
932 bus_isp_opp_table: opp_table4 {
933 compatible = "operating-points-v2";
934 opp-shared;
935
936 opp-50000000 {
937 opp-hz = /bits/ 64 <50000000>;
938 };
939 opp-80000000 {
940 opp-hz = /bits/ 64 <80000000>;
941 };
942 opp-100000000 {
943 opp-hz = /bits/ 64 <100000000>;
944 };
945 opp-200000000 {
946 opp-hz = /bits/ 64 <200000000>;
947 };
948 opp-300000000 {
949 opp-hz = /bits/ 64 <300000000>;
950 };
951 };
952
953 bus_peril_opp_table: opp_table5 {
954 compatible = "operating-points-v2";
955 opp-shared;
956
957 opp-50000000 {
958 opp-hz = /bits/ 64 <50000000>;
959 };
960 opp-80000000 {
961 opp-hz = /bits/ 64 <80000000>;
962 };
963 opp-100000000 {
964 opp-hz = /bits/ 64 <100000000>;
965 };
966 };
967 };
968 };
969
970 #include "exynos3250-pinctrl.dtsi"
971 #include "exynos-syscon-restart.dtsi"
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