arch/arm/boot/dts/exynos4.dtsi

   1 /*
   2  * Samsung's Exynos4 SoC series common device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
  10  * SoCs from Exynos4 series can include this file and provide values for SoCs
  11  * specfic bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <dt-bindings/clock/exynos4.h>
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24 #include "skeleton.dtsi"
  25
  26 / {
  27         interrupt-parent = <&gic>;
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 csis0 = &csis_0;
  42                 csis1 = &csis_1;
  43                 fimc0 = &fimc_0;
  44                 fimc1 = &fimc_1;
  45                 fimc2 = &fimc_2;
  46                 fimc3 = &fimc_3;
  47                 serial0 = &serial_0;
  48                 serial1 = &serial_1;
  49                 serial2 = &serial_2;
  50                 serial3 = &serial_3;
  51         };
  52
  53         clock_audss: clock-controller@03810000 {
  54                 compatible = "samsung,exynos4210-audss-clock";
  55                 reg = <0x03810000 0x0C>;
  56                 #clock-cells = <1>;
  57         };
  58
  59         i2s0: i2s@03830000 {
  60                 compatible = "samsung,s5pv210-i2s";
  61                 reg = <0x03830000 0x100>;
  62                 clocks = <&clock_audss EXYNOS_I2S_BUS>;
  63                 clock-names = "iis";
  64                 #clock-cells = <1>;
  65                 clock-output-names = "i2s_cdclk0";
  66                 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
  67                 dma-names = "tx", "rx", "tx-sec";
  68                 samsung,idma-addr = <0x03000000>;
  69                 #sound-dai-cells = <1>;
  70                 status = "disabled";
  71         };
  72
  73         chipid@10000000 {
  74                 compatible = "samsung,exynos4210-chipid";
  75                 reg = <0x10000000 0x100>;
  76         };
  77
  78         mipi_phy: video-phy@10020710 {
  79                 compatible = "samsung,s5pv210-mipi-video-phy";
  80                 reg = <0x10020710 8>;
  81                 #phy-cells = <1>;
  82                 syscon = <&pmu_system_controller>;
  83         };
  84
  85         pd_mfc: mfc-power-domain@10023C40 {
  86                 compatible = "samsung,exynos4210-pd";
  87                 reg = <0x10023C40 0x20>;
  88                 #power-domain-cells = <0>;
  89         };
  90
  91         pd_g3d: g3d-power-domain@10023C60 {
  92                 compatible = "samsung,exynos4210-pd";
  93                 reg = <0x10023C60 0x20>;
  94                 #power-domain-cells = <0>;
  95         };
  96
  97         pd_lcd0: lcd0-power-domain@10023C80 {
  98                 compatible = "samsung,exynos4210-pd";
  99                 reg = <0x10023C80 0x20>;
 100                 #power-domain-cells = <0>;
 101         };
 102
 103         pd_tv: tv-power-domain@10023C20 {
 104                 compatible = "samsung,exynos4210-pd";
 105                 reg = <0x10023C20 0x20>;
 106                 #power-domain-cells = <0>;
 107         };
 108
 109         pd_cam: cam-power-domain@10023C00 {
 110                 compatible = "samsung,exynos4210-pd";
 111                 reg = <0x10023C00 0x20>;
 112                 #power-domain-cells = <0>;
 113         };
 114
 115         pd_gps: gps-power-domain@10023CE0 {
 116                 compatible = "samsung,exynos4210-pd";
 117                 reg = <0x10023CE0 0x20>;
 118                 #power-domain-cells = <0>;
 119         };
 120
 121         pd_gps_alive: gps-alive-power-domain@10023D00 {
 122                 compatible = "samsung,exynos4210-pd";
 123                 reg = <0x10023D00 0x20>;
 124                 #power-domain-cells = <0>;
 125         };
 126
 127         gic: interrupt-controller@10490000 {
 128                 compatible = "arm,cortex-a9-gic";
 129                 #interrupt-cells = <3>;
 130                 interrupt-controller;
 131                 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
 132         };
 133
 134         combiner: interrupt-controller@10440000 {
 135                 compatible = "samsung,exynos4210-combiner";
 136                 #interrupt-cells = <2>;
 137                 interrupt-controller;
 138                 reg = <0x10440000 0x1000>;
 139         };
 140
 141         pmu {
 142                 compatible = "arm,cortex-a9-pmu";
 143                 interrupt-parent = <&combiner>;
 144                 interrupts = <2 2>, <3 2>;
 145         };
 146
 147         sys_reg: syscon@10010000 {
 148                 compatible = "samsung,exynos4-sysreg", "syscon";
 149                 reg = <0x10010000 0x400>;
 150         };
 151
 152         pmu_system_controller: system-controller@10020000 {
 153                 compatible = "samsung,exynos4210-pmu", "syscon";
 154                 reg = <0x10020000 0x4000>;
 155                 interrupt-controller;
 156                 #interrupt-cells = <3>;
 157                 interrupt-parent = <&gic>;
 158         };
 159
 160         dsi_0: dsi@11C80000 {
 161                 compatible = "samsung,exynos4210-mipi-dsi";
 162                 reg = <0x11C80000 0x10000>;
 163                 interrupts = <0 79 0>;
 164                 power-domains = <&pd_lcd0>;
 165                 phys = <&mipi_phy 1>;
 166                 phy-names = "dsim";
 167                 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
 168                 clock-names = "bus_clk", "pll_clk";
 169                 status = "disabled";
 170                 #address-cells = <1>;
 171                 #size-cells = <0>;
 172         };
 173
 174         camera {
 175                 compatible = "samsung,fimc", "simple-bus";
 176                 status = "disabled";
 177                 #address-cells = <1>;
 178                 #size-cells = <1>;
 179                 #clock-cells = <1>;
 180                 clock-output-names = "cam_a_clkout", "cam_b_clkout";
 181                 ranges;
 182
 183                 fimc_0: fimc@11800000 {
 184                         compatible = "samsung,exynos4210-fimc";
 185                         reg = <0x11800000 0x1000>;
 186                         interrupts = <0 84 0>;
 187                         clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
 188                         clock-names = "fimc", "sclk_fimc";
 189                         power-domains = <&pd_cam>;
 190                         samsung,sysreg = <&sys_reg>;
 191                         status = "disabled";
 192                 };
 193
 194                 fimc_1: fimc@11810000 {
 195                         compatible = "samsung,exynos4210-fimc";
 196                         reg = <0x11810000 0x1000>;
 197                         interrupts = <0 85 0>;
 198                         clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
 199                         clock-names = "fimc", "sclk_fimc";
 200                         power-domains = <&pd_cam>;
 201                         samsung,sysreg = <&sys_reg>;
 202                         status = "disabled";
 203                 };
 204
 205                 fimc_2: fimc@11820000 {
 206                         compatible = "samsung,exynos4210-fimc";
 207                         reg = <0x11820000 0x1000>;
 208                         interrupts = <0 86 0>;
 209                         clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
 210                         clock-names = "fimc", "sclk_fimc";
 211                         power-domains = <&pd_cam>;
 212                         samsung,sysreg = <&sys_reg>;
 213                         status = "disabled";
 214                 };
 215
 216                 fimc_3: fimc@11830000 {
 217                         compatible = "samsung,exynos4210-fimc";
 218                         reg = <0x11830000 0x1000>;
 219                         interrupts = <0 87 0>;
 220                         clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
 221                         clock-names = "fimc", "sclk_fimc";
 222                         power-domains = <&pd_cam>;
 223                         samsung,sysreg = <&sys_reg>;
 224                         status = "disabled";
 225                 };
 226
 227                 csis_0: csis@11880000 {
 228                         compatible = "samsung,exynos4210-csis";
 229                         reg = <0x11880000 0x4000>;
 230                         interrupts = <0 78 0>;
 231                         clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
 232                         clock-names = "csis", "sclk_csis";
 233                         bus-width = <4>;
 234                         power-domains = <&pd_cam>;
 235                         phys = <&mipi_phy 0>;
 236                         phy-names = "csis";
 237                         status = "disabled";
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                 };
 241
 242                 csis_1: csis@11890000 {
 243                         compatible = "samsung,exynos4210-csis";
 244                         reg = <0x11890000 0x4000>;
 245                         interrupts = <0 80 0>;
 246                         clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
 247                         clock-names = "csis", "sclk_csis";
 248                         bus-width = <2>;
 249                         power-domains = <&pd_cam>;
 250                         phys = <&mipi_phy 2>;
 251                         phy-names = "csis";
 252                         status = "disabled";
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                 };
 256         };
 257
 258         watchdog@10060000 {
 259                 compatible = "samsung,s3c2410-wdt";
 260                 reg = <0x10060000 0x100>;
 261                 interrupts = <0 43 0>;
 262                 clocks = <&clock CLK_WDT>;
 263                 clock-names = "watchdog";
 264                 status = "disabled";
 265         };
 266
 267         rtc@10070000 {
 268                 compatible = "samsung,s3c6410-rtc";
 269                 reg = <0x10070000 0x100>;
 270                 interrupt-parent = <&pmu_system_controller>;
 271                 interrupts = <0 44 0>, <0 45 0>;
 272                 clocks = <&clock CLK_RTC>;
 273                 clock-names = "rtc";
 274                 status = "disabled";
 275         };
 276
 277         keypad@100A0000 {
 278                 compatible = "samsung,s5pv210-keypad";
 279                 reg = <0x100A0000 0x100>;
 280                 interrupts = <0 109 0>;
 281                 clocks = <&clock CLK_KEYIF>;
 282                 clock-names = "keypad";
 283                 status = "disabled";
 284         };
 285
 286         sdhci@12510000 {
 287                 compatible = "samsung,exynos4210-sdhci";
 288                 reg = <0x12510000 0x100>;
 289                 interrupts = <0 73 0>;
 290                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 291                 clock-names = "hsmmc", "mmc_busclk.2";
 292                 status = "disabled";
 293         };
 294
 295         sdhci@12520000 {
 296                 compatible = "samsung,exynos4210-sdhci";
 297                 reg = <0x12520000 0x100>;
 298                 interrupts = <0 74 0>;
 299                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 300                 clock-names = "hsmmc", "mmc_busclk.2";
 301                 status = "disabled";
 302         };
 303
 304         sdhci@12530000 {
 305                 compatible = "samsung,exynos4210-sdhci";
 306                 reg = <0x12530000 0x100>;
 307                 interrupts = <0 75 0>;
 308                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 309                 clock-names = "hsmmc", "mmc_busclk.2";
 310                 status = "disabled";
 311         };
 312
 313         sdhci@12540000 {
 314                 compatible = "samsung,exynos4210-sdhci";
 315                 reg = <0x12540000 0x100>;
 316                 interrupts = <0 76 0>;
 317                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 318                 clock-names = "hsmmc", "mmc_busclk.2";
 319                 status = "disabled";
 320         };
 321
 322         exynos_usbphy: exynos-usbphy@125B0000 {
 323                 compatible = "samsung,exynos4210-usb2-phy";
 324                 reg = <0x125B0000 0x100>;
 325                 samsung,pmureg-phandle = <&pmu_system_controller>;
 326                 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
 327                 clock-names = "phy", "ref";
 328                 #phy-cells = <1>;
 329                 status = "disabled";
 330         };
 331
 332         hsotg@12480000 {
 333                 compatible = "samsung,s3c6400-hsotg";
 334                 reg = <0x12480000 0x20000>;
 335                 interrupts = <0 71 0>;
 336                 clocks = <&clock CLK_USB_DEVICE>;
 337                 clock-names = "otg";
 338                 phys = <&exynos_usbphy 0>;
 339                 phy-names = "usb2-phy";
 340                 status = "disabled";
 341         };
 342
 343         ehci@12580000 {
 344                 compatible = "samsung,exynos4210-ehci";
 345                 reg = <0x12580000 0x100>;
 346                 interrupts = <0 70 0>;
 347                 clocks = <&clock CLK_USB_HOST>;
 348                 clock-names = "usbhost";
 349                 status = "disabled";
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 port@0 {
 353                     reg = <0>;
 354                     phys = <&exynos_usbphy 1>;
 355                     status = "disabled";
 356                 };
 357                 port@1 {
 358                     reg = <1>;
 359                     phys = <&exynos_usbphy 2>;
 360                     status = "disabled";
 361                 };
 362                 port@2 {
 363                     reg = <2>;
 364                     phys = <&exynos_usbphy 3>;
 365                     status = "disabled";
 366                 };
 367         };
 368
 369         ohci@12590000 {
 370                 compatible = "samsung,exynos4210-ohci";
 371                 reg = <0x12590000 0x100>;
 372                 interrupts = <0 70 0>;
 373                 clocks = <&clock CLK_USB_HOST>;
 374                 clock-names = "usbhost";
 375                 status = "disabled";
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 port@0 {
 379                     reg = <0>;
 380                     phys = <&exynos_usbphy 1>;
 381                     status = "disabled";
 382                 };
 383         };
 384
 385         i2s1: i2s@13960000 {
 386                 compatible = "samsung,s3c6410-i2s";
 387                 reg = <0x13960000 0x100>;
 388                 clocks = <&clock CLK_I2S1>;
 389                 clock-names = "iis";
 390                 #clock-cells = <1>;
 391                 clock-output-names = "i2s_cdclk1";
 392                 dmas = <&pdma1 12>, <&pdma1 11>;
 393                 dma-names = "tx", "rx";
 394                 #sound-dai-cells = <1>;
 395                 status = "disabled";
 396         };
 397
 398         i2s2: i2s@13970000 {
 399                 compatible = "samsung,s3c6410-i2s";
 400                 reg = <0x13970000 0x100>;
 401                 clocks = <&clock CLK_I2S2>;
 402                 clock-names = "iis";
 403                 #clock-cells = <1>;
 404                 clock-output-names = "i2s_cdclk2";
 405                 dmas = <&pdma0 14>, <&pdma0 13>;
 406                 dma-names = "tx", "rx";
 407                 #sound-dai-cells = <1>;
 408                 status = "disabled";
 409         };
 410
 411         mfc: codec@13400000 {
 412                 compatible = "samsung,mfc-v5";
 413                 reg = <0x13400000 0x10000>;
 414                 interrupts = <0 94 0>;
 415                 power-domains = <&pd_mfc>;
 416                 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
 417                 clock-names = "mfc", "sclk_mfc";
 418                 status = "disabled";
 419         };
 420
 421         serial_0: serial@13800000 {
 422                 compatible = "samsung,exynos4210-uart";
 423                 reg = <0x13800000 0x100>;
 424                 interrupts = <0 52 0>;
 425                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 426                 clock-names = "uart", "clk_uart_baud0";
 427                 status = "disabled";
 428         };
 429
 430         serial_1: serial@13810000 {
 431                 compatible = "samsung,exynos4210-uart";
 432                 reg = <0x13810000 0x100>;
 433                 interrupts = <0 53 0>;
 434                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 435                 clock-names = "uart", "clk_uart_baud0";
 436                 status = "disabled";
 437         };
 438
 439         serial_2: serial@13820000 {
 440                 compatible = "samsung,exynos4210-uart";
 441                 reg = <0x13820000 0x100>;
 442                 interrupts = <0 54 0>;
 443                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 444                 clock-names = "uart", "clk_uart_baud0";
 445                 status = "disabled";
 446         };
 447
 448         serial_3: serial@13830000 {
 449                 compatible = "samsung,exynos4210-uart";
 450                 reg = <0x13830000 0x100>;
 451                 interrupts = <0 55 0>;
 452                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 453                 clock-names = "uart", "clk_uart_baud0";
 454                 status = "disabled";
 455         };
 456
 457         i2c_0: i2c@13860000 {
 458                 #address-cells = <1>;
 459                 #size-cells = <0>;
 460                 compatible = "samsung,s3c2440-i2c";
 461                 reg = <0x13860000 0x100>;
 462                 interrupts = <0 58 0>;
 463                 clocks = <&clock CLK_I2C0>;
 464                 clock-names = "i2c";
 465                 pinctrl-names = "default";
 466                 pinctrl-0 = <&i2c0_bus>;
 467                 status = "disabled";
 468         };
 469
 470         i2c_1: i2c@13870000 {
 471                 #address-cells = <1>;
 472                 #size-cells = <0>;
 473                 compatible = "samsung,s3c2440-i2c";
 474                 reg = <0x13870000 0x100>;
 475                 interrupts = <0 59 0>;
 476                 clocks = <&clock CLK_I2C1>;
 477                 clock-names = "i2c";
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&i2c1_bus>;
 480                 status = "disabled";
 481         };
 482
 483         i2c_2: i2c@13880000 {
 484                 #address-cells = <1>;
 485                 #size-cells = <0>;
 486                 compatible = "samsung,s3c2440-i2c";
 487                 reg = <0x13880000 0x100>;
 488                 interrupts = <0 60 0>;
 489                 clocks = <&clock CLK_I2C2>;
 490                 clock-names = "i2c";
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&i2c2_bus>;
 493                 status = "disabled";
 494         };
 495
 496         i2c_3: i2c@13890000 {
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 compatible = "samsung,s3c2440-i2c";
 500                 reg = <0x13890000 0x100>;
 501                 interrupts = <0 61 0>;
 502                 clocks = <&clock CLK_I2C3>;
 503                 clock-names = "i2c";
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&i2c3_bus>;
 506                 status = "disabled";
 507         };
 508
 509         i2c_4: i2c@138A0000 {
 510                 #address-cells = <1>;
 511                 #size-cells = <0>;
 512                 compatible = "samsung,s3c2440-i2c";
 513                 reg = <0x138A0000 0x100>;
 514                 interrupts = <0 62 0>;
 515                 clocks = <&clock CLK_I2C4>;
 516                 clock-names = "i2c";
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&i2c4_bus>;
 519                 status = "disabled";
 520         };
 521
 522         i2c_5: i2c@138B0000 {
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 compatible = "samsung,s3c2440-i2c";
 526                 reg = <0x138B0000 0x100>;
 527                 interrupts = <0 63 0>;
 528                 clocks = <&clock CLK_I2C5>;
 529                 clock-names = "i2c";
 530                 pinctrl-names = "default";
 531                 pinctrl-0 = <&i2c5_bus>;
 532                 status = "disabled";
 533         };
 534
 535         i2c_6: i2c@138C0000 {
 536                 #address-cells = <1>;
 537                 #size-cells = <0>;
 538                 compatible = "samsung,s3c2440-i2c";
 539                 reg = <0x138C0000 0x100>;
 540                 interrupts = <0 64 0>;
 541                 clocks = <&clock CLK_I2C6>;
 542                 clock-names = "i2c";
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&i2c6_bus>;
 545                 status = "disabled";
 546         };
 547
 548         i2c_7: i2c@138D0000 {
 549                 #address-cells = <1>;
 550                 #size-cells = <0>;
 551                 compatible = "samsung,s3c2440-i2c";
 552                 reg = <0x138D0000 0x100>;
 553                 interrupts = <0 65 0>;
 554                 clocks = <&clock CLK_I2C7>;
 555                 clock-names = "i2c";
 556                 pinctrl-names = "default";
 557                 pinctrl-0 = <&i2c7_bus>;
 558                 status = "disabled";
 559         };
 560
 561         spi_0: spi@13920000 {
 562                 compatible = "samsung,exynos4210-spi";
 563                 reg = <0x13920000 0x100>;
 564                 interrupts = <0 66 0>;
 565                 dmas = <&pdma0 7>, <&pdma0 6>;
 566                 dma-names = "tx", "rx";
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 570                 clock-names = "spi", "spi_busclk0";
 571                 pinctrl-names = "default";
 572                 pinctrl-0 = <&spi0_bus>;
 573                 status = "disabled";
 574         };
 575
 576         spi_1: spi@13930000 {
 577                 compatible = "samsung,exynos4210-spi";
 578                 reg = <0x13930000 0x100>;
 579                 interrupts = <0 67 0>;
 580                 dmas = <&pdma1 7>, <&pdma1 6>;
 581                 dma-names = "tx", "rx";
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 585                 clock-names = "spi", "spi_busclk0";
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&spi1_bus>;
 588                 status = "disabled";
 589         };
 590
 591         spi_2: spi@13940000 {
 592                 compatible = "samsung,exynos4210-spi";
 593                 reg = <0x13940000 0x100>;
 594                 interrupts = <0 68 0>;
 595                 dmas = <&pdma0 9>, <&pdma0 8>;
 596                 dma-names = "tx", "rx";
 597                 #address-cells = <1>;
 598                 #size-cells = <0>;
 599                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 600                 clock-names = "spi", "spi_busclk0";
 601                 pinctrl-names = "default";
 602                 pinctrl-0 = <&spi2_bus>;
 603                 status = "disabled";
 604         };
 605
 606         pwm@139D0000 {
 607                 compatible = "samsung,exynos4210-pwm";
 608                 reg = <0x139D0000 0x1000>;
 609                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
 610                 clocks = <&clock CLK_PWM>;
 611                 clock-names = "timers";
 612                 #pwm-cells = <3>;
 613                 status = "disabled";
 614         };
 615
 616         amba {
 617                 #address-cells = <1>;
 618                 #size-cells = <1>;
 619                 compatible = "arm,amba-bus";
 620                 interrupt-parent = <&gic>;
 621                 ranges;
 622
 623                 pdma0: pdma@12680000 {
 624                         compatible = "arm,pl330", "arm,primecell";
 625                         reg = <0x12680000 0x1000>;
 626                         interrupts = <0 35 0>;
 627                         clocks = <&clock CLK_PDMA0>;
 628                         clock-names = "apb_pclk";
 629                         #dma-cells = <1>;
 630                         #dma-channels = <8>;
 631                         #dma-requests = <32>;
 632                 };
 633
 634                 pdma1: pdma@12690000 {
 635                         compatible = "arm,pl330", "arm,primecell";
 636                         reg = <0x12690000 0x1000>;
 637                         interrupts = <0 36 0>;
 638                         clocks = <&clock CLK_PDMA1>;
 639                         clock-names = "apb_pclk";
 640                         #dma-cells = <1>;
 641                         #dma-channels = <8>;
 642                         #dma-requests = <32>;
 643                 };
 644
 645                 mdma1: mdma@12850000 {
 646                         compatible = "arm,pl330", "arm,primecell";
 647                         reg = <0x12850000 0x1000>;
 648                         interrupts = <0 34 0>;
 649                         clocks = <&clock CLK_MDMA>;
 650                         clock-names = "apb_pclk";
 651                         #dma-cells = <1>;
 652                         #dma-channels = <8>;
 653                         #dma-requests = <1>;
 654                 };
 655         };
 656
 657         fimd: fimd@11c00000 {
 658                 compatible = "samsung,exynos4210-fimd";
 659                 interrupt-parent = <&combiner>;
 660                 reg = <0x11c00000 0x20000>;
 661                 interrupt-names = "fifo", "vsync", "lcd_sys";
 662                 interrupts = <11 0>, <11 1>, <11 2>;
 663                 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
 664                 clock-names = "sclk_fimd", "fimd";
 665                 power-domains = <&pd_lcd0>;
 666                 samsung,sysreg = <&sys_reg>;
 667                 status = "disabled";
 668         };
 669
 670         ppmu_dmc0: ppmu_dmc0@106a0000 {
 671                 compatible = "samsung,exynos-ppmu";
 672                 reg = <0x106a0000 0x2000>;
 673                 clocks = <&clock CLK_PPMUDMC0>;
 674                 clock-names = "ppmu";
 675                 status = "disabled";
 676         };
 677
 678         ppmu_dmc1: ppmu_dmc1@106b0000 {
 679                 compatible = "samsung,exynos-ppmu";
 680                 reg = <0x106b0000 0x2000>;
 681                 clocks = <&clock CLK_PPMUDMC1>;
 682                 clock-names = "ppmu";
 683                 status = "disabled";
 684         };
 685
 686         ppmu_cpu: ppmu_cpu@106c0000 {
 687                 compatible = "samsung,exynos-ppmu";
 688                 reg = <0x106c0000 0x2000>;
 689                 clocks = <&clock CLK_PPMUCPU>;
 690                 clock-names = "ppmu";
 691                 status = "disabled";
 692         };
 693
 694         ppmu_acp: ppmu_acp@10ae0000 {
 695                 compatible = "samsung,exynos-ppmu";
 696                 reg = <0x106e0000 0x2000>;
 697                 status = "disabled";
 698         };
 699
 700         ppmu_rightbus: ppmu_rightbus@112a0000 {
 701                 compatible = "samsung,exynos-ppmu";
 702                 reg = <0x112a0000 0x2000>;
 703                 clocks = <&clock CLK_PPMURIGHT>;
 704                 clock-names = "ppmu";
 705                 status = "disabled";
 706         };
 707
 708         ppmu_leftbus: ppmu_leftbus0@116a0000 {
 709                 compatible = "samsung,exynos-ppmu";
 710                 reg = <0x116a0000 0x2000>;
 711                 clocks = <&clock CLK_PPMULEFT>;
 712                 clock-names = "ppmu";
 713                 status = "disabled";
 714         };
 715
 716         ppmu_camif: ppmu_camif@11ac0000 {
 717                 compatible = "samsung,exynos-ppmu";
 718                 reg = <0x11ac0000 0x2000>;
 719                 clocks = <&clock CLK_PPMUCAMIF>;
 720                 clock-names = "ppmu";
 721                 status = "disabled";
 722         };
 723
 724         ppmu_lcd0: ppmu_lcd0@11e40000 {
 725                 compatible = "samsung,exynos-ppmu";
 726                 reg = <0x11e40000 0x2000>;
 727                 clocks = <&clock CLK_PPMULCD0>;
 728                 clock-names = "ppmu";
 729                 status = "disabled";
 730         };
 731
 732         ppmu_fsys: ppmu_g3d@12630000 {
 733                 compatible = "samsung,exynos-ppmu";
 734                 reg = <0x12630000 0x2000>;
 735                 status = "disabled";
 736         };
 737
 738         ppmu_image: ppmu_image@12aa0000 {
 739                 compatible = "samsung,exynos-ppmu";
 740                 reg = <0x12aa0000 0x2000>;
 741                 clocks = <&clock CLK_PPMUIMAGE>;
 742                 clock-names = "ppmu";
 743                 status = "disabled";
 744         };
 745
 746         ppmu_tv: ppmu_tv@12e40000 {
 747                 compatible = "samsung,exynos-ppmu";
 748                 reg = <0x12e40000 0x2000>;
 749                 clocks = <&clock CLK_PPMUTV>;
 750                 clock-names = "ppmu";
 751                 status = "disabled";
 752         };
 753
 754         ppmu_g3d: ppmu_g3d@13220000 {
 755                 compatible = "samsung,exynos-ppmu";
 756                 reg = <0x13220000 0x2000>;
 757                 clocks = <&clock CLK_PPMUG3D>;
 758                 clock-names = "ppmu";
 759                 status = "disabled";
 760         };
 761
 762         ppmu_mfc_left: ppmu_mfc_left@13660000 {
 763                 compatible = "samsung,exynos-ppmu";
 764                 reg = <0x13660000 0x2000>;
 765                 clocks = <&clock CLK_PPMUMFC_L>;
 766                 clock-names = "ppmu";
 767                 status = "disabled";
 768         };
 769
 770         ppmu_mfc_right: ppmu_mfc_right@13670000 {
 771                 compatible = "samsung,exynos-ppmu";
 772                 reg = <0x13670000 0x2000>;
 773                 clocks = <&clock CLK_PPMUMFC_R>;
 774                 clock-names = "ppmu";
 775                 status = "disabled";
 776         };
 777 };