2 * Samsung's Exynos4210 SoC device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include "exynos4.dtsi"
23 #include "exynos4210-pinctrl.dtsi"
24 #include "exynos4-cpu-thermal.dtsi"
27 compatible = "samsung,exynos4210", "samsung,exynos4";
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 pinctrl2 = &pinctrl_2;
41 compatible = "arm,cortex-a9";
43 clocks = <&clock CLK_ARM_CLK>;
45 clock-latency = <160000>;
55 cooling-min-level = <4>;
56 cooling-max-level = <2>;
57 #cooling-cells = <2>; /* min followed by max */
62 compatible = "arm,cortex-a9";
67 sysram: sysram@02020000 {
68 compatible = "mmio-sram";
69 reg = <0x02020000 0x20000>;
72 ranges = <0 0x02020000 0x20000>;
75 compatible = "samsung,exynos4210-sysram";
80 compatible = "samsung,exynos4210-sysram-ns";
81 reg = <0x1f000 0x1000>;
85 pd_lcd1: lcd1-power-domain@10023CA0 {
86 compatible = "samsung,exynos4210-pd";
87 reg = <0x10023CA0 0x20>;
88 #power-domain-cells = <0>;
92 l2c: l2-cache-controller@10502000 {
93 compatible = "arm,pl310-cache";
94 reg = <0x10502000 0x1000>;
97 arm,tag-latency = <2 2 1>;
98 arm,data-latency = <2 2 1>;
102 compatible = "samsung,exynos4210-mct";
103 reg = <0x10050000 0x800>;
104 interrupt-parent = <&mct_map>;
105 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
106 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
107 clock-names = "fin_pll", "mct";
110 #interrupt-cells = <1>;
111 #address-cells = <0>;
113 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
114 <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
117 <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
118 <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
122 clock: clock-controller@10030000 {
123 compatible = "samsung,exynos4210-clock";
124 reg = <0x10030000 0x20000>;
128 pinctrl_0: pinctrl@11400000 {
129 compatible = "samsung,exynos4210-pinctrl";
130 reg = <0x11400000 0x1000>;
131 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
134 pinctrl_1: pinctrl@11000000 {
135 compatible = "samsung,exynos4210-pinctrl";
136 reg = <0x11000000 0x1000>;
137 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
139 wakup_eint: wakeup-interrupt-controller {
140 compatible = "samsung,exynos4210-wakeup-eint";
141 interrupt-parent = <&gic>;
142 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
146 pinctrl_2: pinctrl@03860000 {
147 compatible = "samsung,exynos4210-pinctrl";
148 reg = <0x03860000 0x1000>;
152 compatible = "samsung,exynos4210-tmu";
153 interrupt-parent = <&combiner>;
154 reg = <0x100C0000 0x100>;
156 clocks = <&clock CLK_TMU_APBIF>;
157 clock-names = "tmu_apbif";
158 samsung,tmu_gain = <15>;
159 samsung,tmu_reference_voltage = <7>;
164 cpu_thermal: cpu-thermal {
165 polling-delay-passive = <0>;
167 thermal-sensors = <&tmu 0>;
170 cpu_alert0: cpu-alert-0 {
171 temperature = <85000>; /* millicelsius */
173 cpu_alert1: cpu-alert-1 {
174 temperature = <100000>; /* millicelsius */
176 cpu_alert2: cpu-alert-2 {
177 temperature = <110000>; /* millicelsius */
184 compatible = "samsung,s5pv210-g2d";
185 reg = <0x12800000 0x1000>;
186 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
188 clock-names = "sclk_fimg2d", "fimg2d";
189 power-domains = <&pd_lcd0>;
190 iommus = <&sysmmu_g2d>;
194 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
195 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
196 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
198 fimc_0: fimc@11800000 {
199 samsung,pix-limits = <4224 8192 1920 4224>;
200 samsung,mainscaler-ext;
204 fimc_1: fimc@11810000 {
205 samsung,pix-limits = <4224 8192 1920 4224>;
206 samsung,mainscaler-ext;
210 fimc_2: fimc@11820000 {
211 samsung,pix-limits = <4224 8192 1920 4224>;
212 samsung,mainscaler-ext;
216 fimc_3: fimc@11830000 {
217 samsung,pix-limits = <1920 8192 1366 1920>;
218 samsung,rotators = <0>;
219 samsung,mainscaler-ext;
224 mixer: mixer@12C10000 {
225 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
227 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
228 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
229 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
232 ppmu_lcd1: ppmu_lcd1@12240000 {
233 compatible = "samsung,exynos-ppmu";
234 reg = <0x12240000 0x2000>;
235 clocks = <&clock CLK_PPMULCD1>;
236 clock-names = "ppmu";
240 sysmmu_g2d: sysmmu@12A20000 {
241 compatible = "samsung,exynos-sysmmu";
242 reg = <0x12A20000 0x1000>;
243 interrupt-parent = <&combiner>;
245 clock-names = "sysmmu", "master";
246 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
247 power-domains = <&pd_lcd0>;
251 sysmmu_fimd1: sysmmu@12220000 {
252 compatible = "samsung,exynos-sysmmu";
253 interrupt-parent = <&combiner>;
254 reg = <0x12220000 0x1000>;
256 clock-names = "sysmmu", "master";
257 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
258 power-domains = <&pd_lcd1>;
263 compatible = "samsung,exynos-bus";
264 clocks = <&clock CLK_DIV_DMC>;
266 operating-points-v2 = <&bus_dmc_opp_table>;
271 compatible = "samsung,exynos-bus";
272 clocks = <&clock CLK_DIV_ACP>;
274 operating-points-v2 = <&bus_acp_opp_table>;
279 compatible = "samsung,exynos-bus";
280 clocks = <&clock CLK_ACLK100>;
282 operating-points-v2 = <&bus_peri_opp_table>;
287 compatible = "samsung,exynos-bus";
288 clocks = <&clock CLK_ACLK133>;
290 operating-points-v2 = <&bus_fsys_opp_table>;
294 bus_display: bus_display {
295 compatible = "samsung,exynos-bus";
296 clocks = <&clock CLK_ACLK160>;
298 operating-points-v2 = <&bus_display_opp_table>;
303 compatible = "samsung,exynos-bus";
304 clocks = <&clock CLK_ACLK200>;
306 operating-points-v2 = <&bus_leftbus_opp_table>;
310 bus_leftbus: bus_leftbus {
311 compatible = "samsung,exynos-bus";
312 clocks = <&clock CLK_DIV_GDL>;
314 operating-points-v2 = <&bus_leftbus_opp_table>;
318 bus_rightbus: bus_rightbus {
319 compatible = "samsung,exynos-bus";
320 clocks = <&clock CLK_DIV_GDR>;
322 operating-points-v2 = <&bus_leftbus_opp_table>;
327 compatible = "samsung,exynos-bus";
328 clocks = <&clock CLK_SCLK_MFC>;
330 operating-points-v2 = <&bus_leftbus_opp_table>;
334 bus_dmc_opp_table: opp_table1 {
335 compatible = "operating-points-v2";
339 opp-hz = /bits/ 64 <134000000>;
340 opp-microvolt = <1025000>;
343 opp-hz = /bits/ 64 <267000000>;
344 opp-microvolt = <1050000>;
347 opp-hz = /bits/ 64 <400000000>;
348 opp-microvolt = <1150000>;
352 bus_acp_opp_table: opp_table2 {
353 compatible = "operating-points-v2";
357 opp-hz = /bits/ 64 <134000000>;
360 opp-hz = /bits/ 64 <160000000>;
363 opp-hz = /bits/ 64 <200000000>;
367 bus_peri_opp_table: opp_table3 {
368 compatible = "operating-points-v2";
372 opp-hz = /bits/ 64 <5000000>;
375 opp-hz = /bits/ 64 <100000000>;
379 bus_fsys_opp_table: opp_table4 {
380 compatible = "operating-points-v2";
384 opp-hz = /bits/ 64 <10000000>;
387 opp-hz = /bits/ 64 <134000000>;
391 bus_display_opp_table: opp_table5 {
392 compatible = "operating-points-v2";
396 opp-hz = /bits/ 64 <100000000>;
399 opp-hz = /bits/ 64 <134000000>;
402 opp-hz = /bits/ 64 <160000000>;
406 bus_leftbus_opp_table: opp_table6 {
407 compatible = "operating-points-v2";
411 opp-hz = /bits/ 64 <100000000>;
414 opp-hz = /bits/ 64 <160000000>;
417 opp-hz = /bits/ 64 <200000000>;
423 cpu-offset = <0x8000>;
427 samsung,combiner-nr = <16>;
428 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
447 power-domains = <&pd_lcd0>;
450 &pmu_system_controller {
451 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
452 "clkout4", "clkout8", "clkout9";
453 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
454 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
455 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
460 power-domains = <&pd_lcd0>;
464 power-domains = <&pd_lcd0>;