arch/arm/boot/dts/exynos4x12.dtsi

   1 /*
   2  * Samsung's Exynos4x12 SoCs device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4.dtsi"
  21 #include "exynos4x12-pinctrl.dtsi"
  22 #include "exynos4-cpu-thermal.dtsi"
  23
  24 / {
  25         aliases {
  26                 pinctrl0 = &pinctrl_0;
  27                 pinctrl1 = &pinctrl_1;
  28                 pinctrl2 = &pinctrl_2;
  29                 pinctrl3 = &pinctrl_3;
  30                 fimc-lite0 = &fimc_lite_0;
  31                 fimc-lite1 = &fimc_lite_1;
  32                 mshc0 = &mshc_0;
  33         };
  34
  35         sysram@02020000 {
  36                 compatible = "mmio-sram";
  37                 reg = <0x02020000 0x40000>;
  38                 #address-cells = <1>;
  39                 #size-cells = <1>;
  40                 ranges = <0 0x02020000 0x40000>;
  41
  42                 smp-sysram@0 {
  43                         compatible = "samsung,exynos4210-sysram";
  44                         reg = <0x0 0x1000>;
  45                 };
  46
  47                 smp-sysram@2f000 {
  48                         compatible = "samsung,exynos4210-sysram-ns";
  49                         reg = <0x2f000 0x1000>;
  50                 };
  51         };
  52
  53         pd_isp: isp-power-domain@10023CA0 {
  54                 compatible = "samsung,exynos4210-pd";
  55                 reg = <0x10023CA0 0x20>;
  56                 #power-domain-cells = <0>;
  57         };
  58
  59         l2c: l2-cache-controller@10502000 {
  60                 compatible = "arm,pl310-cache";
  61                 reg = <0x10502000 0x1000>;
  62                 cache-unified;
  63                 cache-level = <2>;
  64                 arm,tag-latency = <2 2 1>;
  65                 arm,data-latency = <3 2 1>;
  66                 arm,double-linefill = <1>;
  67                 arm,double-linefill-incr = <0>;
  68                 arm,double-linefill-wrap = <1>;
  69                 arm,prefetch-drop = <1>;
  70                 arm,prefetch-offset = <7>;
  71         };
  72
  73         clock: clock-controller@10030000 {
  74                 compatible = "samsung,exynos4412-clock";
  75                 reg = <0x10030000 0x20000>;
  76                 #clock-cells = <1>;
  77         };
  78
  79         mct@10050000 {
  80                 compatible = "samsung,exynos4412-mct";
  81                 reg = <0x10050000 0x800>;
  82                 interrupt-parent = <&mct_map>;
  83                 interrupts = <0>, <1>, <2>, <3>, <4>;
  84                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  85                 clock-names = "fin_pll", "mct";
  86
  87                 mct_map: mct-map {
  88                         #interrupt-cells = <1>;
  89                         #address-cells = <0>;
  90                         #size-cells = <0>;
  91                         interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
  92                                         <1 &combiner 12 5>,
  93                                         <2 &combiner 12 6>,
  94                                         <3 &combiner 12 7>,
  95                                         <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
  96                 };
  97         };
  98
  99         adc: adc@126C0000 {
 100                 compatible = "samsung,exynos-adc-v1";
 101                 reg = <0x126C0000 0x100>;
 102                 interrupt-parent = <&combiner>;
 103                 interrupts = <10 3>;
 104                 clocks = <&clock CLK_TSADC>;
 105                 clock-names = "adc";
 106                 #io-channel-cells = <1>;
 107                 io-channel-ranges;
 108                 samsung,syscon-phandle = <&pmu_system_controller>;
 109                 status = "disabled";
 110         };
 111
 112         g2d: g2d@10800000 {
 113                 compatible = "samsung,exynos4212-g2d";
 114                 reg = <0x10800000 0x1000>;
 115                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 116                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 117                 clock-names = "sclk_fimg2d", "fimg2d";
 118                 iommus = <&sysmmu_g2d>;
 119         };
 120
 121         camera {
 122                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 123                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 124                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 125
 126                 /* fimc_[0-3] are configured outside, under phandles */
 127                 fimc_lite_0: fimc-lite@12390000 {
 128                         compatible = "samsung,exynos4212-fimc-lite";
 129                         reg = <0x12390000 0x1000>;
 130                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 131                         power-domains = <&pd_isp>;
 132                         clocks = <&clock CLK_FIMC_LITE0>;
 133                         clock-names = "flite";
 134                         iommus = <&sysmmu_fimc_lite0>;
 135                         status = "disabled";
 136                 };
 137
 138                 fimc_lite_1: fimc-lite@123A0000 {
 139                         compatible = "samsung,exynos4212-fimc-lite";
 140                         reg = <0x123A0000 0x1000>;
 141                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 142                         power-domains = <&pd_isp>;
 143                         clocks = <&clock CLK_FIMC_LITE1>;
 144                         clock-names = "flite";
 145                         iommus = <&sysmmu_fimc_lite1>;
 146                         status = "disabled";
 147                 };
 148
 149                 fimc_is: fimc-is@12000000 {
 150                         compatible = "samsung,exynos4212-fimc-is";
 151                         reg = <0x12000000 0x260000>;
 152                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 153                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 154                         power-domains = <&pd_isp>;
 155                         clocks = <&clock CLK_FIMC_LITE0>,
 156                                  <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
 157                                  <&clock CLK_PPMUISPMX>,
 158                                  <&clock CLK_MOUT_MPLL_USER_T>,
 159                                  <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
 160                                  <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
 161                                  <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>,
 162                                  <&clock CLK_PWM_ISP>,
 163                                  <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>,
 164                                  <&clock CLK_DIV_MCUISP0>,
 165                                  <&clock CLK_DIV_MCUISP1>,
 166                                  <&clock CLK_UART_ISP_SCLK>,
 167                                  <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
 168                                  <&clock CLK_ACLK400_MCUISP>,
 169                                  <&clock CLK_DIV_ACLK400_MCUISP>;
 170                         clock-names = "lite0", "lite1", "ppmuispx",
 171                                       "ppmuispmx", "mpll", "isp",
 172                                       "drc", "fd", "mcuisp",
 173                                       "gicisp", "mcuctl_isp", "pwm_isp",
 174                                       "ispdiv0", "ispdiv1", "mcuispdiv0",
 175                                       "mcuispdiv1", "uart", "aclk200",
 176                                       "div_aclk200", "aclk400mcuisp",
 177                                       "div_aclk400mcuisp";
 178                         iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
 179                                  <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
 180                         iommu-names = "isp", "drc", "fd", "mcuctl";
 181                         #address-cells = <1>;
 182                         #size-cells = <1>;
 183                         ranges;
 184                         status = "disabled";
 185
 186                         pmu@10020000 {
 187                                 reg = <0x10020000 0x3000>;
 188                         };
 189
 190                         i2c1_isp: i2c-isp@12140000 {
 191                                 compatible = "samsung,exynos4212-i2c-isp";
 192                                 reg = <0x12140000 0x100>;
 193                                 clocks = <&clock CLK_I2C1_ISP>;
 194                                 clock-names = "i2c_isp";
 195                                 #address-cells = <1>;
 196                                 #size-cells = <0>;
 197                         };
 198                 };
 199         };
 200
 201         mshc_0: mmc@12550000 {
 202                 compatible = "samsung,exynos4412-dw-mshc";
 203                 reg = <0x12550000 0x1000>;
 204                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 205                 #address-cells = <1>;
 206                 #size-cells = <0>;
 207                 fifo-depth = <0x80>;
 208                 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 209                 clock-names = "biu", "ciu";
 210                 status = "disabled";
 211         };
 212
 213         sysmmu_g2d: sysmmu@10A40000{
 214                 compatible = "samsung,exynos-sysmmu";
 215                 reg = <0x10A40000 0x1000>;
 216                 interrupt-parent = <&combiner>;
 217                 interrupts = <4 7>;
 218                 clock-names = "sysmmu", "master";
 219                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 220                 #iommu-cells = <0>;
 221         };
 222
 223         sysmmu_fimc_isp: sysmmu@12260000 {
 224                 compatible = "samsung,exynos-sysmmu";
 225                 reg = <0x12260000 0x1000>;
 226                 interrupt-parent = <&combiner>;
 227                 interrupts = <16 2>;
 228                 power-domains = <&pd_isp>;
 229                 clock-names = "sysmmu";
 230                 clocks = <&clock CLK_SMMU_ISP>;
 231                 #iommu-cells = <0>;
 232         };
 233
 234         sysmmu_fimc_drc: sysmmu@12270000 {
 235                 compatible = "samsung,exynos-sysmmu";
 236                 reg = <0x12270000 0x1000>;
 237                 interrupt-parent = <&combiner>;
 238                 interrupts = <16 3>;
 239                 power-domains = <&pd_isp>;
 240                 clock-names = "sysmmu";
 241                 clocks = <&clock CLK_SMMU_DRC>;
 242                 #iommu-cells = <0>;
 243         };
 244
 245         sysmmu_fimc_fd: sysmmu@122A0000 {
 246                 compatible = "samsung,exynos-sysmmu";
 247                 reg = <0x122A0000 0x1000>;
 248                 interrupt-parent = <&combiner>;
 249                 interrupts = <16 4>;
 250                 power-domains = <&pd_isp>;
 251                 clock-names = "sysmmu";
 252                 clocks = <&clock CLK_SMMU_FD>;
 253                 #iommu-cells = <0>;
 254         };
 255
 256         sysmmu_fimc_mcuctl: sysmmu@122B0000 {
 257                 compatible = "samsung,exynos-sysmmu";
 258                 reg = <0x122B0000 0x1000>;
 259                 interrupt-parent = <&combiner>;
 260                 interrupts = <16 5>;
 261                 power-domains = <&pd_isp>;
 262                 clock-names = "sysmmu";
 263                 clocks = <&clock CLK_SMMU_ISPCX>;
 264                 #iommu-cells = <0>;
 265         };
 266
 267         sysmmu_fimc_lite0: sysmmu@123B0000 {
 268                 compatible = "samsung,exynos-sysmmu";
 269                 reg = <0x123B0000 0x1000>;
 270                 interrupt-parent = <&combiner>;
 271                 interrupts = <16 0>;
 272                 power-domains = <&pd_isp>;
 273                 clock-names = "sysmmu", "master";
 274                 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
 275                 #iommu-cells = <0>;
 276         };
 277
 278         sysmmu_fimc_lite1: sysmmu@123C0000 {
 279                 compatible = "samsung,exynos-sysmmu";
 280                 reg = <0x123C0000 0x1000>;
 281                 interrupt-parent = <&combiner>;
 282                 interrupts = <16 1>;
 283                 power-domains = <&pd_isp>;
 284                 clock-names = "sysmmu", "master";
 285                 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
 286                 #iommu-cells = <0>;
 287         };
 288
 289         bus_dmc: bus_dmc {
 290                 compatible = "samsung,exynos-bus";
 291                 clocks = <&clock CLK_DIV_DMC>;
 292                 clock-names = "bus";
 293                 operating-points-v2 = <&bus_dmc_opp_table>;
 294                 status = "disabled";
 295         };
 296
 297         bus_acp: bus_acp {
 298                 compatible = "samsung,exynos-bus";
 299                 clocks = <&clock CLK_DIV_ACP>;
 300                 clock-names = "bus";
 301                 operating-points-v2 = <&bus_acp_opp_table>;
 302                 status = "disabled";
 303         };
 304
 305         bus_c2c: bus_c2c {
 306                 compatible = "samsung,exynos-bus";
 307                 clocks = <&clock CLK_DIV_C2C>;
 308                 clock-names = "bus";
 309                 operating-points-v2 = <&bus_dmc_opp_table>;
 310                 status = "disabled";
 311         };
 312
 313         bus_dmc_opp_table: opp_table1 {
 314                 compatible = "operating-points-v2";
 315                 opp-shared;
 316
 317                 opp@100000000 {
 318                         opp-hz = /bits/ 64 <100000000>;
 319                         opp-microvolt = <900000>;
 320                 };
 321                 opp@134000000 {
 322                         opp-hz = /bits/ 64 <134000000>;
 323                         opp-microvolt = <900000>;
 324                 };
 325                 opp@160000000 {
 326                         opp-hz = /bits/ 64 <160000000>;
 327                         opp-microvolt = <900000>;
 328                 };
 329                 opp@267000000 {
 330                         opp-hz = /bits/ 64 <267000000>;
 331                         opp-microvolt = <950000>;
 332                 };
 333                 opp@400000000 {
 334                         opp-hz = /bits/ 64 <400000000>;
 335                         opp-microvolt = <1050000>;
 336                 };
 337         };
 338
 339         bus_acp_opp_table: opp_table2 {
 340                 compatible = "operating-points-v2";
 341                 opp-shared;
 342
 343                 opp@100000000 {
 344                         opp-hz = /bits/ 64 <100000000>;
 345                 };
 346                 opp@134000000 {
 347                         opp-hz = /bits/ 64 <134000000>;
 348                 };
 349                 opp@160000000 {
 350                         opp-hz = /bits/ 64 <160000000>;
 351                 };
 352                 opp@267000000 {
 353                         opp-hz = /bits/ 64 <267000000>;
 354                 };
 355         };
 356
 357         bus_leftbus: bus_leftbus {
 358                 compatible = "samsung,exynos-bus";
 359                 clocks = <&clock CLK_DIV_GDL>;
 360                 clock-names = "bus";
 361                 operating-points-v2 = <&bus_leftbus_opp_table>;
 362                 status = "disabled";
 363         };
 364
 365         bus_rightbus: bus_rightbus {
 366                 compatible = "samsung,exynos-bus";
 367                 clocks = <&clock CLK_DIV_GDR>;
 368                 clock-names = "bus";
 369                 operating-points-v2 = <&bus_leftbus_opp_table>;
 370                 status = "disabled";
 371         };
 372
 373         bus_display: bus_display {
 374                 compatible = "samsung,exynos-bus";
 375                 clocks = <&clock CLK_ACLK160>;
 376                 clock-names = "bus";
 377                 operating-points-v2 = <&bus_display_opp_table>;
 378                 status = "disabled";
 379         };
 380
 381         bus_fsys: bus_fsys {
 382                 compatible = "samsung,exynos-bus";
 383                 clocks = <&clock CLK_ACLK133>;
 384                 clock-names = "bus";
 385                 operating-points-v2 = <&bus_fsys_opp_table>;
 386                 status = "disabled";
 387         };
 388
 389         bus_peri: bus_peri {
 390                 compatible = "samsung,exynos-bus";
 391                 clocks = <&clock CLK_ACLK100>;
 392                 clock-names = "bus";
 393                 operating-points-v2 = <&bus_peri_opp_table>;
 394                 status = "disabled";
 395         };
 396
 397         bus_mfc: bus_mfc {
 398                 compatible = "samsung,exynos-bus";
 399                 clocks = <&clock CLK_SCLK_MFC>;
 400                 clock-names = "bus";
 401                 operating-points-v2 = <&bus_leftbus_opp_table>;
 402                 status = "disabled";
 403         };
 404
 405         bus_leftbus_opp_table: opp_table3 {
 406                 compatible = "operating-points-v2";
 407                 opp-shared;
 408
 409                 opp@100000000 {
 410                         opp-hz = /bits/ 64 <100000000>;
 411                         opp-microvolt = <900000>;
 412                 };
 413                 opp@134000000 {
 414                         opp-hz = /bits/ 64 <134000000>;
 415                         opp-microvolt = <925000>;
 416                 };
 417                 opp@160000000 {
 418                         opp-hz = /bits/ 64 <160000000>;
 419                         opp-microvolt = <950000>;
 420                 };
 421                 opp@200000000 {
 422                         opp-hz = /bits/ 64 <200000000>;
 423                         opp-microvolt = <1000000>;
 424                 };
 425         };
 426
 427         bus_display_opp_table: opp_table4 {
 428                 compatible = "operating-points-v2";
 429                 opp-shared;
 430
 431                 opp@160000000 {
 432                         opp-hz = /bits/ 64 <160000000>;
 433                 };
 434                 opp@200000000 {
 435                         opp-hz = /bits/ 64 <200000000>;
 436                 };
 437         };
 438
 439         bus_fsys_opp_table: opp_table5 {
 440                 compatible = "operating-points-v2";
 441                 opp-shared;
 442
 443                 opp@100000000 {
 444                         opp-hz = /bits/ 64 <100000000>;
 445                 };
 446                 opp@134000000 {
 447                         opp-hz = /bits/ 64 <134000000>;
 448                 };
 449         };
 450
 451         bus_peri_opp_table: opp_table6 {
 452                 compatible = "operating-points-v2";
 453                 opp-shared;
 454
 455                 opp@50000000 {
 456                         opp-hz = /bits/ 64 <50000000>;
 457                 };
 458                 opp@100000000 {
 459                         opp-hz = /bits/ 64 <100000000>;
 460                 };
 461         };
 462 };
 463
 464 &combiner {
 465         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 466                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 467                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 468                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 469                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 470                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 471                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 472                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 473                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 474                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 475                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 476                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 477                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 478                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 479                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 480                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 481                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 482                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 483                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 484                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 485 };
 486
 487 &exynos_usbphy {
 488         compatible = "samsung,exynos4x12-usb2-phy";
 489         samsung,sysreg-phandle = <&sys_reg>;
 490 };
 491
 492 &fimc_0 {
 493         compatible = "samsung,exynos4212-fimc";
 494         samsung,pix-limits = <4224 8192 1920 4224>;
 495         samsung,mainscaler-ext;
 496         samsung,isp-wb;
 497         samsung,cam-if;
 498 };
 499
 500 &fimc_1 {
 501         compatible = "samsung,exynos4212-fimc";
 502         samsung,pix-limits = <4224 8192 1920 4224>;
 503         samsung,mainscaler-ext;
 504         samsung,isp-wb;
 505         samsung,cam-if;
 506 };
 507
 508 &fimc_2 {
 509         compatible = "samsung,exynos4212-fimc";
 510         samsung,pix-limits = <4224 8192 1920 4224>;
 511         samsung,mainscaler-ext;
 512         samsung,isp-wb;
 513         samsung,lcd-wb;
 514         samsung,cam-if;
 515 };
 516
 517 &fimc_3 {
 518         compatible = "samsung,exynos4212-fimc";
 519         samsung,pix-limits = <1920 8192 1366 1920>;
 520         samsung,rotators = <0>;
 521         samsung,mainscaler-ext;
 522         samsung,isp-wb;
 523         samsung,lcd-wb;
 524 };
 525
 526 &hdmi {
 527         compatible = "samsung,exynos4212-hdmi";
 528 };
 529
 530 &jpeg_codec {
 531         compatible = "samsung,exynos4212-jpeg";
 532 };
 533
 534 &rotator {
 535         compatible = "samsung,exynos4212-rotator";
 536 };
 537
 538 &mixer {
 539         compatible = "samsung,exynos4212-mixer";
 540         clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
 541         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 542                  <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
 543 };
 544
 545 &pinctrl_0 {
 546         compatible = "samsung,exynos4x12-pinctrl";
 547         reg = <0x11400000 0x1000>;
 548         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 549 };
 550
 551 &pinctrl_1 {
 552         compatible = "samsung,exynos4x12-pinctrl";
 553         reg = <0x11000000 0x1000>;
 554         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 555
 556         wakup_eint: wakeup-interrupt-controller {
 557                 compatible = "samsung,exynos4210-wakeup-eint";
 558                 interrupt-parent = <&gic>;
 559                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 560         };
 561 };
 562
 563 &pinctrl_2 {
 564         compatible = "samsung,exynos4x12-pinctrl";
 565         reg = <0x03860000 0x1000>;
 566         interrupt-parent = <&combiner>;
 567         interrupts = <10 0>;
 568 };
 569
 570 &pinctrl_3 {
 571         compatible = "samsung,exynos4x12-pinctrl";
 572         reg = <0x106E0000 0x1000>;
 573         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 574 };
 575
 576 &pmu_system_controller {
 577         compatible = "samsung,exynos4212-pmu", "syscon";
 578         clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
 579                         "clkout4", "clkout8", "clkout9";
 580         clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
 581                 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
 582                 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
 583         #clock-cells = <1>;
 584 };
 585
 586 &tmu {
 587         compatible = "samsung,exynos4412-tmu";
 588         interrupt-parent = <&combiner>;
 589         interrupts = <2 4>;
 590         reg = <0x100C0000 0x100>;
 591         clocks = <&clock 383>;
 592         clock-names = "tmu_apbif";
 593         status = "disabled";
 594 };