arch/arm/boot/dts/exynos5250.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS5250 SoC device tree source
   4  *
   5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   9  * EXYNOS5250 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  14  * additional nodes can be added to this file.
  15  */
  16
  17 #include <dt-bindings/clock/exynos5250.h>
  18 #include "exynos5.dtsi"
  19 #include "exynos4-cpu-thermal.dtsi"
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5250", "samsung,exynos5";
  24
  25         aliases {
  26                 spi0 = &spi_0;
  27                 spi1 = &spi_1;
  28                 spi2 = &spi_2;
  29                 gsc0 = &gsc_0;
  30                 gsc1 = &gsc_1;
  31                 gsc2 = &gsc_2;
  32                 gsc3 = &gsc_3;
  33                 mshc0 = &mmc_0;
  34                 mshc1 = &mmc_1;
  35                 mshc2 = &mmc_2;
  36                 mshc3 = &mmc_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 i2c9 = &i2c_9;
  43                 pinctrl0 = &pinctrl_0;
  44                 pinctrl1 = &pinctrl_1;
  45                 pinctrl2 = &pinctrl_2;
  46                 pinctrl3 = &pinctrl_3;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu0: cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a15";
  56                         reg = <0>;
  57                         clock-frequency = <1700000000>;
  58                         clocks = <&clock CLK_ARM_CLK>;
  59                         clock-names = "cpu";
  60                         clock-latency = <140000>;
  61
  62                         operating-points = <
  63                                 1700000 1300000
  64                                 1600000 1250000
  65                                 1500000 1225000
  66                                 1400000 1200000
  67                                 1300000 1150000
  68                                 1200000 1125000
  69                                 1100000 1100000
  70                                 1000000 1075000
  71                                  900000 1050000
  72                                  800000 1025000
  73                                  700000 1012500
  74                                  600000 1000000
  75                                  500000  975000
  76                                  400000  950000
  77                                  300000  937500
  78                                  200000  925000
  79                         >;
  80                         #cooling-cells = <2>; /* min followed by max */
  81                 };
  82                 cpu@1 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a15";
  85                         reg = <1>;
  86                         clock-frequency = <1700000000>;
  87                 };
  88         };
  89
  90         soc: soc {
  91                 sysram@2020000 {
  92                         compatible = "mmio-sram";
  93                         reg = <0x02020000 0x30000>;
  94                         #address-cells = <1>;
  95                         #size-cells = <1>;
  96                         ranges = <0 0x02020000 0x30000>;
  97
  98                         smp-sysram@0 {
  99                                 compatible = "samsung,exynos4210-sysram";
 100                                 reg = <0x0 0x1000>;
 101                         };
 102
 103                         smp-sysram@2f000 {
 104                                 compatible = "samsung,exynos4210-sysram-ns";
 105                                 reg = <0x2f000 0x1000>;
 106                         };
 107                 };
 108
 109                 pd_gsc: power-domain@10044000 {
 110                         compatible = "samsung,exynos4210-pd";
 111                         reg = <0x10044000 0x20>;
 112                         #power-domain-cells = <0>;
 113                         label = "GSC";
 114                 };
 115
 116                 pd_mfc: power-domain@10044040 {
 117                         compatible = "samsung,exynos4210-pd";
 118                         reg = <0x10044040 0x20>;
 119                         #power-domain-cells = <0>;
 120                         label = "MFC";
 121                 };
 122
 123                 pd_g3d: power-domain@10044060 {
 124                         compatible = "samsung,exynos4210-pd";
 125                         reg = <0x10044060 0x20>;
 126                         #power-domain-cells = <0>;
 127                         label = "G3D";
 128                 };
 129
 130                 pd_disp1: power-domain@100440a0 {
 131                         compatible = "samsung,exynos4210-pd";
 132                         reg = <0x100440A0 0x20>;
 133                         #power-domain-cells = <0>;
 134                         label = "DISP1";
 135                 };
 136
 137                 pd_mau: power-domain@100440c0 {
 138                         compatible = "samsung,exynos4210-pd";
 139                         reg = <0x100440C0 0x20>;
 140                         #power-domain-cells = <0>;
 141                         label = "MAU";
 142                 };
 143
 144                 clock: clock-controller@10010000 {
 145                         compatible = "samsung,exynos5250-clock";
 146                         reg = <0x10010000 0x30000>;
 147                         #clock-cells = <1>;
 148                 };
 149
 150                 clock_audss: audss-clock-controller@3810000 {
 151                         compatible = "samsung,exynos5250-audss-clock";
 152                         reg = <0x03810000 0x0C>;
 153                         #clock-cells = <1>;
 154                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 155                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 156                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 157                         power-domains = <&pd_mau>;
 158                 };
 159
 160                 timer {
 161                         compatible = "arm,armv7-timer";
 162                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 163                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 164                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 165                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 166                         /*
 167                          * Unfortunately we need this since some versions
 168                          * of U-Boot on Exynos don't set the CNTFRQ register,
 169                          * so we need the value from DT.
 170                          */
 171                         clock-frequency = <24000000>;
 172                 };
 173
 174                 mct@101c0000 {
 175                         compatible = "samsung,exynos4210-mct";
 176                         reg = <0x101C0000 0x800>;
 177                         interrupt-controller;
 178                         #interrupt-cells = <2>;
 179                         interrupt-parent = <&mct_map>;
 180                         interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 181                                      <4 0>, <5 0>;
 182                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 183                         clock-names = "fin_pll", "mct";
 184
 185                         mct_map: mct-map {
 186                                 #interrupt-cells = <2>;
 187                                 #address-cells = <0>;
 188                                 #size-cells = <0>;
 189                                 interrupt-map = <0x0 0 &combiner 23 3>,
 190                                                 <0x1 0 &combiner 23 4>,
 191                                                 <0x2 0 &combiner 25 2>,
 192                                                 <0x3 0 &combiner 25 3>,
 193                                                 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
 194                                                 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
 195                         };
 196                 };
 197
 198                 pmu {
 199                         compatible = "arm,cortex-a15-pmu";
 200                         interrupt-parent = <&combiner>;
 201                         interrupts = <1 2>, <22 4>;
 202                 };
 203
 204                 pinctrl_0: pinctrl@11400000 {
 205                         compatible = "samsung,exynos5250-pinctrl";
 206                         reg = <0x11400000 0x1000>;
 207                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 208
 209                         wakup_eint: wakeup-interrupt-controller {
 210                                 compatible = "samsung,exynos4210-wakeup-eint";
 211                                 interrupt-parent = <&gic>;
 212                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 213                         };
 214                 };
 215
 216                 pinctrl_1: pinctrl@13400000 {
 217                         compatible = "samsung,exynos5250-pinctrl";
 218                         reg = <0x13400000 0x1000>;
 219                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 220                 };
 221
 222                 pinctrl_2: pinctrl@10d10000 {
 223                         compatible = "samsung,exynos5250-pinctrl";
 224                         reg = <0x10d10000 0x1000>;
 225                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 226                 };
 227
 228                 pinctrl_3: pinctrl@3860000 {
 229                         compatible = "samsung,exynos5250-pinctrl";
 230                         reg = <0x03860000 0x1000>;
 231                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 232                         power-domains = <&pd_mau>;
 233                 };
 234
 235                 pmu_system_controller: system-controller@10040000 {
 236                         compatible = "samsung,exynos5250-pmu", "syscon";
 237                         reg = <0x10040000 0x5000>;
 238                         clock-names = "clkout16";
 239                         clocks = <&clock CLK_FIN_PLL>;
 240                         #clock-cells = <1>;
 241                         interrupt-controller;
 242                         #interrupt-cells = <3>;
 243                         interrupt-parent = <&gic>;
 244                 };
 245
 246                 watchdog@101d0000 {
 247                         compatible = "samsung,exynos5250-wdt";
 248                         reg = <0x101D0000 0x100>;
 249                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&clock CLK_WDT>;
 251                         clock-names = "watchdog";
 252                         samsung,syscon-phandle = <&pmu_system_controller>;
 253                 };
 254
 255                 mfc: codec@11000000 {
 256                         compatible = "samsung,mfc-v6";
 257                         reg = <0x11000000 0x10000>;
 258                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 259                         power-domains = <&pd_mfc>;
 260                         clocks = <&clock CLK_MFC>;
 261                         clock-names = "mfc";
 262                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 263                         iommu-names = "left", "right";
 264                 };
 265
 266                 rotator: rotator@11c00000 {
 267                         compatible = "samsung,exynos5250-rotator";
 268                         reg = <0x11C00000 0x64>;
 269                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 270                         clocks = <&clock CLK_ROTATOR>;
 271                         clock-names = "rotator";
 272                         iommus = <&sysmmu_rotator>;
 273                 };
 274
 275                 tmu: tmu@10060000 {
 276                         compatible = "samsung,exynos5250-tmu";
 277                         reg = <0x10060000 0x100>;
 278                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&clock CLK_TMU>;
 280                         clock-names = "tmu_apbif";
 281                         #include "exynos4412-tmu-sensor-conf.dtsi"
 282                 };
 283
 284                 sata: sata@122f0000 {
 285                         compatible = "snps,dwc-ahci";
 286                         samsung,sata-freq = <66>;
 287                         reg = <0x122F0000 0x1ff>;
 288                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 289                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 290                         clock-names = "sata", "sclk_sata";
 291                         phys = <&sata_phy>;
 292                         phy-names = "sata-phy";
 293                         status = "disabled";
 294                 };
 295
 296                 sata_phy: sata-phy@12170000 {
 297                         compatible = "samsung,exynos5250-sata-phy";
 298                         reg = <0x12170000 0x1ff>;
 299                         clocks = <&clock CLK_SATA_PHYCTRL>;
 300                         clock-names = "sata_phyctrl";
 301                         #phy-cells = <0>;
 302                         samsung,syscon-phandle = <&pmu_system_controller>;
 303                         status = "disabled";
 304                 };
 305
 306                 /* i2c_0-3 are defined in exynos5.dtsi */
 307                 i2c_4: i2c@12ca0000 {
 308                         compatible = "samsung,s3c2440-i2c";
 309                         reg = <0x12CA0000 0x100>;
 310                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         clocks = <&clock CLK_I2C4>;
 314                         clock-names = "i2c";
 315                         pinctrl-names = "default";
 316                         pinctrl-0 = <&i2c4_bus>;
 317                         status = "disabled";
 318                 };
 319
 320                 i2c_5: i2c@12cb0000 {
 321                         compatible = "samsung,s3c2440-i2c";
 322                         reg = <0x12CB0000 0x100>;
 323                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                         clocks = <&clock CLK_I2C5>;
 327                         clock-names = "i2c";
 328                         pinctrl-names = "default";
 329                         pinctrl-0 = <&i2c5_bus>;
 330                         status = "disabled";
 331                 };
 332
 333                 i2c_6: i2c@12cc0000 {
 334                         compatible = "samsung,s3c2440-i2c";
 335                         reg = <0x12CC0000 0x100>;
 336                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                         clocks = <&clock CLK_I2C6>;
 340                         clock-names = "i2c";
 341                         pinctrl-names = "default";
 342                         pinctrl-0 = <&i2c6_bus>;
 343                         status = "disabled";
 344                 };
 345
 346                 i2c_7: i2c@12cd0000 {
 347                         compatible = "samsung,s3c2440-i2c";
 348                         reg = <0x12CD0000 0x100>;
 349                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         clocks = <&clock CLK_I2C7>;
 353                         clock-names = "i2c";
 354                         pinctrl-names = "default";
 355                         pinctrl-0 = <&i2c7_bus>;
 356                         status = "disabled";
 357                 };
 358
 359                 i2c_8: i2c@12ce0000 {
 360                         compatible = "samsung,s3c2440-hdmiphy-i2c";
 361                         reg = <0x12CE0000 0x1000>;
 362                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         clocks = <&clock CLK_I2C_HDMI>;
 366                         clock-names = "i2c";
 367                         status = "disabled";
 368
 369                         hdmiphy: hdmiphy@38 {
 370                                 compatible = "samsung,exynos4212-hdmiphy";
 371                                 reg = <0x38>;
 372                         };
 373                 };
 374
 375                 i2c_9: i2c@121d0000 {
 376                         compatible = "samsung,exynos5-sata-phy-i2c";
 377                         reg = <0x121D0000 0x100>;
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         clocks = <&clock CLK_SATA_PHYI2C>;
 381                         clock-names = "i2c";
 382                         status = "disabled";
 383                 };
 384
 385                 spi_0: spi@12d20000 {
 386                         compatible = "samsung,exynos4210-spi";
 387                         status = "disabled";
 388                         reg = <0x12d20000 0x100>;
 389                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 390                         dmas = <&pdma0 5
 391                                 &pdma0 4>;
 392                         dma-names = "tx", "rx";
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 396                         clock-names = "spi", "spi_busclk0";
 397                         pinctrl-names = "default";
 398                         pinctrl-0 = <&spi0_bus>;
 399                 };
 400
 401                 spi_1: spi@12d30000 {
 402                         compatible = "samsung,exynos4210-spi";
 403                         status = "disabled";
 404                         reg = <0x12d30000 0x100>;
 405                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 406                         dmas = <&pdma1 5
 407                                 &pdma1 4>;
 408                         dma-names = "tx", "rx";
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 412                         clock-names = "spi", "spi_busclk0";
 413                         pinctrl-names = "default";
 414                         pinctrl-0 = <&spi1_bus>;
 415                 };
 416
 417                 spi_2: spi@12d40000 {
 418                         compatible = "samsung,exynos4210-spi";
 419                         status = "disabled";
 420                         reg = <0x12d40000 0x100>;
 421                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 422                         dmas = <&pdma0 7
 423                                 &pdma0 6>;
 424                         dma-names = "tx", "rx";
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 428                         clock-names = "spi", "spi_busclk0";
 429                         pinctrl-names = "default";
 430                         pinctrl-0 = <&spi2_bus>;
 431                 };
 432
 433                 mmc_0: mmc@12200000 {
 434                         compatible = "samsung,exynos5250-dw-mshc";
 435                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         reg = <0x12200000 0x1000>;
 439                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 440                         clock-names = "biu", "ciu";
 441                         fifo-depth = <0x80>;
 442                         status = "disabled";
 443                 };
 444
 445                 mmc_1: mmc@12210000 {
 446                         compatible = "samsung,exynos5250-dw-mshc";
 447                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         reg = <0x12210000 0x1000>;
 451                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 452                         clock-names = "biu", "ciu";
 453                         fifo-depth = <0x80>;
 454                         status = "disabled";
 455                 };
 456
 457                 mmc_2: mmc@12220000 {
 458                         compatible = "samsung,exynos5250-dw-mshc";
 459                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         reg = <0x12220000 0x1000>;
 463                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 464                         clock-names = "biu", "ciu";
 465                         fifo-depth = <0x80>;
 466                         status = "disabled";
 467                 };
 468
 469                 mmc_3: mmc@12230000 {
 470                         compatible = "samsung,exynos5250-dw-mshc";
 471                         reg = <0x12230000 0x1000>;
 472                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 476                         clock-names = "biu", "ciu";
 477                         fifo-depth = <0x80>;
 478                         status = "disabled";
 479                 };
 480
 481                 i2s0: i2s@3830000 {
 482                         compatible = "samsung,s5pv210-i2s";
 483                         status = "disabled";
 484                         reg = <0x03830000 0x100>;
 485                         dmas = <&pdma0 10
 486                                 &pdma0 9
 487                                 &pdma0 8>;
 488                         dma-names = "tx", "rx", "tx-sec";
 489                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 490                                 <&clock_audss EXYNOS_I2S_BUS>,
 491                                 <&clock_audss EXYNOS_SCLK_I2S>;
 492                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 493                         samsung,idma-addr = <0x03000000>;
 494                         pinctrl-names = "default";
 495                         pinctrl-0 = <&i2s0_bus>;
 496                         power-domains = <&pd_mau>;
 497                         #clock-cells = <1>;
 498                         #sound-dai-cells = <1>;
 499                 };
 500
 501                 i2s1: i2s@12d60000 {
 502                         compatible = "samsung,s3c6410-i2s";
 503                         status = "disabled";
 504                         reg = <0x12D60000 0x100>;
 505                         dmas = <&pdma1 12
 506                                 &pdma1 11>;
 507                         dma-names = "tx", "rx";
 508                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 509                         clock-names = "iis", "i2s_opclk0";
 510                         pinctrl-names = "default";
 511                         pinctrl-0 = <&i2s1_bus>;
 512                         power-domains = <&pd_mau>;
 513                         #sound-dai-cells = <1>;
 514                 };
 515
 516                 i2s2: i2s@12d70000 {
 517                         compatible = "samsung,s3c6410-i2s";
 518                         status = "disabled";
 519                         reg = <0x12D70000 0x100>;
 520                         dmas = <&pdma0 12
 521                                 &pdma0 11>;
 522                         dma-names = "tx", "rx";
 523                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 524                         clock-names = "iis", "i2s_opclk0";
 525                         pinctrl-names = "default";
 526                         pinctrl-0 = <&i2s2_bus>;
 527                         power-domains = <&pd_mau>;
 528                         #sound-dai-cells = <1>;
 529                 };
 530
 531                 usb_dwc3 {
 532                         compatible = "samsung,exynos5250-dwusb3";
 533                         clocks = <&clock CLK_USB3>;
 534                         clock-names = "usbdrd30";
 535                         #address-cells = <1>;
 536                         #size-cells = <1>;
 537                         ranges;
 538
 539                         usbdrd_dwc3: dwc3@12000000 {
 540                                 compatible = "synopsys,dwc3";
 541                                 reg = <0x12000000 0x10000>;
 542                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 543                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 544                                 phy-names = "usb2-phy", "usb3-phy";
 545                         };
 546                 };
 547
 548                 usbdrd_phy: phy@12100000 {
 549                         compatible = "samsung,exynos5250-usbdrd-phy";
 550                         reg = <0x12100000 0x100>;
 551                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 552                         clock-names = "phy", "ref";
 553                         samsung,pmu-syscon = <&pmu_system_controller>;
 554                         #phy-cells = <1>;
 555                 };
 556
 557                 ehci: usb@12110000 {
 558                         compatible = "samsung,exynos4210-ehci";
 559                         reg = <0x12110000 0x100>;
 560                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 561
 562                         clocks = <&clock CLK_USB2>;
 563                         clock-names = "usbhost";
 564                         #address-cells = <1>;
 565                         #size-cells = <0>;
 566                         port@0 {
 567                                 reg = <0>;
 568                                 phys = <&usb2_phy_gen 1>;
 569                         };
 570                 };
 571
 572                 ohci: usb@12120000 {
 573                         compatible = "samsung,exynos4210-ohci";
 574                         reg = <0x12120000 0x100>;
 575                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 576
 577                         clocks = <&clock CLK_USB2>;
 578                         clock-names = "usbhost";
 579                         #address-cells = <1>;
 580                         #size-cells = <0>;
 581                         port@0 {
 582                                 reg = <0>;
 583                                 phys = <&usb2_phy_gen 1>;
 584                         };
 585                 };
 586
 587                 usb2_phy_gen: phy@12130000 {
 588                         compatible = "samsung,exynos5250-usb2-phy";
 589                         reg = <0x12130000 0x100>;
 590                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 591                         clock-names = "phy", "ref";
 592                         #phy-cells = <1>;
 593                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 594                         samsung,pmureg-phandle = <&pmu_system_controller>;
 595                 };
 596
 597                 amba {
 598                         #address-cells = <1>;
 599                         #size-cells = <1>;
 600                         compatible = "simple-bus";
 601                         interrupt-parent = <&gic>;
 602                         ranges;
 603
 604                         pdma0: pdma@121a0000 {
 605                                 compatible = "arm,pl330", "arm,primecell";
 606                                 reg = <0x121A0000 0x1000>;
 607                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 608                                 clocks = <&clock CLK_PDMA0>;
 609                                 clock-names = "apb_pclk";
 610                                 #dma-cells = <1>;
 611                                 #dma-channels = <8>;
 612                                 #dma-requests = <32>;
 613                         };
 614
 615                         pdma1: pdma@121b0000 {
 616                                 compatible = "arm,pl330", "arm,primecell";
 617                                 reg = <0x121B0000 0x1000>;
 618                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 619                                 clocks = <&clock CLK_PDMA1>;
 620                                 clock-names = "apb_pclk";
 621                                 #dma-cells = <1>;
 622                                 #dma-channels = <8>;
 623                                 #dma-requests = <32>;
 624                         };
 625
 626                         mdma0: mdma@10800000 {
 627                                 compatible = "arm,pl330", "arm,primecell";
 628                                 reg = <0x10800000 0x1000>;
 629                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 630                                 clocks = <&clock CLK_MDMA0>;
 631                                 clock-names = "apb_pclk";
 632                                 #dma-cells = <1>;
 633                                 #dma-channels = <8>;
 634                                 #dma-requests = <1>;
 635                         };
 636
 637                         mdma1: mdma@11c10000 {
 638                                 compatible = "arm,pl330", "arm,primecell";
 639                                 reg = <0x11C10000 0x1000>;
 640                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 641                                 clocks = <&clock CLK_MDMA1>;
 642                                 clock-names = "apb_pclk";
 643                                 #dma-cells = <1>;
 644                                 #dma-channels = <8>;
 645                                 #dma-requests = <1>;
 646                         };
 647                 };
 648
 649                 gsc_0:  gsc@13e00000 {
 650                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 651                         reg = <0x13e00000 0x1000>;
 652                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 653                         power-domains = <&pd_gsc>;
 654                         clocks = <&clock CLK_GSCL0>;
 655                         clock-names = "gscl";
 656                         iommus = <&sysmmu_gsc0>;
 657                 };
 658
 659                 gsc_1:  gsc@13e10000 {
 660                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 661                         reg = <0x13e10000 0x1000>;
 662                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 663                         power-domains = <&pd_gsc>;
 664                         clocks = <&clock CLK_GSCL1>;
 665                         clock-names = "gscl";
 666                         iommus = <&sysmmu_gsc1>;
 667                 };
 668
 669                 gsc_2:  gsc@13e20000 {
 670                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 671                         reg = <0x13e20000 0x1000>;
 672                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 673                         power-domains = <&pd_gsc>;
 674                         clocks = <&clock CLK_GSCL2>;
 675                         clock-names = "gscl";
 676                         iommus = <&sysmmu_gsc2>;
 677                 };
 678
 679                 gsc_3:  gsc@13e30000 {
 680                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 681                         reg = <0x13e30000 0x1000>;
 682                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 683                         power-domains = <&pd_gsc>;
 684                         clocks = <&clock CLK_GSCL3>;
 685                         clock-names = "gscl";
 686                         iommus = <&sysmmu_gsc3>;
 687                 };
 688
 689                 hdmi: hdmi@14530000 {
 690                         compatible = "samsung,exynos4212-hdmi";
 691                         reg = <0x14530000 0x70000>;
 692                         power-domains = <&pd_disp1>;
 693                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 694                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 695                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 696                                  <&clock CLK_MOUT_HDMI>;
 697                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 698                                         "sclk_hdmiphy", "mout_hdmi";
 699                         samsung,syscon-phandle = <&pmu_system_controller>;
 700                         phy = <&hdmiphy>;
 701                         #sound-dai-cells = <0>;
 702                         status = "disabled";
 703                 };
 704
 705                 hdmicec: cec@101b0000 {
 706                         compatible = "samsung,s5p-cec";
 707                         reg = <0x101B0000 0x200>;
 708                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&clock CLK_HDMI_CEC>;
 710                         clock-names = "hdmicec";
 711                         samsung,syscon-phandle = <&pmu_system_controller>;
 712                         hdmi-phandle = <&hdmi>;
 713                         pinctrl-names = "default";
 714                         pinctrl-0 = <&hdmi_cec>;
 715                         status = "disabled";
 716                 };
 717
 718                 mixer: mixer@14450000 {
 719                         compatible = "samsung,exynos5250-mixer";
 720                         reg = <0x14450000 0x10000>;
 721                         power-domains = <&pd_disp1>;
 722                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 723                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 724                                  <&clock CLK_SCLK_HDMI>;
 725                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 726                         iommus = <&sysmmu_tv>;
 727                         status = "disabled";
 728                 };
 729
 730                 dp_phy: video-phy {
 731                         compatible = "samsung,exynos5250-dp-video-phy";
 732                         samsung,pmu-syscon = <&pmu_system_controller>;
 733                         #phy-cells = <0>;
 734                 };
 735
 736                 adc: adc@12d10000 {
 737                         compatible = "samsung,exynos-adc-v1";
 738                         reg = <0x12D10000 0x100>;
 739                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 740                         clocks = <&clock CLK_ADC>;
 741                         clock-names = "adc";
 742                         #io-channel-cells = <1>;
 743                         io-channel-ranges;
 744                         samsung,syscon-phandle = <&pmu_system_controller>;
 745                         status = "disabled";
 746                 };
 747
 748                 sysmmu_g2d: sysmmu@10a60000 {
 749                         compatible = "samsung,exynos-sysmmu";
 750                         reg = <0x10A60000 0x1000>;
 751                         interrupt-parent = <&combiner>;
 752                         interrupts = <24 5>;
 753                         clock-names = "sysmmu", "master";
 754                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
 755                         #iommu-cells = <0>;
 756                 };
 757
 758                 sysmmu_mfc_r: sysmmu@11200000 {
 759                         compatible = "samsung,exynos-sysmmu";
 760                         reg = <0x11200000 0x1000>;
 761                         interrupt-parent = <&combiner>;
 762                         interrupts = <6 2>;
 763                         power-domains = <&pd_mfc>;
 764                         clock-names = "sysmmu", "master";
 765                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 766                         #iommu-cells = <0>;
 767                 };
 768
 769                 sysmmu_mfc_l: sysmmu@11210000 {
 770                         compatible = "samsung,exynos-sysmmu";
 771                         reg = <0x11210000 0x1000>;
 772                         interrupt-parent = <&combiner>;
 773                         interrupts = <8 5>;
 774                         power-domains = <&pd_mfc>;
 775                         clock-names = "sysmmu", "master";
 776                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 777                         #iommu-cells = <0>;
 778                 };
 779
 780                 sysmmu_rotator: sysmmu@11d40000 {
 781                         compatible = "samsung,exynos-sysmmu";
 782                         reg = <0x11D40000 0x1000>;
 783                         interrupt-parent = <&combiner>;
 784                         interrupts = <4 0>;
 785                         clock-names = "sysmmu", "master";
 786                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 787                         #iommu-cells = <0>;
 788                 };
 789
 790                 sysmmu_jpeg: sysmmu@11f20000 {
 791                         compatible = "samsung,exynos-sysmmu";
 792                         reg = <0x11F20000 0x1000>;
 793                         interrupt-parent = <&combiner>;
 794                         interrupts = <4 2>;
 795                         power-domains = <&pd_gsc>;
 796                         clock-names = "sysmmu", "master";
 797                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 798                         #iommu-cells = <0>;
 799                 };
 800
 801                 sysmmu_fimc_isp: sysmmu@13260000 {
 802                         compatible = "samsung,exynos-sysmmu";
 803                         reg = <0x13260000 0x1000>;
 804                         interrupt-parent = <&combiner>;
 805                         interrupts = <10 6>;
 806                         clock-names = "sysmmu";
 807                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
 808                         #iommu-cells = <0>;
 809                 };
 810
 811                 sysmmu_fimc_drc: sysmmu@13270000 {
 812                         compatible = "samsung,exynos-sysmmu";
 813                         reg = <0x13270000 0x1000>;
 814                         interrupt-parent = <&combiner>;
 815                         interrupts = <11 6>;
 816                         clock-names = "sysmmu";
 817                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
 818                         #iommu-cells = <0>;
 819                 };
 820
 821                 sysmmu_fimc_fd: sysmmu@132a0000 {
 822                         compatible = "samsung,exynos-sysmmu";
 823                         reg = <0x132A0000 0x1000>;
 824                         interrupt-parent = <&combiner>;
 825                         interrupts = <5 0>;
 826                         clock-names = "sysmmu";
 827                         clocks = <&clock CLK_SMMU_FIMC_FD>;
 828                         #iommu-cells = <0>;
 829                 };
 830
 831                 sysmmu_fimc_scc: sysmmu@13280000 {
 832                         compatible = "samsung,exynos-sysmmu";
 833                         reg = <0x13280000 0x1000>;
 834                         interrupt-parent = <&combiner>;
 835                         interrupts = <5 2>;
 836                         clock-names = "sysmmu";
 837                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
 838                         #iommu-cells = <0>;
 839                 };
 840
 841                 sysmmu_fimc_scp: sysmmu@13290000 {
 842                         compatible = "samsung,exynos-sysmmu";
 843                         reg = <0x13290000 0x1000>;
 844                         interrupt-parent = <&combiner>;
 845                         interrupts = <3 6>;
 846                         clock-names = "sysmmu";
 847                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
 848                         #iommu-cells = <0>;
 849                 };
 850
 851                 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
 852                         compatible = "samsung,exynos-sysmmu";
 853                         reg = <0x132B0000 0x1000>;
 854                         interrupt-parent = <&combiner>;
 855                         interrupts = <5 4>;
 856                         clock-names = "sysmmu";
 857                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
 858                         #iommu-cells = <0>;
 859                 };
 860
 861                 sysmmu_fimc_odc: sysmmu@132c0000 {
 862                         compatible = "samsung,exynos-sysmmu";
 863                         reg = <0x132C0000 0x1000>;
 864                         interrupt-parent = <&combiner>;
 865                         interrupts = <11 0>;
 866                         clock-names = "sysmmu";
 867                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
 868                         #iommu-cells = <0>;
 869                 };
 870
 871                 sysmmu_fimc_dis0: sysmmu@132d0000 {
 872                         compatible = "samsung,exynos-sysmmu";
 873                         reg = <0x132D0000 0x1000>;
 874                         interrupt-parent = <&combiner>;
 875                         interrupts = <10 4>;
 876                         clock-names = "sysmmu";
 877                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
 878                         #iommu-cells = <0>;
 879                 };
 880
 881                 sysmmu_fimc_dis1: sysmmu@132e0000 {
 882                         compatible = "samsung,exynos-sysmmu";
 883                         reg = <0x132E0000 0x1000>;
 884                         interrupt-parent = <&combiner>;
 885                         interrupts = <9 4>;
 886                         clock-names = "sysmmu";
 887                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
 888                         #iommu-cells = <0>;
 889                 };
 890
 891                 sysmmu_fimc_3dnr: sysmmu@132f0000 {
 892                         compatible = "samsung,exynos-sysmmu";
 893                         reg = <0x132F0000 0x1000>;
 894                         interrupt-parent = <&combiner>;
 895                         interrupts = <5 6>;
 896                         clock-names = "sysmmu";
 897                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
 898                         #iommu-cells = <0>;
 899                 };
 900
 901                 sysmmu_fimc_lite0: sysmmu@13c40000 {
 902                         compatible = "samsung,exynos-sysmmu";
 903                         reg = <0x13C40000 0x1000>;
 904                         interrupt-parent = <&combiner>;
 905                         interrupts = <3 4>;
 906                         power-domains = <&pd_gsc>;
 907                         clock-names = "sysmmu", "master";
 908                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
 909                         #iommu-cells = <0>;
 910                 };
 911
 912                 sysmmu_fimc_lite1: sysmmu@13c50000 {
 913                         compatible = "samsung,exynos-sysmmu";
 914                         reg = <0x13C50000 0x1000>;
 915                         interrupt-parent = <&combiner>;
 916                         interrupts = <24 1>;
 917                         power-domains = <&pd_gsc>;
 918                         clock-names = "sysmmu", "master";
 919                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
 920                         #iommu-cells = <0>;
 921                 };
 922
 923                 sysmmu_gsc0: sysmmu@13e80000 {
 924                         compatible = "samsung,exynos-sysmmu";
 925                         reg = <0x13E80000 0x1000>;
 926                         interrupt-parent = <&combiner>;
 927                         interrupts = <2 0>;
 928                         power-domains = <&pd_gsc>;
 929                         clock-names = "sysmmu", "master";
 930                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 931                         #iommu-cells = <0>;
 932                 };
 933
 934                 sysmmu_gsc1: sysmmu@13e90000 {
 935                         compatible = "samsung,exynos-sysmmu";
 936                         reg = <0x13E90000 0x1000>;
 937                         interrupt-parent = <&combiner>;
 938                         interrupts = <2 2>;
 939                         power-domains = <&pd_gsc>;
 940                         clock-names = "sysmmu", "master";
 941                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
 942                         #iommu-cells = <0>;
 943                 };
 944
 945                 sysmmu_gsc2: sysmmu@13ea0000 {
 946                         compatible = "samsung,exynos-sysmmu";
 947                         reg = <0x13EA0000 0x1000>;
 948                         interrupt-parent = <&combiner>;
 949                         interrupts = <2 4>;
 950                         power-domains = <&pd_gsc>;
 951                         clock-names = "sysmmu", "master";
 952                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
 953                         #iommu-cells = <0>;
 954                 };
 955
 956                 sysmmu_gsc3: sysmmu@13eb0000 {
 957                         compatible = "samsung,exynos-sysmmu";
 958                         reg = <0x13EB0000 0x1000>;
 959                         interrupt-parent = <&combiner>;
 960                         interrupts = <2 6>;
 961                         power-domains = <&pd_gsc>;
 962                         clock-names = "sysmmu", "master";
 963                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
 964                         #iommu-cells = <0>;
 965                 };
 966
 967                 sysmmu_fimd1: sysmmu@14640000 {
 968                         compatible = "samsung,exynos-sysmmu";
 969                         reg = <0x14640000 0x1000>;
 970                         interrupt-parent = <&combiner>;
 971                         interrupts = <3 2>;
 972                         power-domains = <&pd_disp1>;
 973                         clock-names = "sysmmu", "master";
 974                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
 975                         #iommu-cells = <0>;
 976                 };
 977
 978                 sysmmu_tv: sysmmu@14650000 {
 979                         compatible = "samsung,exynos-sysmmu";
 980                         reg = <0x14650000 0x1000>;
 981                         interrupt-parent = <&combiner>;
 982                         interrupts = <7 4>;
 983                         power-domains = <&pd_disp1>;
 984                         clock-names = "sysmmu", "master";
 985                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 986                         #iommu-cells = <0>;
 987                 };
 988         };
 989
 990         thermal-zones {
 991                 cpu_thermal: cpu-thermal {
 992                         polling-delay-passive = <0>;
 993                         polling-delay = <0>;
 994                         thermal-sensors = <&tmu 0>;
 995
 996                         cooling-maps {
 997                                 map0 {
 998                                      /* Corresponds to 800MHz at freq_table */
 999                                      cooling-device = <&cpu0 9 9>;
1000                                 };
1001                                 map1 {
1002                                      /* Corresponds to 200MHz at freq_table */
1003                                      cooling-device = <&cpu0 15 15>;
1004                                };
1005                        };
1006                 };
1007         };
1008 };
1009
1010 &dp {
1011         power-domains = <&pd_disp1>;
1012         clocks = <&clock CLK_DP>;
1013         clock-names = "dp";
1014         phys = <&dp_phy>;
1015         phy-names = "dp";
1016 };
1017
1018 &fimd {
1019         power-domains = <&pd_disp1>;
1020         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1021         clock-names = "sclk_fimd", "fimd";
1022         iommus = <&sysmmu_fimd1>;
1023 };
1024
1025 &g2d {
1026         iommus = <&sysmmu_g2d>;
1027         clocks = <&clock CLK_G2D>;
1028         clock-names = "fimg2d";
1029         status = "okay";
1030 };
1031
1032 &i2c_0 {
1033         clocks = <&clock CLK_I2C0>;
1034         clock-names = "i2c";
1035         pinctrl-names = "default";
1036         pinctrl-0 = <&i2c0_bus>;
1037 };
1038
1039 &i2c_1 {
1040         clocks = <&clock CLK_I2C1>;
1041         clock-names = "i2c";
1042         pinctrl-names = "default";
1043         pinctrl-0 = <&i2c1_bus>;
1044 };
1045
1046 &i2c_2 {
1047         clocks = <&clock CLK_I2C2>;
1048         clock-names = "i2c";
1049         pinctrl-names = "default";
1050         pinctrl-0 = <&i2c2_bus>;
1051 };
1052
1053 &i2c_3 {
1054         clocks = <&clock CLK_I2C3>;
1055         clock-names = "i2c";
1056         pinctrl-names = "default";
1057         pinctrl-0 = <&i2c3_bus>;
1058 };
1059
1060 &prng {
1061         clocks = <&clock CLK_SSS>;
1062         clock-names = "secss";
1063 };
1064
1065 &pwm {
1066         clocks = <&clock CLK_PWM>;
1067         clock-names = "timers";
1068 };
1069
1070 &rtc {
1071         clocks = <&clock CLK_RTC>;
1072         clock-names = "rtc";
1073         interrupt-parent = <&pmu_system_controller>;
1074         status = "disabled";
1075 };
1076
1077 &serial_0 {
1078         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1079         clock-names = "uart", "clk_uart_baud0";
1080         dmas = <&pdma0 13>, <&pdma0 14>;
1081         dma-names = "rx", "tx";
1082 };
1083
1084 &serial_1 {
1085         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1086         clock-names = "uart", "clk_uart_baud0";
1087         dmas = <&pdma1 15>, <&pdma1 16>;
1088         dma-names = "rx", "tx";
1089 };
1090
1091 &serial_2 {
1092         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1093         clock-names = "uart", "clk_uart_baud0";
1094         dmas = <&pdma0 15>, <&pdma0 16>;
1095         dma-names = "rx", "tx";
1096 };
1097
1098 &serial_3 {
1099         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1100         clock-names = "uart", "clk_uart_baud0";
1101         dmas = <&pdma1 17>, <&pdma1 18>;
1102         dma-names = "rx", "tx";
1103 };
1104
1105 &sss {
1106         clocks = <&clock CLK_SSS>;
1107         clock-names = "secss";
1108 };
1109
1110 &trng {
1111         clocks = <&clock CLK_SSS>;
1112         clock-names = "secss";
1113 };
1114
1115 #include "exynos5250-pinctrl.dtsi"
1116 #include "exynos-syscon-restart.dtsi"