arch/arm/boot/dts/exynos5250.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5250 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   8  * EXYNOS5250 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13  * additional nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include <dt-bindings/clock/exynos5250.h>
  21 #include "exynos5.dtsi"
  22 #include "exynos5250-pinctrl.dtsi"
  23
  24 #include <dt-bindings/clock/exynos-audss-clk.h>
  25
  26 / {
  27         compatible = "samsung,exynos5250", "samsung,exynos5";
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 gsc0 = &gsc_0;
  34                 gsc1 = &gsc_1;
  35                 gsc2 = &gsc_2;
  36                 gsc3 = &gsc_3;
  37                 mshc0 = &mmc_0;
  38                 mshc1 = &mmc_1;
  39                 mshc2 = &mmc_2;
  40                 mshc3 = &mmc_3;
  41                 i2c0 = &i2c_0;
  42                 i2c1 = &i2c_1;
  43                 i2c2 = &i2c_2;
  44                 i2c3 = &i2c_3;
  45                 i2c4 = &i2c_4;
  46                 i2c5 = &i2c_5;
  47                 i2c6 = &i2c_6;
  48                 i2c7 = &i2c_7;
  49                 i2c8 = &i2c_8;
  50                 i2c9 = &i2c_9;
  51                 pinctrl0 = &pinctrl_0;
  52                 pinctrl1 = &pinctrl_1;
  53                 pinctrl2 = &pinctrl_2;
  54                 pinctrl3 = &pinctrl_3;
  55         };
  56
  57         cpus {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a15";
  64                         reg = <0>;
  65                         clock-frequency = <1700000000>;
  66                 };
  67                 cpu@1 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a15";
  70                         reg = <1>;
  71                         clock-frequency = <1700000000>;
  72                 };
  73         };
  74
  75         sysram@02020000 {
  76                 compatible = "mmio-sram";
  77                 reg = <0x02020000 0x30000>;
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 ranges = <0 0x02020000 0x30000>;
  81
  82                 smp-sysram@0 {
  83                         compatible = "samsung,exynos4210-sysram";
  84                         reg = <0x0 0x1000>;
  85                 };
  86
  87                 smp-sysram@2f000 {
  88                         compatible = "samsung,exynos4210-sysram-ns";
  89                         reg = <0x2f000 0x1000>;
  90                 };
  91         };
  92
  93         pd_gsc: gsc-power-domain@10044000 {
  94                 compatible = "samsung,exynos4210-pd";
  95                 reg = <0x10044000 0x20>;
  96         };
  97
  98         pd_mfc: mfc-power-domain@10044040 {
  99                 compatible = "samsung,exynos4210-pd";
 100                 reg = <0x10044040 0x20>;
 101         };
 102
 103         clock: clock-controller@10010000 {
 104                 compatible = "samsung,exynos5250-clock";
 105                 reg = <0x10010000 0x30000>;
 106                 #clock-cells = <1>;
 107         };
 108
 109         clock_audss: audss-clock-controller@3810000 {
 110                 compatible = "samsung,exynos5250-audss-clock";
 111                 reg = <0x03810000 0x0C>;
 112                 #clock-cells = <1>;
 113                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 114                          <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 115                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 116         };
 117
 118         timer {
 119                 compatible = "arm,armv7-timer";
 120                 interrupts = <1 13 0xf08>,
 121                              <1 14 0xf08>,
 122                              <1 11 0xf08>,
 123                              <1 10 0xf08>;
 124                 /* Unfortunately we need this since some versions of U-Boot
 125                  * on Exynos don't set the CNTFRQ register, so we need the
 126                  * value from DT.
 127                  */
 128                 clock-frequency = <24000000>;
 129         };
 130
 131         mct@101C0000 {
 132                 compatible = "samsung,exynos4210-mct";
 133                 reg = <0x101C0000 0x800>;
 134                 interrupt-controller;
 135                 #interrups-cells = <2>;
 136                 interrupt-parent = <&mct_map>;
 137                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 138                              <4 0>, <5 0>;
 139                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 140                 clock-names = "fin_pll", "mct";
 141
 142                 mct_map: mct-map {
 143                         #interrupt-cells = <2>;
 144                         #address-cells = <0>;
 145                         #size-cells = <0>;
 146                         interrupt-map = <0x0 0 &combiner 23 3>,
 147                                         <0x1 0 &combiner 23 4>,
 148                                         <0x2 0 &combiner 25 2>,
 149                                         <0x3 0 &combiner 25 3>,
 150                                         <0x4 0 &gic 0 120 0>,
 151                                         <0x5 0 &gic 0 121 0>;
 152                 };
 153         };
 154
 155         pmu {
 156                 compatible = "arm,cortex-a15-pmu";
 157                 interrupt-parent = <&combiner>;
 158                 interrupts = <1 2>, <22 4>;
 159         };
 160
 161         pinctrl_0: pinctrl@11400000 {
 162                 compatible = "samsung,exynos5250-pinctrl";
 163                 reg = <0x11400000 0x1000>;
 164                 interrupts = <0 46 0>;
 165
 166                 wakup_eint: wakeup-interrupt-controller {
 167                         compatible = "samsung,exynos4210-wakeup-eint";
 168                         interrupt-parent = <&gic>;
 169                         interrupts = <0 32 0>;
 170                 };
 171         };
 172
 173         pinctrl_1: pinctrl@13400000 {
 174                 compatible = "samsung,exynos5250-pinctrl";
 175                 reg = <0x13400000 0x1000>;
 176                 interrupts = <0 45 0>;
 177         };
 178
 179         pinctrl_2: pinctrl@10d10000 {
 180                 compatible = "samsung,exynos5250-pinctrl";
 181                 reg = <0x10d10000 0x1000>;
 182                 interrupts = <0 50 0>;
 183         };
 184
 185         pinctrl_3: pinctrl@03860000 {
 186                 compatible = "samsung,exynos5250-pinctrl";
 187                 reg = <0x03860000 0x1000>;
 188                 interrupts = <0 47 0>;
 189         };
 190
 191         pmu_system_controller: system-controller@10040000 {
 192                 compatible = "samsung,exynos5250-pmu", "syscon";
 193                 reg = <0x10040000 0x5000>;
 194                 clock-names = "clkout16";
 195                 clocks = <&clock CLK_FIN_PLL>;
 196                 #clock-cells = <1>;
 197         };
 198
 199         sysreg_system_controller: syscon@10050000 {
 200                 compatible = "samsung,exynos5-sysreg", "syscon";
 201                 reg = <0x10050000 0x5000>;
 202         };
 203
 204         watchdog@101D0000 {
 205                 compatible = "samsung,exynos5250-wdt";
 206                 reg = <0x101D0000 0x100>;
 207                 interrupts = <0 42 0>;
 208                 clocks = <&clock CLK_WDT>;
 209                 clock-names = "watchdog";
 210                 samsung,syscon-phandle = <&pmu_system_controller>;
 211         };
 212
 213         g2d@10850000 {
 214                 compatible = "samsung,exynos5250-g2d";
 215                 reg = <0x10850000 0x1000>;
 216                 interrupts = <0 91 0>;
 217                 clocks = <&clock CLK_G2D>;
 218                 clock-names = "fimg2d";
 219         };
 220
 221         codec@11000000 {
 222                 compatible = "samsung,mfc-v6";
 223                 reg = <0x11000000 0x10000>;
 224                 interrupts = <0 96 0>;
 225                 samsung,power-domain = <&pd_mfc>;
 226                 clocks = <&clock CLK_MFC>;
 227                 clock-names = "mfc";
 228         };
 229
 230         rtc@101E0000 {
 231                 clocks = <&clock CLK_RTC>;
 232                 clock-names = "rtc";
 233                 status = "disabled";
 234         };
 235
 236         tmu@10060000 {
 237                 compatible = "samsung,exynos5250-tmu";
 238                 reg = <0x10060000 0x100>;
 239                 interrupts = <0 65 0>;
 240                 clocks = <&clock CLK_TMU>;
 241                 clock-names = "tmu_apbif";
 242         };
 243
 244         serial@12C00000 {
 245                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 246                 clock-names = "uart", "clk_uart_baud0";
 247         };
 248
 249         serial@12C10000 {
 250                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 251                 clock-names = "uart", "clk_uart_baud0";
 252         };
 253
 254         serial@12C20000 {
 255                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 256                 clock-names = "uart", "clk_uart_baud0";
 257         };
 258
 259         serial@12C30000 {
 260                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 261                 clock-names = "uart", "clk_uart_baud0";
 262         };
 263
 264         sata@122F0000 {
 265                 compatible = "snps,dwc-ahci";
 266                 samsung,sata-freq = <66>;
 267                 reg = <0x122F0000 0x1ff>;
 268                 interrupts = <0 115 0>;
 269                 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 270                 clock-names = "sata", "sclk_sata";
 271                 phys = <&sata_phy>;
 272                 phy-names = "sata-phy";
 273                 status = "disabled";
 274         };
 275
 276         sata_phy: sata-phy@12170000 {
 277                 compatible = "samsung,exynos5250-sata-phy";
 278                 reg = <0x12170000 0x1ff>;
 279                 clocks = <&clock CLK_SATA_PHYCTRL>;
 280                 clock-names = "sata_phyctrl";
 281                 #phy-cells = <0>;
 282                 samsung,syscon-phandle = <&pmu_system_controller>;
 283                 status = "disabled";
 284         };
 285
 286         i2c_0: i2c@12C60000 {
 287                 compatible = "samsung,s3c2440-i2c";
 288                 reg = <0x12C60000 0x100>;
 289                 interrupts = <0 56 0>;
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292                 clocks = <&clock CLK_I2C0>;
 293                 clock-names = "i2c";
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&i2c0_bus>;
 296                 status = "disabled";
 297         };
 298
 299         i2c_1: i2c@12C70000 {
 300                 compatible = "samsung,s3c2440-i2c";
 301                 reg = <0x12C70000 0x100>;
 302                 interrupts = <0 57 0>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 clocks = <&clock CLK_I2C1>;
 306                 clock-names = "i2c";
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&i2c1_bus>;
 309                 status = "disabled";
 310         };
 311
 312         i2c_2: i2c@12C80000 {
 313                 compatible = "samsung,s3c2440-i2c";
 314                 reg = <0x12C80000 0x100>;
 315                 interrupts = <0 58 0>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 clocks = <&clock CLK_I2C2>;
 319                 clock-names = "i2c";
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&i2c2_bus>;
 322                 status = "disabled";
 323         };
 324
 325         i2c_3: i2c@12C90000 {
 326                 compatible = "samsung,s3c2440-i2c";
 327                 reg = <0x12C90000 0x100>;
 328                 interrupts = <0 59 0>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 clocks = <&clock CLK_I2C3>;
 332                 clock-names = "i2c";
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&i2c3_bus>;
 335                 status = "disabled";
 336         };
 337
 338         i2c_4: i2c@12CA0000 {
 339                 compatible = "samsung,s3c2440-i2c";
 340                 reg = <0x12CA0000 0x100>;
 341                 interrupts = <0 60 0>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 clocks = <&clock CLK_I2C4>;
 345                 clock-names = "i2c";
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&i2c4_bus>;
 348                 status = "disabled";
 349         };
 350
 351         i2c_5: i2c@12CB0000 {
 352                 compatible = "samsung,s3c2440-i2c";
 353                 reg = <0x12CB0000 0x100>;
 354                 interrupts = <0 61 0>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 clocks = <&clock CLK_I2C5>;
 358                 clock-names = "i2c";
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&i2c5_bus>;
 361                 status = "disabled";
 362         };
 363
 364         i2c_6: i2c@12CC0000 {
 365                 compatible = "samsung,s3c2440-i2c";
 366                 reg = <0x12CC0000 0x100>;
 367                 interrupts = <0 62 0>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 clocks = <&clock CLK_I2C6>;
 371                 clock-names = "i2c";
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&i2c6_bus>;
 374                 status = "disabled";
 375         };
 376
 377         i2c_7: i2c@12CD0000 {
 378                 compatible = "samsung,s3c2440-i2c";
 379                 reg = <0x12CD0000 0x100>;
 380                 interrupts = <0 63 0>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clocks = <&clock CLK_I2C7>;
 384                 clock-names = "i2c";
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&i2c7_bus>;
 387                 status = "disabled";
 388         };
 389
 390         i2c_8: i2c@12CE0000 {
 391                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 392                 reg = <0x12CE0000 0x1000>;
 393                 interrupts = <0 64 0>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 clocks = <&clock CLK_I2C_HDMI>;
 397                 clock-names = "i2c";
 398                 status = "disabled";
 399         };
 400
 401         i2c_9: i2c@121D0000 {
 402                 compatible = "samsung,exynos5-sata-phy-i2c";
 403                 reg = <0x121D0000 0x100>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clocks = <&clock CLK_SATA_PHYI2C>;
 407                 clock-names = "i2c";
 408                 status = "disabled";
 409         };
 410
 411         spi_0: spi@12d20000 {
 412                 compatible = "samsung,exynos4210-spi";
 413                 status = "disabled";
 414                 reg = <0x12d20000 0x100>;
 415                 interrupts = <0 66 0>;
 416                 dmas = <&pdma0 5
 417                         &pdma0 4>;
 418                 dma-names = "tx", "rx";
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 422                 clock-names = "spi", "spi_busclk0";
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&spi0_bus>;
 425         };
 426
 427         spi_1: spi@12d30000 {
 428                 compatible = "samsung,exynos4210-spi";
 429                 status = "disabled";
 430                 reg = <0x12d30000 0x100>;
 431                 interrupts = <0 67 0>;
 432                 dmas = <&pdma1 5
 433                         &pdma1 4>;
 434                 dma-names = "tx", "rx";
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 438                 clock-names = "spi", "spi_busclk0";
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&spi1_bus>;
 441         };
 442
 443         spi_2: spi@12d40000 {
 444                 compatible = "samsung,exynos4210-spi";
 445                 status = "disabled";
 446                 reg = <0x12d40000 0x100>;
 447                 interrupts = <0 68 0>;
 448                 dmas = <&pdma0 7
 449                         &pdma0 6>;
 450                 dma-names = "tx", "rx";
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 454                 clock-names = "spi", "spi_busclk0";
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&spi2_bus>;
 457         };
 458
 459         mmc_0: mmc@12200000 {
 460                 compatible = "samsung,exynos5250-dw-mshc";
 461                 interrupts = <0 75 0>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 reg = <0x12200000 0x1000>;
 465                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 466                 clock-names = "biu", "ciu";
 467                 fifo-depth = <0x80>;
 468                 status = "disabled";
 469         };
 470
 471         mmc_1: mmc@12210000 {
 472                 compatible = "samsung,exynos5250-dw-mshc";
 473                 interrupts = <0 76 0>;
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 reg = <0x12210000 0x1000>;
 477                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 478                 clock-names = "biu", "ciu";
 479                 fifo-depth = <0x80>;
 480                 status = "disabled";
 481         };
 482
 483         mmc_2: mmc@12220000 {
 484                 compatible = "samsung,exynos5250-dw-mshc";
 485                 interrupts = <0 77 0>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 reg = <0x12220000 0x1000>;
 489                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 490                 clock-names = "biu", "ciu";
 491                 fifo-depth = <0x80>;
 492                 status = "disabled";
 493         };
 494
 495         mmc_3: mmc@12230000 {
 496                 compatible = "samsung,exynos5250-dw-mshc";
 497                 reg = <0x12230000 0x1000>;
 498                 interrupts = <0 78 0>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 502                 clock-names = "biu", "ciu";
 503                 fifo-depth = <0x80>;
 504                 status = "disabled";
 505         };
 506
 507         i2s0: i2s@03830000 {
 508                 compatible = "samsung,s5pv210-i2s";
 509                 status = "disabled";
 510                 reg = <0x03830000 0x100>;
 511                 dmas = <&pdma0 10
 512                         &pdma0 9
 513                         &pdma0 8>;
 514                 dma-names = "tx", "rx", "tx-sec";
 515                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 516                         <&clock_audss EXYNOS_I2S_BUS>,
 517                         <&clock_audss EXYNOS_SCLK_I2S>;
 518                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 519                 samsung,idma-addr = <0x03000000>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2s0_bus>;
 522         };
 523
 524         i2s1: i2s@12D60000 {
 525                 compatible = "samsung,s3c6410-i2s";
 526                 status = "disabled";
 527                 reg = <0x12D60000 0x100>;
 528                 dmas = <&pdma1 12
 529                         &pdma1 11>;
 530                 dma-names = "tx", "rx";
 531                 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 532                 clock-names = "iis", "i2s_opclk0";
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&i2s1_bus>;
 535         };
 536
 537         i2s2: i2s@12D70000 {
 538                 compatible = "samsung,s3c6410-i2s";
 539                 status = "disabled";
 540                 reg = <0x12D70000 0x100>;
 541                 dmas = <&pdma0 12
 542                         &pdma0 11>;
 543                 dma-names = "tx", "rx";
 544                 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 545                 clock-names = "iis", "i2s_opclk0";
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2s2_bus>;
 548         };
 549
 550         usb@12000000 {
 551                 compatible = "samsung,exynos5250-dwusb3";
 552                 clocks = <&clock CLK_USB3>;
 553                 clock-names = "usbdrd30";
 554                 #address-cells = <1>;
 555                 #size-cells = <1>;
 556                 ranges;
 557
 558                 dwc3 {
 559                         compatible = "synopsys,dwc3";
 560                         reg = <0x12000000 0x10000>;
 561                         interrupts = <0 72 0>;
 562                         phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 563                         phy-names = "usb2-phy", "usb3-phy";
 564                 };
 565         };
 566
 567         usbdrd_phy: phy@12100000 {
 568                 compatible = "samsung,exynos5250-usbdrd-phy";
 569                 reg = <0x12100000 0x100>;
 570                 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 571                 clock-names = "phy", "ref";
 572                 samsung,pmu-syscon = <&pmu_system_controller>;
 573                 #phy-cells = <1>;
 574         };
 575
 576         usb@12110000 {
 577                 compatible = "samsung,exynos4210-ehci";
 578                 reg = <0x12110000 0x100>;
 579                 interrupts = <0 71 0>;
 580
 581                 clocks = <&clock CLK_USB2>;
 582                 clock-names = "usbhost";
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 port@0 {
 586                         reg = <0>;
 587                         phys = <&usb2_phy_gen 1>;
 588                 };
 589         };
 590
 591         usb@12120000 {
 592                 compatible = "samsung,exynos4210-ohci";
 593                 reg = <0x12120000 0x100>;
 594                 interrupts = <0 71 0>;
 595
 596                 clocks = <&clock CLK_USB2>;
 597                 clock-names = "usbhost";
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 port@0 {
 601                         reg = <0>;
 602                         phys = <&usb2_phy_gen 1>;
 603                 };
 604         };
 605
 606         usb2_phy_gen: phy@12130000 {
 607                 compatible = "samsung,exynos5250-usb2-phy";
 608                 reg = <0x12130000 0x100>;
 609                 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 610                 clock-names = "phy", "ref";
 611                 #phy-cells = <1>;
 612                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 613                 samsung,pmureg-phandle = <&pmu_system_controller>;
 614         };
 615
 616         pwm: pwm@12dd0000 {
 617                 compatible = "samsung,exynos4210-pwm";
 618                 reg = <0x12dd0000 0x100>;
 619                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 620                 #pwm-cells = <3>;
 621                 clocks = <&clock CLK_PWM>;
 622                 clock-names = "timers";
 623         };
 624
 625         amba {
 626                 #address-cells = <1>;
 627                 #size-cells = <1>;
 628                 compatible = "arm,amba-bus";
 629                 interrupt-parent = <&gic>;
 630                 ranges;
 631
 632                 pdma0: pdma@121A0000 {
 633                         compatible = "arm,pl330", "arm,primecell";
 634                         reg = <0x121A0000 0x1000>;
 635                         interrupts = <0 34 0>;
 636                         clocks = <&clock CLK_PDMA0>;
 637                         clock-names = "apb_pclk";
 638                         #dma-cells = <1>;
 639                         #dma-channels = <8>;
 640                         #dma-requests = <32>;
 641                 };
 642
 643                 pdma1: pdma@121B0000 {
 644                         compatible = "arm,pl330", "arm,primecell";
 645                         reg = <0x121B0000 0x1000>;
 646                         interrupts = <0 35 0>;
 647                         clocks = <&clock CLK_PDMA1>;
 648                         clock-names = "apb_pclk";
 649                         #dma-cells = <1>;
 650                         #dma-channels = <8>;
 651                         #dma-requests = <32>;
 652                 };
 653
 654                 mdma0: mdma@10800000 {
 655                         compatible = "arm,pl330", "arm,primecell";
 656                         reg = <0x10800000 0x1000>;
 657                         interrupts = <0 33 0>;
 658                         clocks = <&clock CLK_MDMA0>;
 659                         clock-names = "apb_pclk";
 660                         #dma-cells = <1>;
 661                         #dma-channels = <8>;
 662                         #dma-requests = <1>;
 663                 };
 664
 665                 mdma1: mdma@11C10000 {
 666                         compatible = "arm,pl330", "arm,primecell";
 667                         reg = <0x11C10000 0x1000>;
 668                         interrupts = <0 124 0>;
 669                         clocks = <&clock CLK_MDMA1>;
 670                         clock-names = "apb_pclk";
 671                         #dma-cells = <1>;
 672                         #dma-channels = <8>;
 673                         #dma-requests = <1>;
 674                 };
 675         };
 676
 677         gsc_0:  gsc@13e00000 {
 678                 compatible = "samsung,exynos5-gsc";
 679                 reg = <0x13e00000 0x1000>;
 680                 interrupts = <0 85 0>;
 681                 samsung,power-domain = <&pd_gsc>;
 682                 clocks = <&clock CLK_GSCL0>;
 683                 clock-names = "gscl";
 684         };
 685
 686         gsc_1:  gsc@13e10000 {
 687                 compatible = "samsung,exynos5-gsc";
 688                 reg = <0x13e10000 0x1000>;
 689                 interrupts = <0 86 0>;
 690                 samsung,power-domain = <&pd_gsc>;
 691                 clocks = <&clock CLK_GSCL1>;
 692                 clock-names = "gscl";
 693         };
 694
 695         gsc_2:  gsc@13e20000 {
 696                 compatible = "samsung,exynos5-gsc";
 697                 reg = <0x13e20000 0x1000>;
 698                 interrupts = <0 87 0>;
 699                 samsung,power-domain = <&pd_gsc>;
 700                 clocks = <&clock CLK_GSCL2>;
 701                 clock-names = "gscl";
 702         };
 703
 704         gsc_3:  gsc@13e30000 {
 705                 compatible = "samsung,exynos5-gsc";
 706                 reg = <0x13e30000 0x1000>;
 707                 interrupts = <0 88 0>;
 708                 samsung,power-domain = <&pd_gsc>;
 709                 clocks = <&clock CLK_GSCL3>;
 710                 clock-names = "gscl";
 711         };
 712
 713         hdmi {
 714                 compatible = "samsung,exynos4212-hdmi";
 715                 reg = <0x14530000 0x70000>;
 716                 interrupts = <0 95 0>;
 717                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 718                          <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 719                          <&clock CLK_MOUT_HDMI>;
 720                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 721                                 "sclk_hdmiphy", "mout_hdmi";
 722                 samsung,syscon-phandle = <&pmu_system_controller>;
 723         };
 724
 725         mixer {
 726                 compatible = "samsung,exynos5250-mixer";
 727                 reg = <0x14450000 0x10000>;
 728                 interrupts = <0 94 0>;
 729                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 730                 clock-names = "mixer", "sclk_hdmi";
 731         };
 732
 733         dp_phy: video-phy@10040720 {
 734                 compatible = "samsung,exynos5250-dp-video-phy";
 735                 reg = <0x10040720 4>;
 736                 #phy-cells = <0>;
 737         };
 738
 739         dp-controller@145B0000 {
 740                 clocks = <&clock CLK_DP>;
 741                 clock-names = "dp";
 742                 phys = <&dp_phy>;
 743                 phy-names = "dp";
 744         };
 745
 746         fimd@14400000 {
 747                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 748                 clock-names = "sclk_fimd", "fimd";
 749         };
 750
 751         adc: adc@12D10000 {
 752                 compatible = "samsung,exynos-adc-v1";
 753                 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
 754                 interrupts = <0 106 0>;
 755                 clocks = <&clock CLK_ADC>;
 756                 clock-names = "adc";
 757                 #io-channel-cells = <1>;
 758                 io-channel-ranges;
 759                 status = "disabled";
 760         };
 761
 762         sss@10830000 {
 763                 compatible = "samsung,exynos4210-secss";
 764                 reg = <0x10830000 0x10000>;
 765                 interrupts = <0 112 0>;
 766                 clocks = <&clock CLK_SSS>;
 767                 clock-names = "secss";
 768         };
 769 };