arch/arm/boot/dts/exynos5410.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5410 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
   8  * EXYNOS5410 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "skeleton.dtsi"
  17 #include <dt-bindings/clock/exynos5410.h>
  18
  19 / {
  20         compatible = "samsung,exynos5410", "samsung,exynos5";
  21         interrupt-parent = <&gic>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 CPU0: cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a15";
  30                         reg = <0x0>;
  31                         clock-frequency = <1600000000>;
  32                 };
  33
  34                 CPU1: cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a15";
  37                         reg = <0x1>;
  38                         clock-frequency = <1600000000>;
  39                 };
  40
  41                 CPU2: cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x2>;
  45                         clock-frequency = <1600000000>;
  46                 };
  47
  48                 CPU3: cpu@3 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a15";
  51                         reg = <0x3>;
  52                         clock-frequency = <1600000000>;
  53                 };
  54         };
  55
  56         soc: soc {
  57                 compatible = "simple-bus";
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 ranges;
  61
  62                 combiner: interrupt-controller@10440000 {
  63                         compatible = "samsung,exynos4210-combiner";
  64                         #interrupt-cells = <2>;
  65                         interrupt-controller;
  66                         samsung,combiner-nr = <32>;
  67                         reg = <0x10440000 0x1000>;
  68                         interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  69                                         <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  70                                         <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  71                                         <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  72                                         <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
  73                                         <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
  74                                         <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
  75                                         <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
  76                 };
  77
  78                 gic: interrupt-controller@10481000 {
  79                         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  80                         #interrupt-cells = <3>;
  81                         interrupt-controller;
  82                         reg =   <0x10481000 0x1000>,
  83                                 <0x10482000 0x1000>,
  84                                 <0x10484000 0x2000>,
  85                                 <0x10486000 0x2000>;
  86                         interrupts = <1 9 0xf04>;
  87                 };
  88
  89                 chipid@10000000 {
  90                         compatible = "samsung,exynos4210-chipid";
  91                         reg = <0x10000000 0x100>;
  92                 };
  93
  94                 mct: mct@101C0000 {
  95                         compatible = "samsung,exynos4210-mct";
  96                         reg = <0x101C0000 0xB00>;
  97                         interrupt-parent = <&interrupt_map>;
  98                         interrupts = <0>, <1>, <2>, <3>,
  99                                 <4>, <5>, <6>, <7>,
 100                                 <8>, <9>, <10>, <11>;
 101                         clocks = <&fin_pll>, <&clock CLK_MCT>;
 102                         clock-names = "fin_pll", "mct";
 103
 104                         interrupt_map: interrupt-map {
 105                                 #interrupt-cells = <1>;
 106                                 #address-cells = <0>;
 107                                 #size-cells = <0>;
 108                                 interrupt-map = <0 &combiner 23 3>,
 109                                                 <1 &combiner 23 4>,
 110                                                 <2 &combiner 25 2>,
 111                                                 <3 &combiner 25 3>,
 112                                                 <4 &gic 0 120 0>,
 113                                                 <5 &gic 0 121 0>,
 114                                                 <6 &gic 0 122 0>,
 115                                                 <7 &gic 0 123 0>,
 116                                                 <8 &gic 0 128 0>,
 117                                                 <9 &gic 0 129 0>,
 118                                                 <10 &gic 0 130 0>,
 119                                                 <11 &gic 0 131 0>;
 120                         };
 121                 };
 122
 123                 sysram@02020000 {
 124                         compatible = "mmio-sram";
 125                         reg = <0x02020000 0x54000>;
 126                         #address-cells = <1>;
 127                         #size-cells = <1>;
 128                         ranges = <0 0x02020000 0x54000>;
 129
 130                         smp-sysram@0 {
 131                                 compatible = "samsung,exynos4210-sysram";
 132                                 reg = <0x0 0x1000>;
 133                         };
 134
 135                         smp-sysram@53000 {
 136                                 compatible = "samsung,exynos4210-sysram-ns";
 137                                 reg = <0x53000 0x1000>;
 138                         };
 139                 };
 140
 141                 clock: clock-controller@10010000 {
 142                         compatible = "samsung,exynos5410-clock";
 143                         reg = <0x10010000 0x30000>;
 144                         #clock-cells = <1>;
 145                 };
 146
 147                 mmc_0: mmc@12200000 {
 148                         compatible = "samsung,exynos5250-dw-mshc";
 149                         reg = <0x12200000 0x1000>;
 150                         interrupts = <0 75 0>;
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 154                         clock-names = "biu", "ciu";
 155                         fifo-depth = <0x80>;
 156                         status = "disabled";
 157                 };
 158
 159                 mmc_1: mmc@12210000 {
 160                         compatible = "samsung,exynos5250-dw-mshc";
 161                         reg = <0x12210000 0x1000>;
 162                         interrupts = <0 76 0>;
 163                         #address-cells = <1>;
 164                         #size-cells = <0>;
 165                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 166                         clock-names = "biu", "ciu";
 167                         fifo-depth = <0x80>;
 168                         status = "disabled";
 169                 };
 170
 171                 mmc_2: mmc@12220000 {
 172                         compatible = "samsung,exynos5250-dw-mshc";
 173                         reg = <0x12220000 0x1000>;
 174                         interrupts = <0 77 0>;
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 178                         clock-names = "biu", "ciu";
 179                         fifo-depth = <0x80>;
 180                         status = "disabled";
 181                 };
 182
 183                 uart0: serial@12C00000 {
 184                         compatible = "samsung,exynos4210-uart";
 185                         reg = <0x12C00000 0x100>;
 186                         interrupts = <0 51 0>;
 187                         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 188                         clock-names = "uart", "clk_uart_baud0";
 189                         status = "disabled";
 190                 };
 191
 192                 uart1: serial@12C10000 {
 193                         compatible = "samsung,exynos4210-uart";
 194                         reg = <0x12C10000 0x100>;
 195                         interrupts = <0 52 0>;
 196                         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 197                         clock-names = "uart", "clk_uart_baud0";
 198                         status = "disabled";
 199                 };
 200
 201                 uart2: serial@12C20000 {
 202                         compatible = "samsung,exynos4210-uart";
 203                         reg = <0x12C20000 0x100>;
 204                         interrupts = <0 53 0>;
 205                         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 206                         clock-names = "uart", "clk_uart_baud0";
 207                         status = "disabled";
 208                 };
 209         };
 210 };