2 * SAMSUNG EXYNOS5410 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
8 * EXYNOS5410 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include "skeleton.dtsi"
17 #include <dt-bindings/clock/exynos5410.h>
20 compatible = "samsung,exynos5410", "samsung,exynos5";
21 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a15";
41 compatible = "arm,cortex-a15";
47 compatible = "arm,cortex-a15";
53 compatible = "arm,cortex-a15";
59 compatible = "simple-bus";
64 combiner: interrupt-controller@10440000 {
65 compatible = "samsung,exynos4210-combiner";
66 #interrupt-cells = <2>;
68 samsung,combiner-nr = <32>;
69 reg = <0x10440000 0x1000>;
70 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
71 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
72 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
73 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
74 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
75 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
76 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
77 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
80 gic: interrupt-controller@10481000 {
81 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
82 #interrupt-cells = <3>;
84 reg = <0x10481000 0x1000>,
88 interrupts = <1 9 0xf04>;
92 compatible = "samsung,exynos4210-chipid";
93 reg = <0x10000000 0x100>;
97 compatible = "samsung,exynos4210-mct";
98 reg = <0x101C0000 0xB00>;
99 interrupt-parent = <&interrupt_map>;
100 interrupts = <0>, <1>, <2>, <3>,
102 <8>, <9>, <10>, <11>;
103 clocks = <&fin_pll>, <&clock CLK_MCT>;
104 clock-names = "fin_pll", "mct";
106 interrupt_map: interrupt-map {
107 #interrupt-cells = <1>;
108 #address-cells = <0>;
110 interrupt-map = <0 &combiner 23 3>,
126 compatible = "mmio-sram";
127 reg = <0x02020000 0x54000>;
128 #address-cells = <1>;
130 ranges = <0 0x02020000 0x54000>;
133 compatible = "samsung,exynos4210-sysram";
138 compatible = "samsung,exynos4210-sysram-ns";
139 reg = <0x53000 0x1000>;
143 clock: clock-controller@10010000 {
144 compatible = "samsung,exynos5410-clock";
145 reg = <0x10010000 0x30000>;
149 mmc_0: mmc@12200000 {
150 compatible = "samsung,exynos5250-dw-mshc";
151 reg = <0x12200000 0x1000>;
152 interrupts = <0 75 0>;
153 #address-cells = <1>;
155 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
156 clock-names = "biu", "ciu";
161 mmc_1: mmc@12210000 {
162 compatible = "samsung,exynos5250-dw-mshc";
163 reg = <0x12210000 0x1000>;
164 interrupts = <0 76 0>;
165 #address-cells = <1>;
167 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
168 clock-names = "biu", "ciu";
173 mmc_2: mmc@12220000 {
174 compatible = "samsung,exynos5250-dw-mshc";
175 reg = <0x12220000 0x1000>;
176 interrupts = <0 77 0>;
177 #address-cells = <1>;
179 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
180 clock-names = "biu", "ciu";
185 uart0: serial@12C00000 {
186 compatible = "samsung,exynos4210-uart";
187 reg = <0x12C00000 0x100>;
188 interrupts = <0 51 0>;
189 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
190 clock-names = "uart", "clk_uart_baud0";
194 uart1: serial@12C10000 {
195 compatible = "samsung,exynos4210-uart";
196 reg = <0x12C10000 0x100>;
197 interrupts = <0 52 0>;
198 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
199 clock-names = "uart", "clk_uart_baud0";
203 uart2: serial@12C20000 {
204 compatible = "samsung,exynos4210-uart";
205 reg = <0x12C20000 0x100>;
206 interrupts = <0 53 0>;
207 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
208 clock-names = "uart", "clk_uart_baud0";