2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
67 compatible = "arm,cortex-a15";
69 clock-frequency = <1800000000>;
74 compatible = "arm,cortex-a15";
76 clock-frequency = <1800000000>;
81 compatible = "arm,cortex-a15";
83 clock-frequency = <1800000000>;
88 compatible = "arm,cortex-a7";
90 clock-frequency = <1000000000>;
95 compatible = "arm,cortex-a7";
97 clock-frequency = <1000000000>;
102 compatible = "arm,cortex-a7";
104 clock-frequency = <1000000000>;
109 compatible = "arm,cortex-a7";
111 clock-frequency = <1000000000>;
116 compatible = "mmio-sram";
117 reg = <0x02020000 0x54000>;
118 #address-cells = <1>;
120 ranges = <0 0x02020000 0x54000>;
123 compatible = "samsung,exynos4210-sysram";
128 compatible = "samsung,exynos4210-sysram-ns";
129 reg = <0x53000 0x1000>;
133 clock: clock-controller@10010000 {
134 compatible = "samsung,exynos5420-clock";
135 reg = <0x10010000 0x30000>;
139 clock_audss: audss-clock-controller@3810000 {
140 compatible = "samsung,exynos5420-audss-clock";
141 reg = <0x03810000 0x0C>;
143 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
144 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
145 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
148 mfc: codec@11000000 {
149 compatible = "samsung,mfc-v7";
150 reg = <0x11000000 0x10000>;
151 interrupts = <0 96 0>;
152 clocks = <&clock CLK_MFC>;
156 mmc_0: mmc@12200000 {
157 compatible = "samsung,exynos5420-dw-mshc-smu";
158 interrupts = <0 75 0>;
159 #address-cells = <1>;
161 reg = <0x12200000 0x2000>;
162 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
163 clock-names = "biu", "ciu";
168 mmc_1: mmc@12210000 {
169 compatible = "samsung,exynos5420-dw-mshc-smu";
170 interrupts = <0 76 0>;
171 #address-cells = <1>;
173 reg = <0x12210000 0x2000>;
174 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
175 clock-names = "biu", "ciu";
180 mmc_2: mmc@12220000 {
181 compatible = "samsung,exynos5420-dw-mshc";
182 interrupts = <0 77 0>;
183 #address-cells = <1>;
185 reg = <0x12220000 0x1000>;
186 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
187 clock-names = "biu", "ciu";
193 compatible = "samsung,exynos4210-mct";
194 reg = <0x101C0000 0x800>;
195 interrupt-controller;
196 #interrups-cells = <1>;
197 interrupt-parent = <&mct_map>;
198 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
199 <8>, <9>, <10>, <11>;
200 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
201 clock-names = "fin_pll", "mct";
204 #interrupt-cells = <1>;
205 #address-cells = <0>;
207 interrupt-map = <0 &combiner 23 3>,
222 gsc_pd: power-domain@10044000 {
223 compatible = "samsung,exynos4210-pd";
224 reg = <0x10044000 0x20>;
227 isp_pd: power-domain@10044020 {
228 compatible = "samsung,exynos4210-pd";
229 reg = <0x10044020 0x20>;
232 mfc_pd: power-domain@10044060 {
233 compatible = "samsung,exynos4210-pd";
234 reg = <0x10044060 0x20>;
237 disp_pd: power-domain@100440C0 {
238 compatible = "samsung,exynos4210-pd";
239 reg = <0x100440C0 0x20>;
242 mau_pd: power-domain@100440E0 {
243 compatible = "samsung,exynos4210-pd";
244 reg = <0x100440E0 0x20>;
247 g2d_pd: power-domain@10044100 {
248 compatible = "samsung,exynos4210-pd";
249 reg = <0x10044100 0x20>;
252 msc_pd: power-domain@10044120 {
253 compatible = "samsung,exynos4210-pd";
254 reg = <0x10044120 0x20>;
257 pinctrl_0: pinctrl@13400000 {
258 compatible = "samsung,exynos5420-pinctrl";
259 reg = <0x13400000 0x1000>;
260 interrupts = <0 45 0>;
262 wakeup-interrupt-controller {
263 compatible = "samsung,exynos4210-wakeup-eint";
264 interrupt-parent = <&gic>;
265 interrupts = <0 32 0>;
269 pinctrl_1: pinctrl@13410000 {
270 compatible = "samsung,exynos5420-pinctrl";
271 reg = <0x13410000 0x1000>;
272 interrupts = <0 78 0>;
275 pinctrl_2: pinctrl@14000000 {
276 compatible = "samsung,exynos5420-pinctrl";
277 reg = <0x14000000 0x1000>;
278 interrupts = <0 46 0>;
281 pinctrl_3: pinctrl@14010000 {
282 compatible = "samsung,exynos5420-pinctrl";
283 reg = <0x14010000 0x1000>;
284 interrupts = <0 50 0>;
287 pinctrl_4: pinctrl@03860000 {
288 compatible = "samsung,exynos5420-pinctrl";
289 reg = <0x03860000 0x1000>;
290 interrupts = <0 47 0>;
294 clocks = <&clock CLK_RTC>;
300 #address-cells = <1>;
302 compatible = "arm,amba-bus";
303 interrupt-parent = <&gic>;
306 adma: adma@03880000 {
307 compatible = "arm,pl330", "arm,primecell";
308 reg = <0x03880000 0x1000>;
309 interrupts = <0 110 0>;
310 clocks = <&clock_audss EXYNOS_ADMA>;
311 clock-names = "apb_pclk";
314 #dma-requests = <16>;
317 pdma0: pdma@121A0000 {
318 compatible = "arm,pl330", "arm,primecell";
319 reg = <0x121A0000 0x1000>;
320 interrupts = <0 34 0>;
321 clocks = <&clock CLK_PDMA0>;
322 clock-names = "apb_pclk";
325 #dma-requests = <32>;
328 pdma1: pdma@121B0000 {
329 compatible = "arm,pl330", "arm,primecell";
330 reg = <0x121B0000 0x1000>;
331 interrupts = <0 35 0>;
332 clocks = <&clock CLK_PDMA1>;
333 clock-names = "apb_pclk";
336 #dma-requests = <32>;
339 mdma0: mdma@10800000 {
340 compatible = "arm,pl330", "arm,primecell";
341 reg = <0x10800000 0x1000>;
342 interrupts = <0 33 0>;
343 clocks = <&clock CLK_MDMA0>;
344 clock-names = "apb_pclk";
350 mdma1: mdma@11C10000 {
351 compatible = "arm,pl330", "arm,primecell";
352 reg = <0x11C10000 0x1000>;
353 interrupts = <0 124 0>;
354 clocks = <&clock CLK_MDMA1>;
355 clock-names = "apb_pclk";
363 compatible = "samsung,exynos5420-i2s";
364 reg = <0x03830000 0x100>;
368 dma-names = "tx", "rx", "tx-sec";
369 clocks = <&clock_audss EXYNOS_I2S_BUS>,
370 <&clock_audss EXYNOS_I2S_BUS>,
371 <&clock_audss EXYNOS_SCLK_I2S>;
372 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
373 samsung,idma-addr = <0x03000000>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2s0_bus>;
380 compatible = "samsung,exynos5420-i2s";
381 reg = <0x12D60000 0x100>;
384 dma-names = "tx", "rx";
385 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
386 clock-names = "iis", "i2s_opclk0";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2s1_bus>;
393 compatible = "samsung,exynos5420-i2s";
394 reg = <0x12D70000 0x100>;
397 dma-names = "tx", "rx";
398 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
399 clock-names = "iis", "i2s_opclk0";
400 pinctrl-names = "default";
401 pinctrl-0 = <&i2s2_bus>;
405 spi_0: spi@12d20000 {
406 compatible = "samsung,exynos4210-spi";
407 reg = <0x12d20000 0x100>;
408 interrupts = <0 66 0>;
411 dma-names = "tx", "rx";
412 #address-cells = <1>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&spi0_bus>;
416 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
417 clock-names = "spi", "spi_busclk0";
421 spi_1: spi@12d30000 {
422 compatible = "samsung,exynos4210-spi";
423 reg = <0x12d30000 0x100>;
424 interrupts = <0 67 0>;
427 dma-names = "tx", "rx";
428 #address-cells = <1>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&spi1_bus>;
432 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
433 clock-names = "spi", "spi_busclk0";
437 spi_2: spi@12d40000 {
438 compatible = "samsung,exynos4210-spi";
439 reg = <0x12d40000 0x100>;
440 interrupts = <0 68 0>;
443 dma-names = "tx", "rx";
444 #address-cells = <1>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&spi2_bus>;
448 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
449 clock-names = "spi", "spi_busclk0";
453 uart_0: serial@12C00000 {
454 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
455 clock-names = "uart", "clk_uart_baud0";
458 uart_1: serial@12C10000 {
459 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
460 clock-names = "uart", "clk_uart_baud0";
463 uart_2: serial@12C20000 {
464 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
465 clock-names = "uart", "clk_uart_baud0";
468 uart_3: serial@12C30000 {
469 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
470 clock-names = "uart", "clk_uart_baud0";
474 compatible = "samsung,exynos4210-pwm";
475 reg = <0x12dd0000 0x100>;
476 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
478 clocks = <&clock CLK_PWM>;
479 clock-names = "timers";
482 dp_phy: video-phy@10040728 {
483 compatible = "samsung,exynos5250-dp-video-phy";
484 reg = <0x10040728 4>;
488 dp: dp-controller@145B0000 {
489 clocks = <&clock CLK_DP1>;
495 fimd: fimd@14400000 {
496 samsung,power-domain = <&disp_pd>;
497 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
498 clock-names = "sclk_fimd", "fimd";
502 compatible = "samsung,exynos-adc-v2";
503 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
504 interrupts = <0 106 0>;
505 clocks = <&clock CLK_TSADC>;
507 #io-channel-cells = <1>;
512 i2c_0: i2c@12C60000 {
513 compatible = "samsung,s3c2440-i2c";
514 reg = <0x12C60000 0x100>;
515 interrupts = <0 56 0>;
516 #address-cells = <1>;
518 clocks = <&clock CLK_I2C0>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c0_bus>;
525 i2c_1: i2c@12C70000 {
526 compatible = "samsung,s3c2440-i2c";
527 reg = <0x12C70000 0x100>;
528 interrupts = <0 57 0>;
529 #address-cells = <1>;
531 clocks = <&clock CLK_I2C1>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c1_bus>;
538 i2c_2: i2c@12C80000 {
539 compatible = "samsung,s3c2440-i2c";
540 reg = <0x12C80000 0x100>;
541 interrupts = <0 58 0>;
542 #address-cells = <1>;
544 clocks = <&clock CLK_I2C2>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c2_bus>;
551 i2c_3: i2c@12C90000 {
552 compatible = "samsung,s3c2440-i2c";
553 reg = <0x12C90000 0x100>;
554 interrupts = <0 59 0>;
555 #address-cells = <1>;
557 clocks = <&clock CLK_I2C3>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c3_bus>;
564 hsi2c_4: i2c@12CA0000 {
565 compatible = "samsung,exynos5-hsi2c";
566 reg = <0x12CA0000 0x1000>;
567 interrupts = <0 60 0>;
568 #address-cells = <1>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&i2c4_hs_bus>;
572 clocks = <&clock CLK_I2C4>;
573 clock-names = "hsi2c";
577 hsi2c_5: i2c@12CB0000 {
578 compatible = "samsung,exynos5-hsi2c";
579 reg = <0x12CB0000 0x1000>;
580 interrupts = <0 61 0>;
581 #address-cells = <1>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&i2c5_hs_bus>;
585 clocks = <&clock CLK_I2C5>;
586 clock-names = "hsi2c";
590 hsi2c_6: i2c@12CC0000 {
591 compatible = "samsung,exynos5-hsi2c";
592 reg = <0x12CC0000 0x1000>;
593 interrupts = <0 62 0>;
594 #address-cells = <1>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&i2c6_hs_bus>;
598 clocks = <&clock CLK_I2C6>;
599 clock-names = "hsi2c";
603 hsi2c_7: i2c@12CD0000 {
604 compatible = "samsung,exynos5-hsi2c";
605 reg = <0x12CD0000 0x1000>;
606 interrupts = <0 63 0>;
607 #address-cells = <1>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&i2c7_hs_bus>;
611 clocks = <&clock CLK_I2C7>;
612 clock-names = "hsi2c";
616 hsi2c_8: i2c@12E00000 {
617 compatible = "samsung,exynos5-hsi2c";
618 reg = <0x12E00000 0x1000>;
619 interrupts = <0 87 0>;
620 #address-cells = <1>;
622 pinctrl-names = "default";
623 pinctrl-0 = <&i2c8_hs_bus>;
624 clocks = <&clock CLK_I2C8>;
625 clock-names = "hsi2c";
629 hsi2c_9: i2c@12E10000 {
630 compatible = "samsung,exynos5-hsi2c";
631 reg = <0x12E10000 0x1000>;
632 interrupts = <0 88 0>;
633 #address-cells = <1>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&i2c9_hs_bus>;
637 clocks = <&clock CLK_I2C9>;
638 clock-names = "hsi2c";
642 hsi2c_10: i2c@12E20000 {
643 compatible = "samsung,exynos5-hsi2c";
644 reg = <0x12E20000 0x1000>;
645 interrupts = <0 203 0>;
646 #address-cells = <1>;
648 pinctrl-names = "default";
649 pinctrl-0 = <&i2c10_hs_bus>;
650 clocks = <&clock CLK_I2C10>;
651 clock-names = "hsi2c";
655 hdmi: hdmi@14530000 {
656 compatible = "samsung,exynos5420-hdmi";
657 reg = <0x14530000 0x70000>;
658 interrupts = <0 95 0>;
659 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
660 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
661 <&clock CLK_MOUT_HDMI>;
662 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
663 "sclk_hdmiphy", "mout_hdmi";
668 hdmiphy: hdmiphy@145D0000 {
669 reg = <0x145D0000 0x20>;
672 mixer: mixer@14450000 {
673 compatible = "samsung,exynos5420-mixer";
674 reg = <0x14450000 0x10000>;
675 interrupts = <0 94 0>;
676 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
677 clock-names = "mixer", "sclk_hdmi";
680 gsc_0: video-scaler@13e00000 {
681 compatible = "samsung,exynos5-gsc";
682 reg = <0x13e00000 0x1000>;
683 interrupts = <0 85 0>;
684 clocks = <&clock CLK_GSCL0>;
685 clock-names = "gscl";
686 samsung,power-domain = <&gsc_pd>;
689 gsc_1: video-scaler@13e10000 {
690 compatible = "samsung,exynos5-gsc";
691 reg = <0x13e10000 0x1000>;
692 interrupts = <0 86 0>;
693 clocks = <&clock CLK_GSCL1>;
694 clock-names = "gscl";
695 samsung,power-domain = <&gsc_pd>;
698 pmu_system_controller: system-controller@10040000 {
699 compatible = "samsung,exynos5420-pmu", "syscon";
700 reg = <0x10040000 0x5000>;
703 tmu_cpu0: tmu@10060000 {
704 compatible = "samsung,exynos5420-tmu";
705 reg = <0x10060000 0x100>;
706 interrupts = <0 65 0>;
707 clocks = <&clock CLK_TMU>;
708 clock-names = "tmu_apbif";
711 tmu_cpu1: tmu@10064000 {
712 compatible = "samsung,exynos5420-tmu";
713 reg = <0x10064000 0x100>;
714 interrupts = <0 183 0>;
715 clocks = <&clock CLK_TMU>;
716 clock-names = "tmu_apbif";
719 tmu_cpu2: tmu@10068000 {
720 compatible = "samsung,exynos5420-tmu-ext-triminfo";
721 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
722 interrupts = <0 184 0>;
723 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
724 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
727 tmu_cpu3: tmu@1006c000 {
728 compatible = "samsung,exynos5420-tmu-ext-triminfo";
729 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
730 interrupts = <0 185 0>;
731 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
732 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
735 tmu_gpu: tmu@100a0000 {
736 compatible = "samsung,exynos5420-tmu-ext-triminfo";
737 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
738 interrupts = <0 215 0>;
739 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
740 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
743 watchdog: watchdog@101D0000 {
744 compatible = "samsung,exynos5420-wdt";
745 reg = <0x101D0000 0x100>;
746 interrupts = <0 42 0>;
747 clocks = <&clock CLK_WDT>;
748 clock-names = "watchdog";
749 samsung,syscon-phandle = <&pmu_system_controller>;
753 compatible = "samsung,exynos4210-secss";
754 reg = <0x10830000 0x10000>;
755 interrupts = <0 112 0>;
756 clocks = <&clock 471>;
757 clock-names = "secss";
758 samsung,power-domain = <&g2d_pd>;
761 usbdrd3_0: usb@12000000 {
762 compatible = "samsung,exynos5250-dwusb3";
763 clocks = <&clock CLK_USBD300>;
764 clock-names = "usbdrd30";
765 #address-cells = <1>;
770 compatible = "snps,dwc3";
771 reg = <0x12000000 0x10000>;
772 interrupts = <0 72 0>;
773 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
774 phy-names = "usb2-phy", "usb3-phy";
778 usbdrd_phy0: phy@12100000 {
779 compatible = "samsung,exynos5420-usbdrd-phy";
780 reg = <0x12100000 0x100>;
781 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
782 clock-names = "phy", "ref";
783 samsung,pmu-syscon = <&pmu_system_controller>;
787 usbdrd3_1: usb@12400000 {
788 compatible = "samsung,exynos5250-dwusb3";
789 clocks = <&clock CLK_USBD301>;
790 clock-names = "usbdrd30";
791 #address-cells = <1>;
796 compatible = "snps,dwc3";
797 reg = <0x12400000 0x10000>;
798 interrupts = <0 73 0>;
799 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
800 phy-names = "usb2-phy", "usb3-phy";
804 usbdrd_phy1: phy@12500000 {
805 compatible = "samsung,exynos5420-usbdrd-phy";
806 reg = <0x12500000 0x100>;
807 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
808 clock-names = "phy", "ref";
809 samsung,pmu-syscon = <&pmu_system_controller>;