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1 /*
2 * Hardkernel Odroid XU3 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2014 Collabora Ltd.
7 * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
8 * Anand Moon <linux.amoon@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <dt-bindings/clock/samsung,s2mps11.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/sound/samsung-i2s.h>
20 #include "exynos5800.dtsi"
21 #include "exynos5422-cpus.dtsi"
22
23 / {
24 memory@40000000 {
25 device_type = "memory";
26 reg = <0x40000000 0x7EA00000>;
27 };
28
29 chosen {
30 stdout-path = "serial2:115200n8";
31 };
32
33 firmware@02073000 {
34 compatible = "samsung,secure-firmware";
35 reg = <0x02073000 0x1000>;
36 };
37
38 fixed-rate-clocks {
39 oscclk {
40 compatible = "samsung,exynos5420-oscclk";
41 clock-frequency = <24000000>;
42 };
43 };
44
45 gpio_keys {
46 compatible = "gpio-keys";
47 pinctrl-names = "default";
48 pinctrl-0 = <&power_key>;
49
50 power_key {
51 /*
52 * The power button (SW2) is connected to the PWRON
53 * pin (active high) of the S2MPS11 PMIC, which acts
54 * as a 16ms debouce filter and signal inverter with
55 * output on ONOB pin (active low). ONOB PMIC pin is
56 * then connected to XEINT3 SoC pin.
57 */
58 gpios = <&gpx0 3 GPIO_ACTIVE_LOW>;
59 linux,code = <KEY_POWER>;
60 label = "power key";
61 debounce-interval = <0>;
62 wakeup-source;
63 };
64 };
65
66 emmc_pwrseq: pwrseq {
67 pinctrl-0 = <&emmc_nrst_pin>;
68 pinctrl-names = "default";
69 compatible = "mmc-pwrseq-emmc";
70 reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
71 };
72
73 fan0: pwm-fan {
74 compatible = "pwm-fan";
75 pwms = <&pwm 0 20972 0>;
76 cooling-min-state = <0>;
77 cooling-max-state = <3>;
78 #cooling-cells = <2>;
79 cooling-levels = <0 130 170 230>;
80 };
81
82 thermal-zones {
83 cpu0_thermal: cpu0-thermal {
84 thermal-sensors = <&tmu_cpu0 0>;
85 polling-delay-passive = <250>;
86 polling-delay = <0>;
87 trips {
88 cpu0_alert0: cpu-alert-0 {
89 temperature = <50000>; /* millicelsius */
90 hysteresis = <5000>; /* millicelsius */
91 type = "active";
92 };
93 cpu0_alert1: cpu-alert-1 {
94 temperature = <60000>; /* millicelsius */
95 hysteresis = <5000>; /* millicelsius */
96 type = "active";
97 };
98 cpu0_alert2: cpu-alert-2 {
99 temperature = <70000>; /* millicelsius */
100 hysteresis = <5000>; /* millicelsius */
101 type = "active";
102 };
103 cpu0_crit0: cpu-crit-0 {
104 temperature = <120000>; /* millicelsius */
105 hysteresis = <0>; /* millicelsius */
106 type = "critical";
107 };
108 /*
109 * Exynos542x supports only 4 trip-points
110 * so for these polling mode is required.
111 * Start polling at temperature level of last
112 * interrupt-driven trip: cpu0_alert2
113 */
114 cpu0_alert3: cpu-alert-3 {
115 temperature = <70000>; /* millicelsius */
116 hysteresis = <10000>; /* millicelsius */
117 type = "passive";
118 };
119 cpu0_alert4: cpu-alert-4 {
120 temperature = <85000>; /* millicelsius */
121 hysteresis = <10000>; /* millicelsius */
122 type = "passive";
123 };
124 };
125 cooling-maps {
126 map0 {
127 trip = <&cpu0_alert0>;
128 cooling-device = <&fan0 0 1>;
129 };
130 map1 {
131 trip = <&cpu0_alert1>;
132 cooling-device = <&fan0 1 2>;
133 };
134 map2 {
135 trip = <&cpu0_alert2>;
136 cooling-device = <&fan0 2 3>;
137 };
138 /*
139 * When reaching cpu0_alert3, reduce CPU
140 * by 2 steps. On Exynos5422/5800 that would
141 * be: 1600 MHz and 1100 MHz.
142 */
143 map3 {
144 trip = <&cpu0_alert3>;
145 cooling-device = <&cpu0 0 2>;
146 };
147 map4 {
148 trip = <&cpu0_alert3>;
149 cooling-device = <&cpu4 0 2>;
150 };
151 /*
152 * When reaching cpu0_alert4, reduce CPU
153 * further, down to 600 MHz (12 steps for big,
154 * 7 steps for LITTLE).
155 */
156 map5 {
157 trip = <&cpu0_alert4>;
158 cooling-device = <&cpu0 3 7>;
159 };
160 map6 {
161 trip = <&cpu0_alert4>;
162 cooling-device = <&cpu4 3 12>;
163 };
164 };
165 };
166 cpu1_thermal: cpu1-thermal {
167 thermal-sensors = <&tmu_cpu1 0>;
168 polling-delay-passive = <250>;
169 polling-delay = <0>;
170 trips {
171 cpu1_alert0: cpu-alert-0 {
172 temperature = <50000>;
173 hysteresis = <5000>;
174 type = "active";
175 };
176 cpu1_alert1: cpu-alert-1 {
177 temperature = <60000>;
178 hysteresis = <5000>;
179 type = "active";
180 };
181 cpu1_alert2: cpu-alert-2 {
182 temperature = <70000>;
183 hysteresis = <5000>;
184 type = "active";
185 };
186 cpu1_crit0: cpu-crit-0 {
187 temperature = <120000>;
188 hysteresis = <0>;
189 type = "critical";
190 };
191 cpu1_alert3: cpu-alert-3 {
192 temperature = <70000>;
193 hysteresis = <10000>;
194 type = "passive";
195 };
196 cpu1_alert4: cpu-alert-4 {
197 temperature = <85000>;
198 hysteresis = <10000>;
199 type = "passive";
200 };
201 };
202 cooling-maps {
203 map0 {
204 trip = <&cpu1_alert0>;
205 cooling-device = <&fan0 0 1>;
206 };
207 map1 {
208 trip = <&cpu1_alert1>;
209 cooling-device = <&fan0 1 2>;
210 };
211 map2 {
212 trip = <&cpu1_alert2>;
213 cooling-device = <&fan0 2 3>;
214 };
215 map3 {
216 trip = <&cpu1_alert3>;
217 cooling-device = <&cpu0 0 2>;
218 };
219 map4 {
220 trip = <&cpu1_alert3>;
221 cooling-device = <&cpu4 0 2>;
222 };
223 map5 {
224 trip = <&cpu1_alert4>;
225 cooling-device = <&cpu0 3 7>;
226 };
227 map6 {
228 trip = <&cpu1_alert4>;
229 cooling-device = <&cpu4 3 12>;
230 };
231 };
232 };
233 cpu2_thermal: cpu2-thermal {
234 thermal-sensors = <&tmu_cpu2 0>;
235 polling-delay-passive = <250>;
236 polling-delay = <0>;
237 trips {
238 cpu2_alert0: cpu-alert-0 {
239 temperature = <50000>;
240 hysteresis = <5000>;
241 type = "active";
242 };
243 cpu2_alert1: cpu-alert-1 {
244 temperature = <60000>;
245 hysteresis = <5000>;
246 type = "active";
247 };
248 cpu2_alert2: cpu-alert-2 {
249 temperature = <70000>;
250 hysteresis = <5000>;
251 type = "active";
252 };
253 cpu2_crit0: cpu-crit-0 {
254 temperature = <120000>;
255 hysteresis = <0>;
256 type = "critical";
257 };
258 cpu2_alert3: cpu-alert-3 {
259 temperature = <70000>;
260 hysteresis = <10000>;
261 type = "passive";
262 };
263 cpu2_alert4: cpu-alert-4 {
264 temperature = <85000>;
265 hysteresis = <10000>;
266 type = "passive";
267 };
268 };
269 cooling-maps {
270 map0 {
271 trip = <&cpu2_alert0>;
272 cooling-device = <&fan0 0 1>;
273 };
274 map1 {
275 trip = <&cpu2_alert1>;
276 cooling-device = <&fan0 1 2>;
277 };
278 map2 {
279 trip = <&cpu2_alert2>;
280 cooling-device = <&fan0 2 3>;
281 };
282 map3 {
283 trip = <&cpu2_alert3>;
284 cooling-device = <&cpu0 0 2>;
285 };
286 map4 {
287 trip = <&cpu2_alert3>;
288 cooling-device = <&cpu4 0 2>;
289 };
290 map5 {
291 trip = <&cpu2_alert4>;
292 cooling-device = <&cpu0 3 7>;
293 };
294 map6 {
295 trip = <&cpu2_alert4>;
296 cooling-device = <&cpu4 3 12>;
297 };
298 };
299 };
300 cpu3_thermal: cpu3-thermal {
301 thermal-sensors = <&tmu_cpu3 0>;
302 polling-delay-passive = <250>;
303 polling-delay = <0>;
304 trips {
305 cpu3_alert0: cpu-alert-0 {
306 temperature = <50000>;
307 hysteresis = <5000>;
308 type = "active";
309 };
310 cpu3_alert1: cpu-alert-1 {
311 temperature = <60000>;
312 hysteresis = <5000>;
313 type = "active";
314 };
315 cpu3_alert2: cpu-alert-2 {
316 temperature = <70000>;
317 hysteresis = <5000>;
318 type = "active";
319 };
320 cpu3_crit0: cpu-crit-0 {
321 temperature = <120000>;
322 hysteresis = <0>;
323 type = "critical";
324 };
325 cpu3_alert3: cpu-alert-3 {
326 temperature = <70000>;
327 hysteresis = <10000>;
328 type = "passive";
329 };
330 cpu3_alert4: cpu-alert-4 {
331 temperature = <85000>;
332 hysteresis = <10000>;
333 type = "passive";
334 };
335 };
336 cooling-maps {
337 map0 {
338 trip = <&cpu3_alert0>;
339 cooling-device = <&fan0 0 1>;
340 };
341 map1 {
342 trip = <&cpu3_alert1>;
343 cooling-device = <&fan0 1 2>;
344 };
345 map2 {
346 trip = <&cpu3_alert2>;
347 cooling-device = <&fan0 2 3>;
348 };
349 map3 {
350 trip = <&cpu3_alert3>;
351 cooling-device = <&cpu0 0 2>;
352 };
353 map4 {
354 trip = <&cpu3_alert3>;
355 cooling-device = <&cpu4 0 2>;
356 };
357 map5 {
358 trip = <&cpu3_alert4>;
359 cooling-device = <&cpu0 3 7>;
360 };
361 map6 {
362 trip = <&cpu3_alert4>;
363 cooling-device = <&cpu4 3 12>;
364 };
365 };
366 };
367 };
368 };
369
370 &adc {
371 vdd-supply = <&ldo4_reg>;
372 status = "okay";
373 };
374
375 &bus_wcore {
376 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
377 <&nocp_mem1_0>, <&nocp_mem1_1>;
378 vdd-supply = <&buck3_reg>;
379 exynos,saturation-ratio = <100>;
380 status = "okay";
381 };
382
383 &bus_noc {
384 devfreq = <&bus_wcore>;
385 status = "okay";
386 };
387
388 &bus_fsys_apb {
389 devfreq = <&bus_wcore>;
390 status = "okay";
391 };
392
393 &bus_fsys {
394 devfreq = <&bus_wcore>;
395 status = "okay";
396 };
397
398 &bus_fsys2 {
399 devfreq = <&bus_wcore>;
400 status = "okay";
401 };
402
403 &bus_mfc {
404 devfreq = <&bus_wcore>;
405 status = "okay";
406 };
407
408 &bus_gen {
409 devfreq = <&bus_wcore>;
410 status = "okay";
411 };
412
413 &bus_peri {
414 devfreq = <&bus_wcore>;
415 status = "okay";
416 };
417
418 &bus_g2d {
419 devfreq = <&bus_wcore>;
420 status = "okay";
421 };
422
423 &bus_g2d_acp {
424 devfreq = <&bus_wcore>;
425 status = "okay";
426 };
427
428 &bus_jpeg {
429 devfreq = <&bus_wcore>;
430 status = "okay";
431 };
432
433 &bus_jpeg_apb {
434 devfreq = <&bus_wcore>;
435 status = "okay";
436 };
437
438 &bus_disp1_fimd {
439 devfreq = <&bus_wcore>;
440 status = "okay";
441 };
442
443 &bus_disp1 {
444 devfreq = <&bus_wcore>;
445 status = "okay";
446 };
447
448 &bus_gscl_scaler {
449 devfreq = <&bus_wcore>;
450 status = "okay";
451 };
452
453 &bus_mscl {
454 devfreq = <&bus_wcore>;
455 status = "okay";
456 };
457
458 &clock_audss {
459 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
460 <&clock_audss EXYNOS_MOUT_I2S>,
461 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
462 assigned-clock-parents = <&clock CLK_FIN_PLL>,
463 <&clock_audss EXYNOS_MOUT_AUDSS>;
464 assigned-clock-rates = <0>,
465 <0>,
466 <19200000>;
467 };
468
469 &cpu0 {
470 cpu-supply = <&buck6_reg>;
471 };
472
473 &cpu4 {
474 cpu-supply = <&buck2_reg>;
475 };
476
477 &hdmi {
478 status = "okay";
479 ddc = <&i2c_2>;
480 hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&hdmi_hpd_irq>;
483
484 vdd_osc-supply = <&ldo7_reg>;
485 vdd_pll-supply = <&ldo6_reg>;
486 vdd-supply = <&ldo6_reg>;
487 };
488
489 &hdmicec {
490 status = "okay";
491 needs-hpd;
492 };
493
494 &hsi2c_4 {
495 status = "okay";
496
497 s2mps11_pmic@66 {
498 compatible = "samsung,s2mps11-pmic";
499 reg = <0x66>;
500 samsung,s2mps11-acokb-ground;
501
502 interrupt-parent = <&gpx0>;
503 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&s2mps11_irq>;
506
507 s2mps11_osc: clocks {
508 #clock-cells = <1>;
509 clock-output-names = "s2mps11_ap",
510 "s2mps11_cp", "s2mps11_bt";
511 };
512
513 regulators {
514 ldo1_reg: LDO1 {
515 regulator-name = "vdd_ldo1";
516 regulator-min-microvolt = <1000000>;
517 regulator-max-microvolt = <1000000>;
518 regulator-always-on;
519 };
520
521 ldo3_reg: LDO3 {
522 regulator-name = "vddq_mmc0";
523 regulator-min-microvolt = <1800000>;
524 regulator-max-microvolt = <1800000>;
525 };
526
527 ldo4_reg: LDO4 {
528 regulator-name = "vdd_adc";
529 regulator-min-microvolt = <1800000>;
530 regulator-max-microvolt = <1800000>;
531 };
532
533 ldo5_reg: LDO5 {
534 regulator-name = "vdd_ldo5";
535 regulator-min-microvolt = <1800000>;
536 regulator-max-microvolt = <1800000>;
537 regulator-always-on;
538 };
539
540 ldo6_reg: LDO6 {
541 regulator-name = "vdd_ldo6";
542 regulator-min-microvolt = <1000000>;
543 regulator-max-microvolt = <1000000>;
544 regulator-always-on;
545 };
546
547 ldo7_reg: LDO7 {
548 regulator-name = "vdd_ldo7";
549 regulator-min-microvolt = <1800000>;
550 regulator-max-microvolt = <1800000>;
551 regulator-always-on;
552 };
553
554 ldo8_reg: LDO8 {
555 regulator-name = "vdd_ldo8";
556 regulator-min-microvolt = <1800000>;
557 regulator-max-microvolt = <1800000>;
558 regulator-always-on;
559 };
560
561 ldo9_reg: LDO9 {
562 regulator-name = "vdd_ldo9";
563 regulator-min-microvolt = <3000000>;
564 regulator-max-microvolt = <3000000>;
565 regulator-always-on;
566 };
567
568 ldo10_reg: LDO10 {
569 regulator-name = "vdd_ldo10";
570 regulator-min-microvolt = <1800000>;
571 regulator-max-microvolt = <1800000>;
572 regulator-always-on;
573 };
574
575 ldo11_reg: LDO11 {
576 regulator-name = "vdd_ldo11";
577 regulator-min-microvolt = <1000000>;
578 regulator-max-microvolt = <1000000>;
579 regulator-always-on;
580 };
581
582 ldo12_reg: LDO12 {
583 regulator-name = "vdd_ldo12";
584 regulator-min-microvolt = <1800000>;
585 regulator-max-microvolt = <1800000>;
586 regulator-always-on;
587 };
588
589 ldo13_reg: LDO13 {
590 regulator-name = "vddq_mmc2";
591 regulator-min-microvolt = <2800000>;
592 regulator-max-microvolt = <2800000>;
593 };
594
595 ldo15_reg: LDO15 {
596 regulator-name = "vdd_ldo15";
597 regulator-min-microvolt = <3100000>;
598 regulator-max-microvolt = <3100000>;
599 regulator-always-on;
600 };
601
602 ldo16_reg: LDO16 {
603 regulator-name = "vdd_ldo16";
604 regulator-min-microvolt = <2200000>;
605 regulator-max-microvolt = <2200000>;
606 regulator-always-on;
607 };
608
609 ldo17_reg: LDO17 {
610 regulator-name = "tsp_avdd";
611 regulator-min-microvolt = <3300000>;
612 regulator-max-microvolt = <3300000>;
613 regulator-always-on;
614 };
615
616 ldo18_reg: LDO18 {
617 regulator-name = "vdd_emmc_1V8";
618 regulator-min-microvolt = <1800000>;
619 regulator-max-microvolt = <1800000>;
620 };
621
622 ldo19_reg: LDO19 {
623 regulator-name = "vdd_sd";
624 regulator-min-microvolt = <2800000>;
625 regulator-max-microvolt = <2800000>;
626 };
627
628 ldo24_reg: LDO24 {
629 regulator-name = "tsp_io";
630 regulator-min-microvolt = <2800000>;
631 regulator-max-microvolt = <2800000>;
632 regulator-always-on;
633 };
634
635 ldo26_reg: LDO26 {
636 regulator-name = "vdd_ldo26";
637 regulator-min-microvolt = <3000000>;
638 regulator-max-microvolt = <3000000>;
639 regulator-always-on;
640 };
641
642 buck1_reg: BUCK1 {
643 regulator-name = "vdd_mif";
644 regulator-min-microvolt = <800000>;
645 regulator-max-microvolt = <1300000>;
646 regulator-always-on;
647 regulator-boot-on;
648 };
649
650 buck2_reg: BUCK2 {
651 regulator-name = "vdd_arm";
652 regulator-min-microvolt = <800000>;
653 regulator-max-microvolt = <1500000>;
654 regulator-always-on;
655 regulator-boot-on;
656 };
657
658 buck3_reg: BUCK3 {
659 regulator-name = "vdd_int";
660 regulator-min-microvolt = <800000>;
661 regulator-max-microvolt = <1400000>;
662 regulator-always-on;
663 regulator-boot-on;
664 };
665
666 buck4_reg: BUCK4 {
667 regulator-name = "vdd_g3d";
668 regulator-min-microvolt = <800000>;
669 regulator-max-microvolt = <1400000>;
670 regulator-always-on;
671 regulator-boot-on;
672 };
673
674 buck5_reg: BUCK5 {
675 regulator-name = "vdd_mem";
676 regulator-min-microvolt = <800000>;
677 regulator-max-microvolt = <1400000>;
678 regulator-always-on;
679 regulator-boot-on;
680 };
681
682 buck6_reg: BUCK6 {
683 regulator-name = "vdd_kfc";
684 regulator-min-microvolt = <800000>;
685 regulator-max-microvolt = <1500000>;
686 regulator-always-on;
687 regulator-boot-on;
688 };
689
690 buck7_reg: BUCK7 {
691 regulator-name = "vdd_1.0v_ldo";
692 regulator-min-microvolt = <800000>;
693 regulator-max-microvolt = <1500000>;
694 regulator-always-on;
695 regulator-boot-on;
696 };
697
698 buck8_reg: BUCK8 {
699 regulator-name = "vdd_1.8v_ldo";
700 regulator-min-microvolt = <800000>;
701 regulator-max-microvolt = <1500000>;
702 regulator-always-on;
703 regulator-boot-on;
704 };
705
706 buck9_reg: BUCK9 {
707 regulator-name = "vdd_2.8v_ldo";
708 regulator-min-microvolt = <3000000>;
709 regulator-max-microvolt = <3750000>;
710 regulator-always-on;
711 regulator-boot-on;
712 };
713
714 buck10_reg: BUCK10 {
715 regulator-name = "vdd_vmem";
716 regulator-min-microvolt = <2850000>;
717 regulator-max-microvolt = <2850000>;
718 regulator-always-on;
719 regulator-boot-on;
720 };
721 };
722 };
723 };
724
725 &i2c_2 {
726 samsung,i2c-sda-delay = <100>;
727 samsung,i2c-max-bus-freq = <66000>;
728 /* used by HDMI DDC */
729 status = "okay";
730 };
731
732 &mixer {
733 status = "okay";
734 };
735
736 &mmc_0 {
737 status = "okay";
738 mmc-pwrseq = <&emmc_pwrseq>;
739 card-detect-delay = <200>;
740 samsung,dw-mshc-ciu-div = <3>;
741 samsung,dw-mshc-sdr-timing = <0 4>;
742 samsung,dw-mshc-ddr-timing = <0 2>;
743 samsung,dw-mshc-hs400-timing = <0 2>;
744 samsung,read-strobe-delay = <90>;
745 pinctrl-names = "default";
746 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>;
747 bus-width = <8>;
748 cap-mmc-highspeed;
749 mmc-hs200-1_8v;
750 mmc-hs400-1_8v;
751 vmmc-supply = <&ldo18_reg>;
752 vqmmc-supply = <&ldo3_reg>;
753 };
754
755 &mmc_2 {
756 status = "okay";
757 card-detect-delay = <200>;
758 samsung,dw-mshc-ciu-div = <3>;
759 samsung,dw-mshc-sdr-timing = <0 4>;
760 samsung,dw-mshc-ddr-timing = <0 2>;
761 pinctrl-names = "default";
762 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
763 bus-width = <4>;
764 cap-sd-highspeed;
765 vmmc-supply = <&ldo19_reg>;
766 vqmmc-supply = <&ldo13_reg>;
767 };
768
769 &nocp_mem0_0 {
770 status = "okay";
771 };
772
773 &nocp_mem0_1 {
774 status = "okay";
775 };
776
777 &nocp_mem1_0 {
778 status = "okay";
779 };
780
781 &nocp_mem1_1 {
782 status = "okay";
783 };
784
785 &pinctrl_0 {
786 power_key: power-key {
787 samsung,pins = "gpx0-3";
788 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
789 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
790 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
791 };
792
793 hdmi_hpd_irq: hdmi-hpd-irq {
794 samsung,pins = "gpx3-7";
795 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
796 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
797 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
798 };
799
800 s2mps11_irq: s2mps11-irq {
801 samsung,pins = "gpx0-4";
802 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
803 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
804 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
805 };
806 };
807
808 &pinctrl_1 {
809 emmc_nrst_pin: emmc-nrst {
810 samsung,pins = "gpd1-0";
811 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
812 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
813 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
814 };
815 };
816
817 &tmu_cpu0 {
818 vtmu-supply = <&ldo7_reg>;
819 };
820
821 &tmu_cpu1 {
822 vtmu-supply = <&ldo7_reg>;
823 };
824
825 &tmu_cpu2 {
826 vtmu-supply = <&ldo7_reg>;
827 };
828
829 &tmu_cpu3 {
830 vtmu-supply = <&ldo7_reg>;
831 };
832
833 &tmu_gpu {
834 vtmu-supply = <&ldo7_reg>;
835 };
836
837 &rtc {
838 status = "okay";
839 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
840 clock-names = "rtc", "rtc_src";
841 };
842
843 &usbdrd_dwc3_0 {
844 dr_mode = "host";
845 };
846
847 /* usbdrd_dwc3_1 mode customized in each board */
848
849 &usbdrd3_0 {
850 vdd33-supply = <&ldo9_reg>;
851 vdd10-supply = <&ldo11_reg>;
852 };
853
854 &usbdrd3_1 {
855 vdd33-supply = <&ldo9_reg>;
856 vdd10-supply = <&ldo11_reg>;
857 };