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1 /*
2 * Hardkernel Odroid XU3 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2014 Collabora Ltd.
7 * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
8 * Anand Moon <linux.amoon@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <dt-bindings/clock/samsung,s2mps11.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/sound/samsung-i2s.h>
19 #include "exynos5800.dtsi"
20 #include "exynos5422-cpus.dtsi"
21
22 / {
23 memory@40000000 {
24 device_type = "memory";
25 reg = <0x40000000 0x7EA00000>;
26 };
27
28 chosen {
29 stdout-path = "serial2:115200n8";
30 };
31
32 firmware@02073000 {
33 compatible = "samsung,secure-firmware";
34 reg = <0x02073000 0x1000>;
35 };
36
37 fixed-rate-clocks {
38 oscclk {
39 compatible = "samsung,exynos5420-oscclk";
40 clock-frequency = <24000000>;
41 };
42 };
43
44 emmc_pwrseq: pwrseq {
45 pinctrl-0 = <&emmc_nrst_pin>;
46 pinctrl-names = "default";
47 compatible = "mmc-pwrseq-emmc";
48 reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
49 };
50
51 fan0: pwm-fan {
52 compatible = "pwm-fan";
53 pwms = <&pwm 0 20972 0>;
54 cooling-min-state = <0>;
55 cooling-max-state = <3>;
56 #cooling-cells = <2>;
57 cooling-levels = <0 130 170 230>;
58 };
59
60 thermal-zones {
61 cpu0_thermal: cpu0-thermal {
62 thermal-sensors = <&tmu_cpu0 0>;
63 polling-delay-passive = <250>;
64 polling-delay = <0>;
65 trips {
66 cpu_alert0: cpu-alert-0 {
67 temperature = <50000>; /* millicelsius */
68 hysteresis = <5000>; /* millicelsius */
69 type = "active";
70 };
71 cpu_alert1: cpu-alert-1 {
72 temperature = <60000>; /* millicelsius */
73 hysteresis = <5000>; /* millicelsius */
74 type = "active";
75 };
76 cpu_alert2: cpu-alert-2 {
77 temperature = <70000>; /* millicelsius */
78 hysteresis = <5000>; /* millicelsius */
79 type = "active";
80 };
81 cpu_crit0: cpu-crit-0 {
82 temperature = <120000>; /* millicelsius */
83 hysteresis = <0>; /* millicelsius */
84 type = "critical";
85 };
86 /*
87 * Exynos542x supports only 4 trip-points
88 * so for these polling mode is required.
89 * Start polling at temperature level of last
90 * interrupt-driven trip: cpu_alert2
91 */
92 cpu_alert3: cpu-alert-3 {
93 temperature = <70000>; /* millicelsius */
94 hysteresis = <10000>; /* millicelsius */
95 type = "passive";
96 };
97 cpu_alert4: cpu-alert-4 {
98 temperature = <85000>; /* millicelsius */
99 hysteresis = <10000>; /* millicelsius */
100 type = "passive";
101 };
102
103 };
104 cooling-maps {
105 map0 {
106 trip = <&cpu_alert0>;
107 cooling-device = <&fan0 0 1>;
108 };
109 map1 {
110 trip = <&cpu_alert1>;
111 cooling-device = <&fan0 1 2>;
112 };
113 map2 {
114 trip = <&cpu_alert2>;
115 cooling-device = <&fan0 2 3>;
116 };
117 /*
118 * When reaching cpu_alert3, reduce CPU
119 * by 2 steps. On Exynos5422/5800 that would
120 * be: 1600 MHz and 1100 MHz.
121 */
122 map3 {
123 trip = <&cpu_alert3>;
124 cooling-device = <&cpu0 0 2>;
125 };
126 map4 {
127 trip = <&cpu_alert3>;
128 cooling-device = <&cpu4 0 2>;
129 };
130
131 /*
132 * When reaching cpu_alert4, reduce CPU
133 * further, down to 600 MHz (11 steps for big,
134 * 7 steps for LITTLE).
135 */
136 map5 {
137 trip = <&cpu_alert4>;
138 cooling-device = <&cpu0 3 7>;
139 };
140 map6 {
141 trip = <&cpu_alert4>;
142 cooling-device = <&cpu4 3 11>;
143 };
144 };
145 };
146 };
147 };
148
149 &adc {
150 vdd-supply = <&ldo4_reg>;
151 status = "okay";
152 };
153
154 &bus_wcore {
155 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
156 <&nocp_mem1_0>, <&nocp_mem1_1>;
157 vdd-supply = <&buck3_reg>;
158 exynos,saturation-ratio = <100>;
159 status = "okay";
160 };
161
162 &bus_noc {
163 devfreq = <&bus_wcore>;
164 status = "okay";
165 };
166
167 &bus_fsys_apb {
168 devfreq = <&bus_wcore>;
169 status = "okay";
170 };
171
172 &bus_fsys {
173 devfreq = <&bus_wcore>;
174 status = "okay";
175 };
176
177 &bus_fsys2 {
178 devfreq = <&bus_wcore>;
179 status = "okay";
180 };
181
182 &bus_mfc {
183 devfreq = <&bus_wcore>;
184 status = "okay";
185 };
186
187 &bus_gen {
188 devfreq = <&bus_wcore>;
189 status = "okay";
190 };
191
192 &bus_peri {
193 devfreq = <&bus_wcore>;
194 status = "okay";
195 };
196
197 &bus_g2d {
198 devfreq = <&bus_wcore>;
199 status = "okay";
200 };
201
202 &bus_g2d_acp {
203 devfreq = <&bus_wcore>;
204 status = "okay";
205 };
206
207 &bus_jpeg {
208 devfreq = <&bus_wcore>;
209 status = "okay";
210 };
211
212 &bus_jpeg_apb {
213 devfreq = <&bus_wcore>;
214 status = "okay";
215 };
216
217 &bus_disp1_fimd {
218 devfreq = <&bus_wcore>;
219 status = "okay";
220 };
221
222 &bus_disp1 {
223 devfreq = <&bus_wcore>;
224 status = "okay";
225 };
226
227 &bus_gscl_scaler {
228 devfreq = <&bus_wcore>;
229 status = "okay";
230 };
231
232 &bus_mscl {
233 devfreq = <&bus_wcore>;
234 status = "okay";
235 };
236
237 &clock_audss {
238 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
239 <&clock_audss EXYNOS_MOUT_I2S>,
240 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
241 assigned-clock-parents = <&clock CLK_FIN_PLL>,
242 <&clock_audss EXYNOS_MOUT_AUDSS>;
243 assigned-clock-rates = <0>,
244 <0>,
245 <19200000>;
246 };
247
248 &cpu0 {
249 cpu-supply = <&buck6_reg>;
250 };
251
252 &cpu4 {
253 cpu-supply = <&buck2_reg>;
254 };
255
256 &hdmi {
257 status = "okay";
258 hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&hdmi_hpd_irq>;
261
262 vdd_osc-supply = <&ldo7_reg>;
263 vdd_pll-supply = <&ldo6_reg>;
264 vdd-supply = <&ldo6_reg>;
265 };
266
267 &hdmicec {
268 status = "okay";
269 };
270
271 &hsi2c_4 {
272 status = "okay";
273
274 s2mps11_pmic@66 {
275 compatible = "samsung,s2mps11-pmic";
276 reg = <0x66>;
277 samsung,s2mps11-acokb-ground;
278
279 interrupt-parent = <&gpx0>;
280 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&s2mps11_irq>;
283
284 s2mps11_osc: clocks {
285 #clock-cells = <1>;
286 clock-output-names = "s2mps11_ap",
287 "s2mps11_cp", "s2mps11_bt";
288 };
289
290 regulators {
291 ldo1_reg: LDO1 {
292 regulator-name = "vdd_ldo1";
293 regulator-min-microvolt = <1000000>;
294 regulator-max-microvolt = <1000000>;
295 regulator-always-on;
296 };
297
298 ldo3_reg: LDO3 {
299 regulator-name = "vddq_mmc0";
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <1800000>;
302 };
303
304 ldo4_reg: LDO4 {
305 regulator-name = "vdd_adc";
306 regulator-min-microvolt = <1800000>;
307 regulator-max-microvolt = <1800000>;
308 };
309
310 ldo5_reg: LDO5 {
311 regulator-name = "vdd_ldo5";
312 regulator-min-microvolt = <1800000>;
313 regulator-max-microvolt = <1800000>;
314 regulator-always-on;
315 };
316
317 ldo6_reg: LDO6 {
318 regulator-name = "vdd_ldo6";
319 regulator-min-microvolt = <1000000>;
320 regulator-max-microvolt = <1000000>;
321 regulator-always-on;
322 };
323
324 ldo7_reg: LDO7 {
325 regulator-name = "vdd_ldo7";
326 regulator-min-microvolt = <1800000>;
327 regulator-max-microvolt = <1800000>;
328 regulator-always-on;
329 };
330
331 ldo8_reg: LDO8 {
332 regulator-name = "vdd_ldo8";
333 regulator-min-microvolt = <1800000>;
334 regulator-max-microvolt = <1800000>;
335 regulator-always-on;
336 };
337
338 ldo9_reg: LDO9 {
339 regulator-name = "vdd_ldo9";
340 regulator-min-microvolt = <3000000>;
341 regulator-max-microvolt = <3000000>;
342 regulator-always-on;
343 };
344
345 ldo10_reg: LDO10 {
346 regulator-name = "vdd_ldo10";
347 regulator-min-microvolt = <1800000>;
348 regulator-max-microvolt = <1800000>;
349 regulator-always-on;
350 };
351
352 ldo11_reg: LDO11 {
353 regulator-name = "vdd_ldo11";
354 regulator-min-microvolt = <1000000>;
355 regulator-max-microvolt = <1000000>;
356 regulator-always-on;
357 };
358
359 ldo12_reg: LDO12 {
360 regulator-name = "vdd_ldo12";
361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <1800000>;
363 regulator-always-on;
364 };
365
366 ldo13_reg: LDO13 {
367 regulator-name = "vddq_mmc2";
368 regulator-min-microvolt = <2800000>;
369 regulator-max-microvolt = <2800000>;
370 };
371
372 ldo15_reg: LDO15 {
373 regulator-name = "vdd_ldo15";
374 regulator-min-microvolt = <3100000>;
375 regulator-max-microvolt = <3100000>;
376 regulator-always-on;
377 };
378
379 ldo16_reg: LDO16 {
380 regulator-name = "vdd_ldo16";
381 regulator-min-microvolt = <2200000>;
382 regulator-max-microvolt = <2200000>;
383 regulator-always-on;
384 };
385
386 ldo17_reg: LDO17 {
387 regulator-name = "tsp_avdd";
388 regulator-min-microvolt = <3300000>;
389 regulator-max-microvolt = <3300000>;
390 regulator-always-on;
391 };
392
393 ldo18_reg: LDO18 {
394 regulator-name = "vdd_emmc_1V8";
395 regulator-min-microvolt = <1800000>;
396 regulator-max-microvolt = <1800000>;
397 };
398
399 ldo19_reg: LDO19 {
400 regulator-name = "vdd_sd";
401 regulator-min-microvolt = <2800000>;
402 regulator-max-microvolt = <2800000>;
403 };
404
405 ldo24_reg: LDO24 {
406 regulator-name = "tsp_io";
407 regulator-min-microvolt = <2800000>;
408 regulator-max-microvolt = <2800000>;
409 regulator-always-on;
410 };
411
412 ldo26_reg: LDO26 {
413 regulator-name = "vdd_ldo26";
414 regulator-min-microvolt = <3000000>;
415 regulator-max-microvolt = <3000000>;
416 regulator-always-on;
417 };
418
419 buck1_reg: BUCK1 {
420 regulator-name = "vdd_mif";
421 regulator-min-microvolt = <800000>;
422 regulator-max-microvolt = <1300000>;
423 regulator-always-on;
424 regulator-boot-on;
425 };
426
427 buck2_reg: BUCK2 {
428 regulator-name = "vdd_arm";
429 regulator-min-microvolt = <800000>;
430 regulator-max-microvolt = <1500000>;
431 regulator-always-on;
432 regulator-boot-on;
433 };
434
435 buck3_reg: BUCK3 {
436 regulator-name = "vdd_int";
437 regulator-min-microvolt = <800000>;
438 regulator-max-microvolt = <1400000>;
439 regulator-always-on;
440 regulator-boot-on;
441 };
442
443 buck4_reg: BUCK4 {
444 regulator-name = "vdd_g3d";
445 regulator-min-microvolt = <800000>;
446 regulator-max-microvolt = <1400000>;
447 regulator-always-on;
448 regulator-boot-on;
449 };
450
451 buck5_reg: BUCK5 {
452 regulator-name = "vdd_mem";
453 regulator-min-microvolt = <800000>;
454 regulator-max-microvolt = <1400000>;
455 regulator-always-on;
456 regulator-boot-on;
457 };
458
459 buck6_reg: BUCK6 {
460 regulator-name = "vdd_kfc";
461 regulator-min-microvolt = <800000>;
462 regulator-max-microvolt = <1500000>;
463 regulator-always-on;
464 regulator-boot-on;
465 };
466
467 buck7_reg: BUCK7 {
468 regulator-name = "vdd_1.0v_ldo";
469 regulator-min-microvolt = <800000>;
470 regulator-max-microvolt = <1500000>;
471 regulator-always-on;
472 regulator-boot-on;
473 };
474
475 buck8_reg: BUCK8 {
476 regulator-name = "vdd_1.8v_ldo";
477 regulator-min-microvolt = <800000>;
478 regulator-max-microvolt = <1500000>;
479 regulator-always-on;
480 regulator-boot-on;
481 };
482
483 buck9_reg: BUCK9 {
484 regulator-name = "vdd_2.8v_ldo";
485 regulator-min-microvolt = <3000000>;
486 regulator-max-microvolt = <3750000>;
487 regulator-always-on;
488 regulator-boot-on;
489 };
490
491 buck10_reg: BUCK10 {
492 regulator-name = "vdd_vmem";
493 regulator-min-microvolt = <2850000>;
494 regulator-max-microvolt = <2850000>;
495 regulator-always-on;
496 regulator-boot-on;
497 };
498 };
499 };
500 };
501
502 &i2c_2 {
503 samsung,i2c-sda-delay = <100>;
504 samsung,i2c-max-bus-freq = <66000>;
505 status = "okay";
506
507 hdmiddc@50 {
508 compatible = "samsung,exynos4210-hdmiddc";
509 reg = <0x50>;
510 };
511 };
512
513 &mmc_0 {
514 status = "okay";
515 mmc-pwrseq = <&emmc_pwrseq>;
516 card-detect-delay = <200>;
517 samsung,dw-mshc-ciu-div = <3>;
518 samsung,dw-mshc-sdr-timing = <0 4>;
519 samsung,dw-mshc-ddr-timing = <0 2>;
520 samsung,dw-mshc-hs400-timing = <0 2>;
521 samsung,read-strobe-delay = <90>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>;
524 bus-width = <8>;
525 cap-mmc-highspeed;
526 mmc-hs200-1_8v;
527 mmc-hs400-1_8v;
528 vmmc-supply = <&ldo18_reg>;
529 vqmmc-supply = <&ldo3_reg>;
530 };
531
532 &mmc_2 {
533 status = "okay";
534 card-detect-delay = <200>;
535 samsung,dw-mshc-ciu-div = <3>;
536 samsung,dw-mshc-sdr-timing = <0 4>;
537 samsung,dw-mshc-ddr-timing = <0 2>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
540 bus-width = <4>;
541 cap-sd-highspeed;
542 vmmc-supply = <&ldo19_reg>;
543 vqmmc-supply = <&ldo13_reg>;
544 };
545
546 &nocp_mem0_0 {
547 status = "okay";
548 };
549
550 &nocp_mem0_1 {
551 status = "okay";
552 };
553
554 &nocp_mem1_0 {
555 status = "okay";
556 };
557
558 &nocp_mem1_1 {
559 status = "okay";
560 };
561
562 &pinctrl_0 {
563 hdmi_hpd_irq: hdmi-hpd-irq {
564 samsung,pins = "gpx3-7";
565 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
566 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
567 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
568 };
569
570 s2mps11_irq: s2mps11-irq {
571 samsung,pins = "gpx0-4";
572 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
573 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
574 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
575 };
576 };
577
578 &pinctrl_1 {
579 emmc_nrst_pin: emmc-nrst {
580 samsung,pins = "gpd1-0";
581 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
582 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
583 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
584 };
585 };
586
587 &tmu_cpu0 {
588 vtmu-supply = <&ldo7_reg>;
589 };
590
591 &tmu_cpu1 {
592 vtmu-supply = <&ldo7_reg>;
593 };
594
595 &tmu_cpu2 {
596 vtmu-supply = <&ldo7_reg>;
597 };
598
599 &tmu_cpu3 {
600 vtmu-supply = <&ldo7_reg>;
601 };
602
603 &tmu_gpu {
604 vtmu-supply = <&ldo7_reg>;
605 };
606
607 &rtc {
608 status = "okay";
609 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
610 clock-names = "rtc", "rtc_src";
611 };
612
613 &usbdrd_dwc3_0 {
614 dr_mode = "host";
615 };
616
617 /* usbdrd_dwc3_1 mode customized in each board */
618
619 &usbdrd3_0 {
620 vdd33-supply = <&ldo9_reg>;
621 vdd10-supply = <&ldo11_reg>;
622 };
623
624 &usbdrd3_1 {
625 vdd33-supply = <&ldo9_reg>;
626 vdd10-supply = <&ldo11_reg>;
627 };