arch/arm/boot/dts/highbank.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2011-2012 Calxeda, Inc.
   4  */
   5
   6 /dts-v1/;
   7
   8 /* First 4KB has pen for secondary cores. */
   9 /memreserve/ 0x00000000 0x0001000;
  10
  11 / {
  12         model = "Calxeda Highbank";
  13         compatible = "calxeda,highbank";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16         clock-ranges;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu@900 {
  23                         compatible = "arm,cortex-a9";
  24                         device_type = "cpu";
  25                         reg = <0x900>;
  26                         next-level-cache = <&L2>;
  27                         clocks = <&a9pll>;
  28                         clock-names = "cpu";
  29                         operating-points = <
  30                                 /* kHz    ignored */
  31                                  1300000  1000000
  32                                  1200000  1000000
  33                                  1100000  1000000
  34                                   800000  1000000
  35                                   400000  1000000
  36                                   200000  1000000
  37                         >;
  38                         clock-latency = <100000>;
  39                 };
  40
  41                 cpu@901 {
  42                         compatible = "arm,cortex-a9";
  43                         device_type = "cpu";
  44                         reg = <0x901>;
  45                         next-level-cache = <&L2>;
  46                         clocks = <&a9pll>;
  47                         clock-names = "cpu";
  48                         operating-points = <
  49                                 /* kHz    ignored */
  50                                  1300000  1000000
  51                                  1200000  1000000
  52                                  1100000  1000000
  53                                   800000  1000000
  54                                   400000  1000000
  55                                   200000  1000000
  56                         >;
  57                         clock-latency = <100000>;
  58                 };
  59
  60                 cpu@902 {
  61                         compatible = "arm,cortex-a9";
  62                         device_type = "cpu";
  63                         reg = <0x902>;
  64                         next-level-cache = <&L2>;
  65                         clocks = <&a9pll>;
  66                         clock-names = "cpu";
  67                         operating-points = <
  68                                 /* kHz    ignored */
  69                                  1300000  1000000
  70                                  1200000  1000000
  71                                  1100000  1000000
  72                                   800000  1000000
  73                                   400000  1000000
  74                                   200000  1000000
  75                         >;
  76                         clock-latency = <100000>;
  77                 };
  78
  79                 cpu@903 {
  80                         compatible = "arm,cortex-a9";
  81                         device_type = "cpu";
  82                         reg = <0x903>;
  83                         next-level-cache = <&L2>;
  84                         clocks = <&a9pll>;
  85                         clock-names = "cpu";
  86                         operating-points = <
  87                                 /* kHz    ignored */
  88                                  1300000  1000000
  89                                  1200000  1000000
  90                                  1100000  1000000
  91                                   800000  1000000
  92                                   400000  1000000
  93                                   200000  1000000
  94                         >;
  95                         clock-latency = <100000>;
  96                 };
  97         };
  98
  99         memory {
 100                 name = "memory";
 101                 device_type = "memory";
 102                 reg = <0x00000000 0xff900000>;
 103         };
 104
 105         soc {
 106                 ranges = <0x00000000 0x00000000 0xffffffff>;
 107
 108                 memory-controller@fff00000 {
 109                         compatible = "calxeda,hb-ddr-ctrl";
 110                         reg = <0xfff00000 0x1000>;
 111                         interrupts = <0 91 4>;
 112                 };
 113
 114                 timer@fff10600 {
 115                         compatible = "arm,cortex-a9-twd-timer";
 116                         reg = <0xfff10600 0x20>;
 117                         interrupts = <1 13 0xf01>;
 118                         clocks = <&a9periphclk>;
 119                 };
 120
 121                 watchdog@fff10620 {
 122                         compatible = "arm,cortex-a9-twd-wdt";
 123                         reg = <0xfff10620 0x20>;
 124                         interrupts = <1 14 0xf01>;
 125                         clocks = <&a9periphclk>;
 126                 };
 127
 128                 intc: interrupt-controller@fff11000 {
 129                         compatible = "arm,cortex-a9-gic";
 130                         #interrupt-cells = <3>;
 131                         #size-cells = <0>;
 132                         #address-cells = <1>;
 133                         interrupt-controller;
 134                         reg = <0xfff11000 0x1000>,
 135                               <0xfff10100 0x100>;
 136                 };
 137
 138                 L2: l2-cache {
 139                         compatible = "arm,pl310-cache";
 140                         reg = <0xfff12000 0x1000>;
 141                         interrupts = <0 70 4>;
 142                         cache-unified;
 143                         cache-level = <2>;
 144                 };
 145
 146                 pmu {
 147                         compatible = "arm,cortex-a9-pmu";
 148                         interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
 149                 };
 150
 151
 152                 sregs@fff3c200 {
 153                         compatible = "calxeda,hb-sregs-l2-ecc";
 154                         reg = <0xfff3c200 0x100>;
 155                         interrupts = <0 71 4  0 72 4>;
 156                 };
 157
 158         };
 159 };
 160
 161 /include/ "ecx-common.dtsi"