2 * Copyright 2012 Sascha Hauer, Pengutronix
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include "imx27-pinfunc.h"
14 #include <dt-bindings/clock/imx27-clock.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
44 aitc: aitc-interrupt-controller@e0000000 {
45 compatible = "fsl,imx27-aitc", "fsl,avic";
47 #interrupt-cells = <1>;
48 reg = <0x10040000 0x1000>;
56 compatible = "fsl,imx-osc26m", "fixed-clock";
58 clock-frequency = <26000000>;
68 compatible = "arm,arm926ej-s";
74 clock-latency = <62500>;
75 clocks = <&clks IMX27_CLK_CPU_DIV>;
76 voltage-tolerance = <5>;
83 compatible = "simple-bus";
84 interrupt-parent = <&aitc>;
87 aipi@10000000 { /* AIPI1 */
88 compatible = "fsl,aipi-bus", "simple-bus";
91 reg = <0x10000000 0x20000>;
95 compatible = "fsl,imx27-dma";
96 reg = <0x10001000 0x1000>;
98 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
99 <&clks IMX27_CLK_DMA_AHB_GATE>;
100 clock-names = "ipg", "ahb";
102 #dma-channels = <16>;
105 wdog: wdog@10002000 {
106 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
107 reg = <0x10002000 0x1000>;
109 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
112 gpt1: timer@10003000 {
113 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
114 reg = <0x10003000 0x1000>;
116 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
117 <&clks IMX27_CLK_PER1_GATE>;
118 clock-names = "ipg", "per";
121 gpt2: timer@10004000 {
122 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
123 reg = <0x10004000 0x1000>;
125 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
126 <&clks IMX27_CLK_PER1_GATE>;
127 clock-names = "ipg", "per";
130 gpt3: timer@10005000 {
131 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
132 reg = <0x10005000 0x1000>;
134 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
135 <&clks IMX27_CLK_PER1_GATE>;
136 clock-names = "ipg", "per";
141 compatible = "fsl,imx27-pwm";
142 reg = <0x10006000 0x1000>;
144 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
145 <&clks IMX27_CLK_PER1_GATE>;
146 clock-names = "ipg", "per";
150 compatible = "fsl,imx21-rtc";
151 reg = <0x10007000 0x1000>;
153 clocks = <&clks IMX27_CLK_CKIL>,
154 <&clks IMX27_CLK_RTC_IPG_GATE>;
155 clock-names = "ref", "ipg";
159 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
160 reg = <0x10008000 0x1000>;
162 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
166 owire: owire@10009000 {
167 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
168 reg = <0x10009000 0x1000>;
169 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
173 uart1: serial@1000a000 {
174 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
175 reg = <0x1000a000 0x1000>;
177 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
178 <&clks IMX27_CLK_PER1_GATE>;
179 clock-names = "ipg", "per";
183 uart2: serial@1000b000 {
184 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
185 reg = <0x1000b000 0x1000>;
187 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
188 <&clks IMX27_CLK_PER1_GATE>;
189 clock-names = "ipg", "per";
193 uart3: serial@1000c000 {
194 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
195 reg = <0x1000c000 0x1000>;
197 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
198 <&clks IMX27_CLK_PER1_GATE>;
199 clock-names = "ipg", "per";
203 uart4: serial@1000d000 {
204 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
205 reg = <0x1000d000 0x1000>;
207 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
208 <&clks IMX27_CLK_PER1_GATE>;
209 clock-names = "ipg", "per";
213 cspi1: cspi@1000e000 {
214 #address-cells = <1>;
216 compatible = "fsl,imx27-cspi";
217 reg = <0x1000e000 0x1000>;
219 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
220 <&clks IMX27_CLK_PER2_GATE>;
221 clock-names = "ipg", "per";
225 cspi2: cspi@1000f000 {
226 #address-cells = <1>;
228 compatible = "fsl,imx27-cspi";
229 reg = <0x1000f000 0x1000>;
231 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
232 <&clks IMX27_CLK_PER2_GATE>;
233 clock-names = "ipg", "per";
238 #sound-dai-cells = <0>;
239 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
240 reg = <0x10010000 0x1000>;
242 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
243 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
244 dma-names = "rx0", "tx0", "rx1", "tx1";
245 fsl,fifo-depth = <8>;
250 #sound-dai-cells = <0>;
251 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
252 reg = <0x10011000 0x1000>;
254 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
255 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
256 dma-names = "rx0", "tx0", "rx1", "tx1";
257 fsl,fifo-depth = <8>;
262 #address-cells = <1>;
264 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
265 reg = <0x10012000 0x1000>;
267 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
271 sdhci1: sdhci@10013000 {
272 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
273 reg = <0x10013000 0x1000>;
275 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
276 <&clks IMX27_CLK_PER2_GATE>;
277 clock-names = "ipg", "per";
283 sdhci2: sdhci@10014000 {
284 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
285 reg = <0x10014000 0x1000>;
287 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
288 <&clks IMX27_CLK_PER2_GATE>;
289 clock-names = "ipg", "per";
295 iomuxc: iomuxc@10015000 {
296 compatible = "fsl,imx27-iomuxc";
297 reg = <0x10015000 0x600>;
298 #address-cells = <1>;
302 gpio1: gpio@10015000 {
303 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
304 reg = <0x10015000 0x100>;
305 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
313 gpio2: gpio@10015100 {
314 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
315 reg = <0x10015100 0x100>;
316 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
324 gpio3: gpio@10015200 {
325 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
326 reg = <0x10015200 0x100>;
327 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
335 gpio4: gpio@10015300 {
336 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
337 reg = <0x10015300 0x100>;
338 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
346 gpio5: gpio@10015400 {
347 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
348 reg = <0x10015400 0x100>;
349 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
357 gpio6: gpio@10015500 {
358 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
359 reg = <0x10015500 0x100>;
360 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
364 interrupt-controller;
365 #interrupt-cells = <2>;
369 audmux: audmux@10016000 {
370 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
371 reg = <0x10016000 0x1000>;
372 clocks = <&clks IMX27_CLK_DUMMY>;
373 clock-names = "audmux";
377 cspi3: cspi@10017000 {
378 #address-cells = <1>;
380 compatible = "fsl,imx27-cspi";
381 reg = <0x10017000 0x1000>;
383 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
384 <&clks IMX27_CLK_PER2_GATE>;
385 clock-names = "ipg", "per";
389 gpt4: timer@10019000 {
390 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
391 reg = <0x10019000 0x1000>;
393 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
394 <&clks IMX27_CLK_PER1_GATE>;
395 clock-names = "ipg", "per";
398 gpt5: timer@1001a000 {
399 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
400 reg = <0x1001a000 0x1000>;
402 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
403 <&clks IMX27_CLK_PER1_GATE>;
404 clock-names = "ipg", "per";
407 uart5: serial@1001b000 {
408 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
409 reg = <0x1001b000 0x1000>;
411 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
412 <&clks IMX27_CLK_PER1_GATE>;
413 clock-names = "ipg", "per";
417 uart6: serial@1001c000 {
418 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
419 reg = <0x1001c000 0x1000>;
421 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
422 <&clks IMX27_CLK_PER1_GATE>;
423 clock-names = "ipg", "per";
428 #address-cells = <1>;
430 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
431 reg = <0x1001d000 0x1000>;
433 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
437 sdhci3: sdhci@1001e000 {
438 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
439 reg = <0x1001e000 0x1000>;
441 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
442 <&clks IMX27_CLK_PER2_GATE>;
443 clock-names = "ipg", "per";
449 gpt6: timer@1001f000 {
450 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
451 reg = <0x1001f000 0x1000>;
453 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
454 <&clks IMX27_CLK_PER1_GATE>;
455 clock-names = "ipg", "per";
459 aipi@10020000 { /* AIPI2 */
460 compatible = "fsl,aipi-bus", "simple-bus";
461 #address-cells = <1>;
463 reg = <0x10020000 0x20000>;
467 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
469 reg = <0x10021000 0x1000>;
470 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
471 <&clks IMX27_CLK_LCDC_AHB_GATE>,
472 <&clks IMX27_CLK_PER3_GATE>;
473 clock-names = "ipg", "ahb", "per";
477 coda: coda@10023000 {
478 compatible = "fsl,imx27-vpu", "cnm,codadx6";
479 reg = <0x10023000 0x0200>;
481 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
482 <&clks IMX27_CLK_VPU_AHB_GATE>;
483 clock-names = "per", "ahb";
487 usbotg: usb@10024000 {
488 compatible = "fsl,imx27-usb";
489 reg = <0x10024000 0x200>;
491 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
492 <&clks IMX27_CLK_USB_AHB_GATE>,
493 <&clks IMX27_CLK_USB_DIV>;
494 clock-names = "ipg", "ahb", "per";
495 fsl,usbmisc = <&usbmisc 0>;
499 usbh1: usb@10024200 {
500 compatible = "fsl,imx27-usb";
501 reg = <0x10024200 0x200>;
503 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
504 <&clks IMX27_CLK_USB_AHB_GATE>,
505 <&clks IMX27_CLK_USB_DIV>;
506 clock-names = "ipg", "ahb", "per";
507 fsl,usbmisc = <&usbmisc 1>;
512 usbh2: usb@10024400 {
513 compatible = "fsl,imx27-usb";
514 reg = <0x10024400 0x200>;
516 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
517 <&clks IMX27_CLK_USB_AHB_GATE>,
518 <&clks IMX27_CLK_USB_DIV>;
519 clock-names = "ipg", "ahb", "per";
520 fsl,usbmisc = <&usbmisc 2>;
525 usbmisc: usbmisc@10024600 {
527 compatible = "fsl,imx27-usbmisc";
528 reg = <0x10024600 0x200>;
531 sahara2: sahara@10025000 {
532 compatible = "fsl,imx27-sahara";
533 reg = <0x10025000 0x1000>;
535 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
536 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
537 clock-names = "ipg", "ahb";
541 compatible = "fsl,imx27-ccm";
542 reg = <0x10027000 0x1000>;
547 compatible = "fsl,imx27-iim";
548 reg = <0x10028000 0x1000>;
550 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
553 fec: ethernet@1002b000 {
554 compatible = "fsl,imx27-fec";
555 reg = <0x1002b000 0x1000>;
557 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
558 <&clks IMX27_CLK_FEC_AHB_GATE>;
559 clock-names = "ipg", "ahb";
565 #address-cells = <1>;
567 compatible = "fsl,imx27-nand";
568 reg = <0xd8000000 0x1000>;
570 clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
574 weim: weim@d8002000 {
575 #address-cells = <2>;
577 compatible = "fsl,imx27-weim";
578 reg = <0xd8002000 0x1000>;
579 clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
581 0 0 0xc0000000 0x08000000
582 1 0 0xc8000000 0x08000000
583 2 0 0xd0000000 0x02000000
584 3 0 0xd2000000 0x02000000
585 4 0 0xd4000000 0x02000000
586 5 0 0xd6000000 0x02000000
591 iram: iram@ffff4c00 {
592 compatible = "mmio-sram";
593 reg = <0xffff4c00 0xb400>;