arch/arm/boot/dts/imx27.dtsi

   1 /*
   2  * Copyright 2012 Sascha Hauer, Pengutronix
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include "skeleton.dtsi"
  13 #include "imx27-pinfunc.h"
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16
  17 / {
  18         aliases {
  19                 gpio0 = &gpio1;
  20                 gpio1 = &gpio2;
  21                 gpio2 = &gpio3;
  22                 gpio3 = &gpio4;
  23                 gpio4 = &gpio5;
  24                 gpio5 = &gpio6;
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30                 serial3 = &uart4;
  31                 serial4 = &uart5;
  32                 serial5 = &uart6;
  33                 spi0 = &cspi1;
  34                 spi1 = &cspi2;
  35                 spi2 = &cspi3;
  36         };
  37
  38         aitc: aitc-interrupt-controller@e0000000 {
  39                 compatible = "fsl,imx27-aitc", "fsl,avic";
  40                 interrupt-controller;
  41                 #interrupt-cells = <1>;
  42                 reg = <0x10040000 0x1000>;
  43         };
  44
  45         clocks {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48
  49                 osc26m {
  50                         compatible = "fsl,imx-osc26m", "fixed-clock";
  51                         clock-frequency = <26000000>;
  52                 };
  53         };
  54
  55         cpus {
  56                 #size-cells = <0>;
  57                 #address-cells = <1>;
  58
  59                 cpu: cpu@0 {
  60                         device_type = "cpu";
  61                         compatible = "arm,arm926ej-s";
  62                         operating-points = <
  63                                 /* kHz uV */
  64                                 266000 1300000
  65                                 399000 1450000
  66                         >;
  67                         clock-latency = <62500>;
  68                         clocks = <&clks 18>;
  69                         voltage-tolerance = <5>;
  70                 };
  71         };
  72
  73         soc {
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 compatible = "simple-bus";
  77                 interrupt-parent = <&aitc>;
  78                 ranges;
  79
  80                 aipi@10000000 { /* AIPI1 */
  81                         compatible = "fsl,aipi-bus", "simple-bus";
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84                         reg = <0x10000000 0x20000>;
  85                         ranges;
  86
  87                         dma: dma@10001000 {
  88                                 compatible = "fsl,imx27-dma";
  89                                 reg = <0x10001000 0x1000>;
  90                                 interrupts = <32>;
  91                                 clocks = <&clks 50>, <&clks 70>;
  92                                 clock-names = "ipg", "ahb";
  93                                 #dma-cells = <1>;
  94                                 #dma-channels = <16>;
  95                         };
  96
  97                         wdog: wdog@10002000 {
  98                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
  99                                 reg = <0x10002000 0x1000>;
 100                                 interrupts = <27>;
 101                                 clocks = <&clks 74>;
 102                         };
 103
 104                         gpt1: timer@10003000 {
 105                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 106                                 reg = <0x10003000 0x1000>;
 107                                 interrupts = <26>;
 108                                 clocks = <&clks 46>, <&clks 61>;
 109                                 clock-names = "ipg", "per";
 110                         };
 111
 112                         gpt2: timer@10004000 {
 113                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 114                                 reg = <0x10004000 0x1000>;
 115                                 interrupts = <25>;
 116                                 clocks = <&clks 45>, <&clks 61>;
 117                                 clock-names = "ipg", "per";
 118                         };
 119
 120                         gpt3: timer@10005000 {
 121                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 122                                 reg = <0x10005000 0x1000>;
 123                                 interrupts = <24>;
 124                                 clocks = <&clks 44>, <&clks 61>;
 125                                 clock-names = "ipg", "per";
 126                         };
 127
 128                         pwm: pwm@10006000 {
 129                                 #pwm-cells = <2>;
 130                                 compatible = "fsl,imx27-pwm";
 131                                 reg = <0x10006000 0x1000>;
 132                                 interrupts = <23>;
 133                                 clocks = <&clks 34>, <&clks 61>;
 134                                 clock-names = "ipg", "per";
 135                         };
 136
 137                         kpp: kpp@10008000 {
 138                                 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
 139                                 reg = <0x10008000 0x1000>;
 140                                 interrupts = <21>;
 141                                 clocks = <&clks 37>;
 142                                 status = "disabled";
 143                         };
 144
 145                         owire: owire@10009000 {
 146                                 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
 147                                 reg = <0x10009000 0x1000>;
 148                                 clocks = <&clks 35>;
 149                                 status = "disabled";
 150                         };
 151
 152                         uart1: serial@1000a000 {
 153                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 154                                 reg = <0x1000a000 0x1000>;
 155                                 interrupts = <20>;
 156                                 clocks = <&clks 81>, <&clks 61>;
 157                                 clock-names = "ipg", "per";
 158                                 status = "disabled";
 159                         };
 160
 161                         uart2: serial@1000b000 {
 162                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 163                                 reg = <0x1000b000 0x1000>;
 164                                 interrupts = <19>;
 165                                 clocks = <&clks 80>, <&clks 61>;
 166                                 clock-names = "ipg", "per";
 167                                 status = "disabled";
 168                         };
 169
 170                         uart3: serial@1000c000 {
 171                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 172                                 reg = <0x1000c000 0x1000>;
 173                                 interrupts = <18>;
 174                                 clocks = <&clks 79>, <&clks 61>;
 175                                 clock-names = "ipg", "per";
 176                                 status = "disabled";
 177                         };
 178
 179                         uart4: serial@1000d000 {
 180                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 181                                 reg = <0x1000d000 0x1000>;
 182                                 interrupts = <17>;
 183                                 clocks = <&clks 78>, <&clks 61>;
 184                                 clock-names = "ipg", "per";
 185                                 status = "disabled";
 186                         };
 187
 188                         cspi1: cspi@1000e000 {
 189                                 #address-cells = <1>;
 190                                 #size-cells = <0>;
 191                                 compatible = "fsl,imx27-cspi";
 192                                 reg = <0x1000e000 0x1000>;
 193                                 interrupts = <16>;
 194                                 clocks = <&clks 53>, <&clks 60>;
 195                                 clock-names = "ipg", "per";
 196                                 status = "disabled";
 197                         };
 198
 199                         cspi2: cspi@1000f000 {
 200                                 #address-cells = <1>;
 201                                 #size-cells = <0>;
 202                                 compatible = "fsl,imx27-cspi";
 203                                 reg = <0x1000f000 0x1000>;
 204                                 interrupts = <15>;
 205                                 clocks = <&clks 52>, <&clks 60>;
 206                                 clock-names = "ipg", "per";
 207                                 status = "disabled";
 208                         };
 209
 210                         ssi1: ssi@10010000 {
 211                                 #sound-dai-cells = <0>;
 212                                 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
 213                                 reg = <0x10010000 0x1000>;
 214                                 interrupts = <14>;
 215                                 clocks = <&clks 26>;
 216                                 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
 217                                 dma-names = "rx0", "tx0", "rx1", "tx1";
 218                                 fsl,fifo-depth = <8>;
 219                                 status = "disabled";
 220                         };
 221
 222                         ssi2: ssi@10011000 {
 223                                 #sound-dai-cells = <0>;
 224                                 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
 225                                 reg = <0x10011000 0x1000>;
 226                                 interrupts = <13>;
 227                                 clocks = <&clks 25>;
 228                                 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
 229                                 dma-names = "rx0", "tx0", "rx1", "tx1";
 230                                 fsl,fifo-depth = <8>;
 231                                 status = "disabled";
 232                         };
 233
 234                         i2c1: i2c@10012000 {
 235                                 #address-cells = <1>;
 236                                 #size-cells = <0>;
 237                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 238                                 reg = <0x10012000 0x1000>;
 239                                 interrupts = <12>;
 240                                 clocks = <&clks 40>;
 241                                 status = "disabled";
 242                         };
 243
 244                         sdhci1: sdhci@10013000 {
 245                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 246                                 reg = <0x10013000 0x1000>;
 247                                 interrupts = <11>;
 248                                 clocks = <&clks 30>, <&clks 60>;
 249                                 clock-names = "ipg", "per";
 250                                 dmas = <&dma 7>;
 251                                 dma-names = "rx-tx";
 252                                 status = "disabled";
 253                         };
 254
 255                         sdhci2: sdhci@10014000 {
 256                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 257                                 reg = <0x10014000 0x1000>;
 258                                 interrupts = <10>;
 259                                 clocks = <&clks 29>, <&clks 60>;
 260                                 clock-names = "ipg", "per";
 261                                 dmas = <&dma 6>;
 262                                 dma-names = "rx-tx";
 263                                 status = "disabled";
 264                         };
 265
 266                         iomuxc: iomuxc@10015000 {
 267                                 compatible = "fsl,imx27-iomuxc";
 268                                 reg = <0x10015000 0x600>;
 269                                 #address-cells = <1>;
 270                                 #size-cells = <1>;
 271                                 ranges;
 272
 273                                 gpio1: gpio@10015000 {
 274                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 275                                         reg = <0x10015000 0x100>;
 276                                         interrupts = <8>;
 277                                         gpio-controller;
 278                                         #gpio-cells = <2>;
 279                                         interrupt-controller;
 280                                         #interrupt-cells = <2>;
 281                                 };
 282
 283                                 gpio2: gpio@10015100 {
 284                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 285                                         reg = <0x10015100 0x100>;
 286                                         interrupts = <8>;
 287                                         gpio-controller;
 288                                         #gpio-cells = <2>;
 289                                         interrupt-controller;
 290                                         #interrupt-cells = <2>;
 291                                 };
 292
 293                                 gpio3: gpio@10015200 {
 294                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 295                                         reg = <0x10015200 0x100>;
 296                                         interrupts = <8>;
 297                                         gpio-controller;
 298                                         #gpio-cells = <2>;
 299                                         interrupt-controller;
 300                                         #interrupt-cells = <2>;
 301                                 };
 302
 303                                 gpio4: gpio@10015300 {
 304                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 305                                         reg = <0x10015300 0x100>;
 306                                         interrupts = <8>;
 307                                         gpio-controller;
 308                                         #gpio-cells = <2>;
 309                                         interrupt-controller;
 310                                         #interrupt-cells = <2>;
 311                                 };
 312
 313                                 gpio5: gpio@10015400 {
 314                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 315                                         reg = <0x10015400 0x100>;
 316                                         interrupts = <8>;
 317                                         gpio-controller;
 318                                         #gpio-cells = <2>;
 319                                         interrupt-controller;
 320                                         #interrupt-cells = <2>;
 321                                 };
 322
 323                                 gpio6: gpio@10015500 {
 324                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 325                                         reg = <0x10015500 0x100>;
 326                                         interrupts = <8>;
 327                                         gpio-controller;
 328                                         #gpio-cells = <2>;
 329                                         interrupt-controller;
 330                                         #interrupt-cells = <2>;
 331                                 };
 332                         };
 333
 334                         audmux: audmux@10016000 {
 335                                 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
 336                                 reg = <0x10016000 0x1000>;
 337                                 clocks = <&clks 0>;
 338                                 clock-names = "audmux";
 339                                 status = "disabled";
 340                         };
 341
 342                         cspi3: cspi@10017000 {
 343                                 #address-cells = <1>;
 344                                 #size-cells = <0>;
 345                                 compatible = "fsl,imx27-cspi";
 346                                 reg = <0x10017000 0x1000>;
 347                                 interrupts = <6>;
 348                                 clocks = <&clks 51>, <&clks 60>;
 349                                 clock-names = "ipg", "per";
 350                                 status = "disabled";
 351                         };
 352
 353                         gpt4: timer@10019000 {
 354                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 355                                 reg = <0x10019000 0x1000>;
 356                                 interrupts = <4>;
 357                                 clocks = <&clks 43>, <&clks 61>;
 358                                 clock-names = "ipg", "per";
 359                         };
 360
 361                         gpt5: timer@1001a000 {
 362                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 363                                 reg = <0x1001a000 0x1000>;
 364                                 interrupts = <3>;
 365                                 clocks = <&clks 42>, <&clks 61>;
 366                                 clock-names = "ipg", "per";
 367                         };
 368
 369                         uart5: serial@1001b000 {
 370                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 371                                 reg = <0x1001b000 0x1000>;
 372                                 interrupts = <49>;
 373                                 clocks = <&clks 77>, <&clks 61>;
 374                                 clock-names = "ipg", "per";
 375                                 status = "disabled";
 376                         };
 377
 378                         uart6: serial@1001c000 {
 379                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 380                                 reg = <0x1001c000 0x1000>;
 381                                 interrupts = <48>;
 382                                 clocks = <&clks 78>, <&clks 61>;
 383                                 clock-names = "ipg", "per";
 384                                 status = "disabled";
 385                         };
 386
 387                         i2c2: i2c@1001d000 {
 388                                 #address-cells = <1>;
 389                                 #size-cells = <0>;
 390                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 391                                 reg = <0x1001d000 0x1000>;
 392                                 interrupts = <1>;
 393                                 clocks = <&clks 39>;
 394                                 status = "disabled";
 395                         };
 396
 397                         sdhci3: sdhci@1001e000 {
 398                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 399                                 reg = <0x1001e000 0x1000>;
 400                                 interrupts = <9>;
 401                                 clocks = <&clks 28>, <&clks 60>;
 402                                 clock-names = "ipg", "per";
 403                                 dmas = <&dma 36>;
 404                                 dma-names = "rx-tx";
 405                                 status = "disabled";
 406                         };
 407
 408                         gpt6: timer@1001f000 {
 409                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
 410                                 reg = <0x1001f000 0x1000>;
 411                                 interrupts = <2>;
 412                                 clocks = <&clks 41>, <&clks 61>;
 413                                 clock-names = "ipg", "per";
 414                         };
 415                 };
 416
 417                 aipi@10020000 { /* AIPI2 */
 418                         compatible = "fsl,aipi-bus", "simple-bus";
 419                         #address-cells = <1>;
 420                         #size-cells = <1>;
 421                         reg = <0x10020000 0x20000>;
 422                         ranges;
 423
 424                         fb: fb@10021000 {
 425                                 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
 426                                 interrupts = <61>;
 427                                 reg = <0x10021000 0x1000>;
 428                                 clocks = <&clks 36>, <&clks 65>, <&clks 59>;
 429                                 clock-names = "ipg", "ahb", "per";
 430                                 status = "disabled";
 431                         };
 432
 433                         coda: coda@10023000 {
 434                                 compatible = "fsl,imx27-vpu";
 435                                 reg = <0x10023000 0x0200>;
 436                                 interrupts = <53>;
 437                                 clocks = <&clks 57>, <&clks 66>;
 438                                 clock-names = "per", "ahb";
 439                                 iram = <&iram>;
 440                         };
 441
 442                         sahara2: sahara@10025000 {
 443                                 compatible = "fsl,imx27-sahara";
 444                                 reg = <0x10025000 0x1000>;
 445                                 interrupts = <59>;
 446                                 clocks = <&clks 32>, <&clks 64>;
 447                                 clock-names = "ipg", "ahb";
 448                         };
 449
 450                         clks: ccm@10027000{
 451                                 compatible = "fsl,imx27-ccm";
 452                                 reg = <0x10027000 0x1000>;
 453                                 #clock-cells = <1>;
 454                         };
 455
 456                         iim: iim@10028000 {
 457                                 compatible = "fsl,imx27-iim";
 458                                 reg = <0x10028000 0x1000>;
 459                                 interrupts = <62>;
 460                                 clocks = <&clks 38>;
 461                         };
 462
 463                         fec: ethernet@1002b000 {
 464                                 compatible = "fsl,imx27-fec";
 465                                 reg = <0x1002b000 0x4000>;
 466                                 interrupts = <50>;
 467                                 clocks = <&clks 48>, <&clks 67>;
 468                                 clock-names = "ipg", "ahb";
 469                                 status = "disabled";
 470                         };
 471                 };
 472
 473                 nfc: nand@d8000000 {
 474                         #address-cells = <1>;
 475                         #size-cells = <1>;
 476                         compatible = "fsl,imx27-nand";
 477                         reg = <0xd8000000 0x1000>;
 478                         interrupts = <29>;
 479                         clocks = <&clks 54>;
 480                         status = "disabled";
 481                 };
 482
 483                 weim: weim@d8002000 {
 484                         #address-cells = <2>;
 485                         #size-cells = <1>;
 486                         compatible = "fsl,imx27-weim";
 487                         reg = <0xd8002000 0x1000>;
 488                         clocks = <&clks 0>;
 489                         ranges = <
 490                                 0 0 0xc0000000 0x08000000
 491                                 1 0 0xc8000000 0x08000000
 492                                 2 0 0xd0000000 0x02000000
 493                                 3 0 0xd2000000 0x02000000
 494                                 4 0 0xd4000000 0x02000000
 495                                 5 0 0xd6000000 0x02000000
 496                         >;
 497                         status = "disabled";
 498                 };
 499
 500                 iram: iram@ffff4c00 {
 501                         compatible = "mmio-sram";
 502                         reg = <0xffff4c00 0xb400>;
 503                 };
 504         };
 505 };