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Merge branch 'drm-intel-next-queued' into gvt-next
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx27.dtsi
1 /*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 #include "imx27-pinfunc.h"
13
14 #include <dt-bindings/clock/imx27-clock.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18
19 / {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 /*
23 * The decompressor and also some bootloaders rely on a
24 * pre-existing /chosen node to be available to insert the
25 * command line and merge other ATAGS info.
26 * Also for U-Boot there must be a pre-existing /memory node.
27 */
28 chosen {};
29 memory { device_type = "memory"; };
30
31 aliases {
32 ethernet0 = &fec;
33 gpio0 = &gpio1;
34 gpio1 = &gpio2;
35 gpio2 = &gpio3;
36 gpio3 = &gpio4;
37 gpio4 = &gpio5;
38 gpio5 = &gpio6;
39 i2c0 = &i2c1;
40 i2c1 = &i2c2;
41 serial0 = &uart1;
42 serial1 = &uart2;
43 serial2 = &uart3;
44 serial3 = &uart4;
45 serial4 = &uart5;
46 serial5 = &uart6;
47 spi0 = &cspi1;
48 spi1 = &cspi2;
49 spi2 = &cspi3;
50 };
51
52 aitc: aitc-interrupt-controller@e0000000 {
53 compatible = "fsl,imx27-aitc", "fsl,avic";
54 interrupt-controller;
55 #interrupt-cells = <1>;
56 reg = <0x10040000 0x1000>;
57 };
58
59 clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 osc26m {
64 compatible = "fsl,imx-osc26m", "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <26000000>;
67 };
68 };
69
70 cpus {
71 #size-cells = <0>;
72 #address-cells = <1>;
73
74 cpu: cpu@0 {
75 device_type = "cpu";
76 reg = <0>;
77 compatible = "arm,arm926ej-s";
78 operating-points = <
79 /* kHz uV */
80 266000 1300000
81 399000 1450000
82 >;
83 clock-latency = <62500>;
84 clocks = <&clks IMX27_CLK_CPU_DIV>;
85 voltage-tolerance = <5>;
86 };
87 };
88
89 soc {
90 #address-cells = <1>;
91 #size-cells = <1>;
92 compatible = "simple-bus";
93 interrupt-parent = <&aitc>;
94 ranges;
95
96 aipi@10000000 { /* AIPI1 */
97 compatible = "fsl,aipi-bus", "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 reg = <0x10000000 0x20000>;
101 ranges;
102
103 dma: dma@10001000 {
104 compatible = "fsl,imx27-dma";
105 reg = <0x10001000 0x1000>;
106 interrupts = <32>;
107 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
108 <&clks IMX27_CLK_DMA_AHB_GATE>;
109 clock-names = "ipg", "ahb";
110 #dma-cells = <1>;
111 #dma-channels = <16>;
112 };
113
114 wdog: wdog@10002000 {
115 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
116 reg = <0x10002000 0x1000>;
117 interrupts = <27>;
118 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
119 };
120
121 gpt1: timer@10003000 {
122 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
123 reg = <0x10003000 0x1000>;
124 interrupts = <26>;
125 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
126 <&clks IMX27_CLK_PER1_GATE>;
127 clock-names = "ipg", "per";
128 };
129
130 gpt2: timer@10004000 {
131 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
132 reg = <0x10004000 0x1000>;
133 interrupts = <25>;
134 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
135 <&clks IMX27_CLK_PER1_GATE>;
136 clock-names = "ipg", "per";
137 };
138
139 gpt3: timer@10005000 {
140 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
141 reg = <0x10005000 0x1000>;
142 interrupts = <24>;
143 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
144 <&clks IMX27_CLK_PER1_GATE>;
145 clock-names = "ipg", "per";
146 };
147
148 pwm: pwm@10006000 {
149 #pwm-cells = <2>;
150 compatible = "fsl,imx27-pwm";
151 reg = <0x10006000 0x1000>;
152 interrupts = <23>;
153 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
154 <&clks IMX27_CLK_PER1_GATE>;
155 clock-names = "ipg", "per";
156 };
157
158 rtc: rtc@10007000 {
159 compatible = "fsl,imx21-rtc";
160 reg = <0x10007000 0x1000>;
161 interrupts = <22>;
162 clocks = <&clks IMX27_CLK_CKIL>,
163 <&clks IMX27_CLK_RTC_IPG_GATE>;
164 clock-names = "ref", "ipg";
165 };
166
167 kpp: kpp@10008000 {
168 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
169 reg = <0x10008000 0x1000>;
170 interrupts = <21>;
171 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
172 status = "disabled";
173 };
174
175 owire: owire@10009000 {
176 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
177 reg = <0x10009000 0x1000>;
178 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
179 status = "disabled";
180 };
181
182 uart1: serial@1000a000 {
183 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
184 reg = <0x1000a000 0x1000>;
185 interrupts = <20>;
186 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
187 <&clks IMX27_CLK_PER1_GATE>;
188 clock-names = "ipg", "per";
189 status = "disabled";
190 };
191
192 uart2: serial@1000b000 {
193 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
194 reg = <0x1000b000 0x1000>;
195 interrupts = <19>;
196 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
197 <&clks IMX27_CLK_PER1_GATE>;
198 clock-names = "ipg", "per";
199 status = "disabled";
200 };
201
202 uart3: serial@1000c000 {
203 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
204 reg = <0x1000c000 0x1000>;
205 interrupts = <18>;
206 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
207 <&clks IMX27_CLK_PER1_GATE>;
208 clock-names = "ipg", "per";
209 status = "disabled";
210 };
211
212 uart4: serial@1000d000 {
213 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
214 reg = <0x1000d000 0x1000>;
215 interrupts = <17>;
216 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
217 <&clks IMX27_CLK_PER1_GATE>;
218 clock-names = "ipg", "per";
219 status = "disabled";
220 };
221
222 cspi1: cspi@1000e000 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "fsl,imx27-cspi";
226 reg = <0x1000e000 0x1000>;
227 interrupts = <16>;
228 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
229 <&clks IMX27_CLK_PER2_GATE>;
230 clock-names = "ipg", "per";
231 status = "disabled";
232 };
233
234 cspi2: cspi@1000f000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "fsl,imx27-cspi";
238 reg = <0x1000f000 0x1000>;
239 interrupts = <15>;
240 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
241 <&clks IMX27_CLK_PER2_GATE>;
242 clock-names = "ipg", "per";
243 status = "disabled";
244 };
245
246 ssi1: ssi@10010000 {
247 #sound-dai-cells = <0>;
248 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
249 reg = <0x10010000 0x1000>;
250 interrupts = <14>;
251 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
252 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
253 dma-names = "rx0", "tx0", "rx1", "tx1";
254 fsl,fifo-depth = <8>;
255 status = "disabled";
256 };
257
258 ssi2: ssi@10011000 {
259 #sound-dai-cells = <0>;
260 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
261 reg = <0x10011000 0x1000>;
262 interrupts = <13>;
263 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
264 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
265 dma-names = "rx0", "tx0", "rx1", "tx1";
266 fsl,fifo-depth = <8>;
267 status = "disabled";
268 };
269
270 i2c1: i2c@10012000 {
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
274 reg = <0x10012000 0x1000>;
275 interrupts = <12>;
276 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
277 status = "disabled";
278 };
279
280 sdhci1: sdhci@10013000 {
281 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
282 reg = <0x10013000 0x1000>;
283 interrupts = <11>;
284 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
285 <&clks IMX27_CLK_PER2_GATE>;
286 clock-names = "ipg", "per";
287 dmas = <&dma 7>;
288 dma-names = "rx-tx";
289 status = "disabled";
290 };
291
292 sdhci2: sdhci@10014000 {
293 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
294 reg = <0x10014000 0x1000>;
295 interrupts = <10>;
296 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
297 <&clks IMX27_CLK_PER2_GATE>;
298 clock-names = "ipg", "per";
299 dmas = <&dma 6>;
300 dma-names = "rx-tx";
301 status = "disabled";
302 };
303
304 iomuxc: iomuxc@10015000 {
305 compatible = "fsl,imx27-iomuxc";
306 reg = <0x10015000 0x600>;
307 #address-cells = <1>;
308 #size-cells = <1>;
309 ranges;
310
311 gpio1: gpio@10015000 {
312 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
313 reg = <0x10015000 0x100>;
314 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
315 interrupts = <8>;
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 };
321
322 gpio2: gpio@10015100 {
323 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
324 reg = <0x10015100 0x100>;
325 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
326 interrupts = <8>;
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 };
332
333 gpio3: gpio@10015200 {
334 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
335 reg = <0x10015200 0x100>;
336 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
337 interrupts = <8>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 };
343
344 gpio4: gpio@10015300 {
345 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
346 reg = <0x10015300 0x100>;
347 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
348 interrupts = <8>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
354
355 gpio5: gpio@10015400 {
356 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
357 reg = <0x10015400 0x100>;
358 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
359 interrupts = <8>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 };
365
366 gpio6: gpio@10015500 {
367 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
368 reg = <0x10015500 0x100>;
369 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
370 interrupts = <8>;
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 };
376 };
377
378 audmux: audmux@10016000 {
379 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
380 reg = <0x10016000 0x1000>;
381 clocks = <&clks IMX27_CLK_DUMMY>;
382 clock-names = "audmux";
383 status = "disabled";
384 };
385
386 cspi3: cspi@10017000 {
387 #address-cells = <1>;
388 #size-cells = <0>;
389 compatible = "fsl,imx27-cspi";
390 reg = <0x10017000 0x1000>;
391 interrupts = <6>;
392 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
393 <&clks IMX27_CLK_PER2_GATE>;
394 clock-names = "ipg", "per";
395 status = "disabled";
396 };
397
398 gpt4: timer@10019000 {
399 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
400 reg = <0x10019000 0x1000>;
401 interrupts = <4>;
402 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
403 <&clks IMX27_CLK_PER1_GATE>;
404 clock-names = "ipg", "per";
405 };
406
407 gpt5: timer@1001a000 {
408 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
409 reg = <0x1001a000 0x1000>;
410 interrupts = <3>;
411 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
412 <&clks IMX27_CLK_PER1_GATE>;
413 clock-names = "ipg", "per";
414 };
415
416 uart5: serial@1001b000 {
417 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
418 reg = <0x1001b000 0x1000>;
419 interrupts = <49>;
420 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
421 <&clks IMX27_CLK_PER1_GATE>;
422 clock-names = "ipg", "per";
423 status = "disabled";
424 };
425
426 uart6: serial@1001c000 {
427 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
428 reg = <0x1001c000 0x1000>;
429 interrupts = <48>;
430 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
431 <&clks IMX27_CLK_PER1_GATE>;
432 clock-names = "ipg", "per";
433 status = "disabled";
434 };
435
436 i2c2: i2c@1001d000 {
437 #address-cells = <1>;
438 #size-cells = <0>;
439 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
440 reg = <0x1001d000 0x1000>;
441 interrupts = <1>;
442 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
443 status = "disabled";
444 };
445
446 sdhci3: sdhci@1001e000 {
447 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
448 reg = <0x1001e000 0x1000>;
449 interrupts = <9>;
450 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
451 <&clks IMX27_CLK_PER2_GATE>;
452 clock-names = "ipg", "per";
453 dmas = <&dma 36>;
454 dma-names = "rx-tx";
455 status = "disabled";
456 };
457
458 gpt6: timer@1001f000 {
459 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
460 reg = <0x1001f000 0x1000>;
461 interrupts = <2>;
462 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
463 <&clks IMX27_CLK_PER1_GATE>;
464 clock-names = "ipg", "per";
465 };
466 };
467
468 aipi@10020000 { /* AIPI2 */
469 compatible = "fsl,aipi-bus", "simple-bus";
470 #address-cells = <1>;
471 #size-cells = <1>;
472 reg = <0x10020000 0x20000>;
473 ranges;
474
475 fb: fb@10021000 {
476 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
477 interrupts = <61>;
478 reg = <0x10021000 0x1000>;
479 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
480 <&clks IMX27_CLK_LCDC_AHB_GATE>,
481 <&clks IMX27_CLK_PER3_GATE>;
482 clock-names = "ipg", "ahb", "per";
483 status = "disabled";
484 };
485
486 coda: coda@10023000 {
487 compatible = "fsl,imx27-vpu", "cnm,codadx6";
488 reg = <0x10023000 0x0200>;
489 interrupts = <53>;
490 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
491 <&clks IMX27_CLK_VPU_AHB_GATE>;
492 clock-names = "per", "ahb";
493 iram = <&iram>;
494 };
495
496 usbotg: usb@10024000 {
497 compatible = "fsl,imx27-usb";
498 reg = <0x10024000 0x200>;
499 interrupts = <56>;
500 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
501 <&clks IMX27_CLK_USB_AHB_GATE>,
502 <&clks IMX27_CLK_USB_DIV>;
503 clock-names = "ipg", "ahb", "per";
504 fsl,usbmisc = <&usbmisc 0>;
505 status = "disabled";
506 };
507
508 usbh1: usb@10024200 {
509 compatible = "fsl,imx27-usb";
510 reg = <0x10024200 0x200>;
511 interrupts = <54>;
512 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
513 <&clks IMX27_CLK_USB_AHB_GATE>,
514 <&clks IMX27_CLK_USB_DIV>;
515 clock-names = "ipg", "ahb", "per";
516 fsl,usbmisc = <&usbmisc 1>;
517 dr_mode = "host";
518 status = "disabled";
519 };
520
521 usbh2: usb@10024400 {
522 compatible = "fsl,imx27-usb";
523 reg = <0x10024400 0x200>;
524 interrupts = <55>;
525 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
526 <&clks IMX27_CLK_USB_AHB_GATE>,
527 <&clks IMX27_CLK_USB_DIV>;
528 clock-names = "ipg", "ahb", "per";
529 fsl,usbmisc = <&usbmisc 2>;
530 dr_mode = "host";
531 status = "disabled";
532 };
533
534 usbmisc: usbmisc@10024600 {
535 #index-cells = <1>;
536 compatible = "fsl,imx27-usbmisc";
537 reg = <0x10024600 0x200>;
538 };
539
540 sahara2: sahara@10025000 {
541 compatible = "fsl,imx27-sahara";
542 reg = <0x10025000 0x1000>;
543 interrupts = <59>;
544 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
545 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
546 clock-names = "ipg", "ahb";
547 };
548
549 clks: ccm@10027000{
550 compatible = "fsl,imx27-ccm";
551 reg = <0x10027000 0x1000>;
552 #clock-cells = <1>;
553 };
554
555 iim: iim@10028000 {
556 compatible = "fsl,imx27-iim";
557 reg = <0x10028000 0x1000>;
558 interrupts = <62>;
559 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
560 };
561
562 fec: ethernet@1002b000 {
563 compatible = "fsl,imx27-fec";
564 reg = <0x1002b000 0x1000>;
565 interrupts = <50>;
566 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
567 <&clks IMX27_CLK_FEC_AHB_GATE>;
568 clock-names = "ipg", "ahb";
569 status = "disabled";
570 };
571 };
572
573 nfc: nand@d8000000 {
574 #address-cells = <1>;
575 #size-cells = <1>;
576 compatible = "fsl,imx27-nand";
577 reg = <0xd8000000 0x1000>;
578 interrupts = <29>;
579 clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
580 status = "disabled";
581 };
582
583 weim: weim@d8002000 {
584 #address-cells = <2>;
585 #size-cells = <1>;
586 compatible = "fsl,imx27-weim";
587 reg = <0xd8002000 0x1000>;
588 clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
589 ranges = <
590 0 0 0xc0000000 0x08000000
591 1 0 0xc8000000 0x08000000
592 2 0 0xd0000000 0x02000000
593 3 0 0xd2000000 0x02000000
594 4 0 0xd4000000 0x02000000
595 5 0 0xd6000000 0x02000000
596 >;
597 status = "disabled";
598 };
599
600 iram: iram@ffff4c00 {
601 compatible = "mmio-sram";
602 reg = <0xffff4c00 0xb400>;
603 };
604 };
605 };
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