arch/arm/boot/dts/imx50-evk.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2013 Greg Ungerer <gerg@uclinux.org>
   4 // Copyright 2011 Freescale Semiconductor, Inc.
   5 // Copyright 2011 Linaro Ltd.
   6
   7 /dts-v1/;
   8 #include "imx50.dtsi"
   9
  10 / {
  11         model = "Freescale i.MX50 Evaluation Kit";
  12         compatible = "fsl,imx50-evk", "fsl,imx50";
  13
  14         memory@70000000 {
  15                 reg = <0x70000000 0x80000000>;
  16         };
  17 };
  18
  19 &cspi {
  20         pinctrl-names = "default";
  21         pinctrl-0 = <&pinctrl_cspi>;
  22         cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
  23         status = "okay";
  24
  25         flash: m25p32@1 {
  26                 #address-cells = <1>;
  27                 #size-cells = <1>;
  28                 compatible = "m25p32", "jedec,spi-nor";
  29                 spi-max-frequency = <25000000>;
  30                 reg = <1>;
  31
  32                 partition@0 {
  33                         label = "bootloader";
  34                         reg = <0x0 0x100000>;
  35                         read-only;
  36                 };
  37
  38                 partition@100000 {
  39                         label = "kernel";
  40                         reg = <0x100000 0x300000>;
  41                 };
  42         };
  43 };
  44
  45 &fec {
  46         pinctrl-names = "default";
  47         pinctrl-0 = <&pinctrl_fec>;
  48         phy-mode = "rmii";
  49         phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
  50         status = "okay";
  51 };
  52
  53 &iomuxc {
  54         imx50-evk {
  55                 pinctrl_cspi: cspigrp {
  56                         fsl,pins = <
  57                                 MX50_PAD_CSPI_SCLK__CSPI_SCLK           0x00
  58                                 MX50_PAD_CSPI_MISO__CSPI_MISO           0x00
  59                                 MX50_PAD_CSPI_MOSI__CSPI_MOSI           0x00
  60                                 MX50_PAD_CSPI_SS0__GPIO4_11             0xc4
  61                                 MX50_PAD_ECSPI1_MOSI__CSPI_SS1          0xf4
  62                         >;
  63                 };
  64
  65                 pinctrl_fec: fecgrp {
  66                         fsl,pins = <
  67                                 MX50_PAD_SSI_RXFS__FEC_MDC              0x80
  68                                 MX50_PAD_SSI_RXC__FEC_MDIO              0x80
  69                                 MX50_PAD_DISP_D0__FEC_TX_CLK            0x80
  70                                 MX50_PAD_DISP_D1__FEC_RX_ERR            0x80
  71                                 MX50_PAD_DISP_D2__FEC_RX_DV             0x80
  72                                 MX50_PAD_DISP_D3__FEC_RDATA_1           0x80
  73                                 MX50_PAD_DISP_D4__FEC_RDATA_0           0x80
  74                                 MX50_PAD_DISP_D5__FEC_TX_EN             0x80
  75                                 MX50_PAD_DISP_D6__FEC_TDATA_1           0x80
  76                                 MX50_PAD_DISP_D7__FEC_TDATA_0           0x80
  77                         >;
  78                 };
  79
  80                 pinctrl_uart1: uart1grp {
  81                         fsl,pins = <
  82                                 MX50_PAD_UART1_TXD__UART1_TXD_MUX       0x1e4
  83                                 MX50_PAD_UART1_RXD__UART1_RXD_MUX       0x1e4
  84                                 MX50_PAD_UART1_RTS__UART1_RTS           0x1e4
  85                                 MX50_PAD_UART1_CTS__UART1_CTS           0x1e4
  86                         >;
  87                 };
  88         };
  89 };
  90
  91 &uart1 {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_uart1>;
  94         status = "okay";
  95 };
  96
  97 &usbh1 {
  98         status = "okay";
  99 };
 100
 101 &usbotg {
 102         status = "okay";
 103 };