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Merge tag 'topic/designware-baytrail-2017-03-02' of git://anongit.freedesktop.org...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx50.dtsi
1 /*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14 #include "imx50-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 /*
21 * The decompressor and also some bootloaders rely on a
22 * pre-existing /chosen node to be available to insert the
23 * command line and merge other ATAGS info.
24 * Also for U-Boot there must be a pre-existing /memory node.
25 */
26 chosen {};
27 memory { device_type = "memory"; reg = <0 0>; };
28
29 aliases {
30 ethernet0 = &fec;
31 gpio0 = &gpio1;
32 gpio1 = &gpio2;
33 gpio2 = &gpio3;
34 gpio3 = &gpio4;
35 gpio4 = &gpio5;
36 gpio5 = &gpio6;
37 serial0 = &uart1;
38 serial1 = &uart2;
39 serial2 = &uart3;
40 serial3 = &uart4;
41 serial4 = &uart5;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a8";
50 reg = <0x0>;
51 };
52 };
53
54 tzic: tz-interrupt-controller@0fffc000 {
55 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
56 interrupt-controller;
57 #interrupt-cells = <1>;
58 reg = <0x0fffc000 0x4000>;
59 };
60
61 clocks {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 ckil {
66 compatible = "fsl,imx-ckil", "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <32768>;
69 };
70
71 ckih1 {
72 compatible = "fsl,imx-ckih1", "fixed-clock";
73 #clock-cells = <0>;
74 clock-frequency = <22579200>;
75 };
76
77 ckih2 {
78 compatible = "fsl,imx-ckih2", "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <0>;
81 };
82
83 osc {
84 compatible = "fsl,imx-osc", "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <24000000>;
87 };
88 };
89
90 soc {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
94 interrupt-parent = <&tzic>;
95 ranges;
96
97 aips@50000000 { /* AIPS1 */
98 compatible = "fsl,aips-bus", "simple-bus";
99 #address-cells = <1>;
100 #size-cells = <1>;
101 reg = <0x50000000 0x10000000>;
102 ranges;
103
104 spba@50000000 {
105 compatible = "fsl,spba-bus", "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0x50000000 0x40000>;
109 ranges;
110
111 esdhc1: esdhc@50004000 {
112 compatible = "fsl,imx50-esdhc";
113 reg = <0x50004000 0x4000>;
114 interrupts = <1>;
115 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
116 <&clks IMX5_CLK_DUMMY>,
117 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
118 clock-names = "ipg", "ahb", "per";
119 bus-width = <4>;
120 status = "disabled";
121 };
122
123 esdhc2: esdhc@50008000 {
124 compatible = "fsl,imx50-esdhc";
125 reg = <0x50008000 0x4000>;
126 interrupts = <2>;
127 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
128 <&clks IMX5_CLK_DUMMY>,
129 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
130 clock-names = "ipg", "ahb", "per";
131 bus-width = <4>;
132 status = "disabled";
133 };
134
135 uart3: serial@5000c000 {
136 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
137 reg = <0x5000c000 0x4000>;
138 interrupts = <33>;
139 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
140 <&clks IMX5_CLK_UART3_PER_GATE>;
141 clock-names = "ipg", "per";
142 status = "disabled";
143 };
144
145 ecspi1: ecspi@50010000 {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
149 reg = <0x50010000 0x4000>;
150 interrupts = <36>;
151 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
152 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
153 clock-names = "ipg", "per";
154 status = "disabled";
155 };
156
157 ssi2: ssi@50014000 {
158 #sound-dai-cells = <0>;
159 compatible = "fsl,imx50-ssi",
160 "fsl,imx51-ssi",
161 "fsl,imx21-ssi";
162 reg = <0x50014000 0x4000>;
163 interrupts = <30>;
164 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
165 dmas = <&sdma 24 1 0>,
166 <&sdma 25 1 0>;
167 dma-names = "rx", "tx";
168 fsl,fifo-depth = <15>;
169 status = "disabled";
170 };
171
172 esdhc3: esdhc@50020000 {
173 compatible = "fsl,imx50-esdhc";
174 reg = <0x50020000 0x4000>;
175 interrupts = <3>;
176 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
177 <&clks IMX5_CLK_DUMMY>,
178 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
179 clock-names = "ipg", "ahb", "per";
180 bus-width = <4>;
181 status = "disabled";
182 };
183
184 esdhc4: esdhc@50024000 {
185 compatible = "fsl,imx50-esdhc";
186 reg = <0x50024000 0x4000>;
187 interrupts = <4>;
188 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
189 <&clks IMX5_CLK_DUMMY>,
190 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
191 clock-names = "ipg", "ahb", "per";
192 bus-width = <4>;
193 status = "disabled";
194 };
195 };
196
197 usbotg: usb@53f80000 {
198 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
199 reg = <0x53f80000 0x0200>;
200 interrupts = <18>;
201 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
202 status = "disabled";
203 };
204
205 usbh1: usb@53f80200 {
206 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
207 reg = <0x53f80200 0x0200>;
208 interrupts = <14>;
209 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
210 dr_mode = "host";
211 status = "disabled";
212 };
213
214 usbh2: usb@53f80400 {
215 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
216 reg = <0x53f80400 0x0200>;
217 interrupts = <16>;
218 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
219 dr_mode = "host";
220 status = "disabled";
221 };
222
223 usbh3: usb@53f80600 {
224 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
225 reg = <0x53f80600 0x0200>;
226 interrupts = <17>;
227 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
228 dr_mode = "host";
229 status = "disabled";
230 };
231
232 gpio1: gpio@53f84000 {
233 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
234 reg = <0x53f84000 0x4000>;
235 interrupts = <50 51>;
236 gpio-controller;
237 #gpio-cells = <2>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 gpio-ranges = <&iomuxc 0 151 28>;
241 };
242
243 gpio2: gpio@53f88000 {
244 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
245 reg = <0x53f88000 0x4000>;
246 interrupts = <52 53>;
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
252 <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
253 <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
254 <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
255 };
256
257 gpio3: gpio@53f8c000 {
258 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
259 reg = <0x53f8c000 0x4000>;
260 interrupts = <54 55>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 gpio-ranges = <&iomuxc 0 108 32>;
266 };
267
268 gpio4: gpio@53f90000 {
269 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
270 reg = <0x53f90000 0x4000>;
271 interrupts = <56 57>;
272 gpio-controller;
273 #gpio-cells = <2>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
277 <&iomuxc 20 140 11>;
278 };
279
280 wdog1: wdog@53f98000 {
281 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
282 reg = <0x53f98000 0x4000>;
283 interrupts = <58>;
284 clocks = <&clks IMX5_CLK_DUMMY>;
285 };
286
287 gpt: timer@53fa0000 {
288 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
289 reg = <0x53fa0000 0x4000>;
290 interrupts = <39>;
291 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
292 <&clks IMX5_CLK_GPT_HF_GATE>;
293 clock-names = "ipg", "per";
294 };
295
296 iomuxc: iomuxc@53fa8000 {
297 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
298 reg = <0x53fa8000 0x4000>;
299 };
300
301 gpr: iomuxc-gpr@53fa8000 {
302 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
303 reg = <0x53fa8000 0xc>;
304 };
305
306 pwm1: pwm@53fb4000 {
307 #pwm-cells = <2>;
308 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
309 reg = <0x53fb4000 0x4000>;
310 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
311 <&clks IMX5_CLK_PWM1_HF_GATE>;
312 clock-names = "ipg", "per";
313 interrupts = <61>;
314 };
315
316 pwm2: pwm@53fb8000 {
317 #pwm-cells = <2>;
318 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
319 reg = <0x53fb8000 0x4000>;
320 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
321 <&clks IMX5_CLK_PWM2_HF_GATE>;
322 clock-names = "ipg", "per";
323 interrupts = <94>;
324 };
325
326 uart1: serial@53fbc000 {
327 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
328 reg = <0x53fbc000 0x4000>;
329 interrupts = <31>;
330 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
331 <&clks IMX5_CLK_UART1_PER_GATE>;
332 clock-names = "ipg", "per";
333 status = "disabled";
334 };
335
336 uart2: serial@53fc0000 {
337 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
338 reg = <0x53fc0000 0x4000>;
339 interrupts = <32>;
340 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
341 <&clks IMX5_CLK_UART2_PER_GATE>;
342 clock-names = "ipg", "per";
343 status = "disabled";
344 };
345
346 src: src@53fd0000 {
347 compatible = "fsl,imx50-src", "fsl,imx51-src";
348 reg = <0x53fd0000 0x4000>;
349 #reset-cells = <1>;
350 };
351
352 clks: ccm@53fd4000{
353 compatible = "fsl,imx50-ccm";
354 reg = <0x53fd4000 0x4000>;
355 interrupts = <0 71 0x04 0 72 0x04>;
356 #clock-cells = <1>;
357 };
358
359 gpio5: gpio@53fdc000 {
360 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
361 reg = <0x53fdc000 0x4000>;
362 interrupts = <103 104>;
363 gpio-controller;
364 #gpio-cells = <2>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
367 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
368 };
369
370 gpio6: gpio@53fe0000 {
371 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
372 reg = <0x53fe0000 0x4000>;
373 interrupts = <105 106>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
379 };
380
381 i2c3: i2c@53fec000 {
382 #address-cells = <1>;
383 #size-cells = <0>;
384 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
385 reg = <0x53fec000 0x4000>;
386 interrupts = <64>;
387 clocks = <&clks IMX5_CLK_I2C3_GATE>;
388 status = "disabled";
389 };
390
391 uart4: serial@53ff0000 {
392 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
393 reg = <0x53ff0000 0x4000>;
394 interrupts = <13>;
395 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
396 <&clks IMX5_CLK_UART4_PER_GATE>;
397 clock-names = "ipg", "per";
398 status = "disabled";
399 };
400 };
401
402 aips@60000000 { /* AIPS2 */
403 compatible = "fsl,aips-bus", "simple-bus";
404 #address-cells = <1>;
405 #size-cells = <1>;
406 reg = <0x60000000 0x10000000>;
407 ranges;
408
409 uart5: serial@63f90000 {
410 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
411 reg = <0x63f90000 0x4000>;
412 interrupts = <86>;
413 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
414 <&clks IMX5_CLK_UART5_PER_GATE>;
415 clock-names = "ipg", "per";
416 status = "disabled";
417 };
418
419 owire: owire@63fa4000 {
420 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
421 reg = <0x63fa4000 0x4000>;
422 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
423 status = "disabled";
424 };
425
426 ecspi2: ecspi@63fac000 {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
430 reg = <0x63fac000 0x4000>;
431 interrupts = <37>;
432 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
433 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
434 clock-names = "ipg", "per";
435 status = "disabled";
436 };
437
438 sdma: sdma@63fb0000 {
439 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
440 reg = <0x63fb0000 0x4000>;
441 interrupts = <6>;
442 clocks = <&clks IMX5_CLK_SDMA_GATE>,
443 <&clks IMX5_CLK_SDMA_GATE>;
444 clock-names = "ipg", "ahb";
445 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
446 };
447
448 cspi: cspi@63fc0000 {
449 #address-cells = <1>;
450 #size-cells = <0>;
451 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
452 reg = <0x63fc0000 0x4000>;
453 interrupts = <38>;
454 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
455 <&clks IMX5_CLK_CSPI_IPG_GATE>;
456 clock-names = "ipg", "per";
457 status = "disabled";
458 };
459
460 i2c2: i2c@63fc4000 {
461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
464 reg = <0x63fc4000 0x4000>;
465 interrupts = <63>;
466 clocks = <&clks IMX5_CLK_I2C2_GATE>;
467 status = "disabled";
468 };
469
470 i2c1: i2c@63fc8000 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
474 reg = <0x63fc8000 0x4000>;
475 interrupts = <62>;
476 clocks = <&clks IMX5_CLK_I2C1_GATE>;
477 status = "disabled";
478 };
479
480 ssi1: ssi@63fcc000 {
481 #sound-dai-cells = <0>;
482 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
483 "fsl,imx21-ssi";
484 reg = <0x63fcc000 0x4000>;
485 interrupts = <29>;
486 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
487 dmas = <&sdma 28 0 0>,
488 <&sdma 29 0 0>;
489 dma-names = "rx", "tx";
490 fsl,fifo-depth = <15>;
491 status = "disabled";
492 };
493
494 audmux: audmux@63fd0000 {
495 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
496 reg = <0x63fd0000 0x4000>;
497 status = "disabled";
498 };
499
500 fec: ethernet@63fec000 {
501 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
502 reg = <0x63fec000 0x4000>;
503 interrupts = <87>;
504 clocks = <&clks IMX5_CLK_FEC_GATE>,
505 <&clks IMX5_CLK_FEC_GATE>,
506 <&clks IMX5_CLK_FEC_GATE>;
507 clock-names = "ipg", "ahb", "ptp";
508 status = "disabled";
509 };
510 };
511 };
512 };
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