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Merge tag 'mips_fixes_5.1_1' into mips-next
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx51-zii-rdu1.dts
1 /*
2 * Copyright (C) 2017 Zodiac Inflight Innovations
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42 /dts-v1/;
43 #include "imx51.dtsi"
44 #include <dt-bindings/sound/fsl-imx-audmux.h>
45
46 / {
47 model = "ZII RDU1 Board";
48 compatible = "zii,imx51-rdu1", "fsl,imx51";
49
50 chosen {
51 stdout-path = &uart1;
52 };
53
54 /* Will be filled by the bootloader */
55 memory@90000000 {
56 device_type = "memory";
57 reg = <0x90000000 0>;
58 };
59
60 aliases {
61 mdio-gpio0 = &mdio_gpio;
62 rtc0 = &ds1341;
63 };
64
65 clk_26M_osc: 26M_osc {
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <26000000>;
69 };
70
71 clk_26M_osc_gate: 26M_gate {
72 compatible = "gpio-gate-clock";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_clk26mhz>;
75 clocks = <&clk_26M_osc>;
76 #clock-cells = <0>;
77 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
78 };
79
80 clk_26M_usb: usbhost_gate {
81 compatible = "gpio-gate-clock";
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_usbgate26mhz>;
84 clocks = <&clk_26M_osc_gate>;
85 #clock-cells = <0>;
86 enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
87 };
88
89 clk_26M_snd: snd_gate {
90 compatible = "gpio-gate-clock";
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_sndgate26mhz>;
93 clocks = <&clk_26M_osc_gate>;
94 #clock-cells = <0>;
95 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
96 };
97
98 reg_5p0v_main: regulator-5p0v-main {
99 compatible = "regulator-fixed";
100 regulator-name = "5V_MAIN";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 regulator-always-on;
104 };
105
106 reg_3p3v: regulator-3p3v {
107 compatible = "regulator-fixed";
108 regulator-name = "3.3V";
109 regulator-min-microvolt = <3300000>;
110 regulator-max-microvolt = <3300000>;
111 regulator-always-on;
112 };
113
114 disp0 {
115 compatible = "fsl,imx-parallel-display";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_ipu_disp1>;
118
119 #address-cells = <1>;
120 #size-cells = <0>;
121
122 port@0 {
123 reg = <0>;
124
125 display_in: endpoint {
126 remote-endpoint = <&ipu_di0_disp1>;
127 };
128 };
129
130 port@1 {
131 reg = <1>;
132
133 display_out: endpoint {
134 remote-endpoint = <&panel_in>;
135 };
136 };
137 };
138
139 panel {
140 /* no compatible here, bootloader will patch in correct one */
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_panel>;
143 power-supply = <&reg_3p3v>;
144 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
145 status = "disabled";
146
147 port {
148 panel_in: endpoint {
149 remote-endpoint = <&display_out>;
150 };
151 };
152 };
153
154 i2c_gpio: i2c-gpio {
155 compatible = "i2c-gpio";
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_swi2c>;
158 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
159 <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
160 i2c-gpio,delay-us = <50>;
161 status = "okay";
162
163 #address-cells = <1>;
164 #size-cells = <0>;
165
166 sgtl5000: codec@a {
167 compatible = "fsl,sgtl5000";
168 reg = <0x0a>;
169 clocks = <&clk_26M_snd>;
170 VDDA-supply = <&vdig_reg>;
171 VDDIO-supply = <&vvideo_reg>;
172 #sound-dai-cells = <0>;
173 };
174 };
175
176 spi_gpio: spi-gpio {
177 compatible = "spi-gpio";
178 #address-cells = <1>;
179 #size-cells = <0>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_gpiospi0>;
182 status = "okay";
183
184 gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>;
185 gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>;
186 gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>;
187 num-chipselects = <1>;
188 cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
189
190 eeprom@0 {
191 compatible = "eeprom-93xx46";
192 reg = <0>;
193 spi-max-frequency = <1000000>;
194 spi-cs-high;
195 data-size = <8>;
196 };
197 };
198
199 mdio_gpio: mdio-gpio {
200 compatible = "virtual,mdio-gpio";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_swmdio>;
203 gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */
204 <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */
205
206 #address-cells = <1>;
207 #size-cells = <0>;
208
209 switch@0 {
210 compatible = "marvell,mv88e6085";
211 reg = <0>;
212 dsa,member = <0 0>;
213
214 ports {
215 #address-cells = <1>;
216 #size-cells = <0>;
217
218 port@0 {
219 reg = <0>;
220 label = "cpu";
221 ethernet = <&fec>;
222
223 fixed-link {
224 speed = <100>;
225 full-duplex;
226 };
227 };
228
229 port@1 {
230 reg = <1>;
231 label = "netaux";
232 };
233
234 port@3 {
235 reg = <3>;
236 label = "netright";
237 };
238
239 port@4 {
240 reg = <4>;
241 label = "netleft";
242 };
243 };
244 };
245 };
246
247 sound {
248 compatible = "simple-audio-card";
249 simple-audio-card,name = "Front";
250 simple-audio-card,format = "i2s";
251 simple-audio-card,bitclock-master = <&sound_codec>;
252 simple-audio-card,frame-master = <&sound_codec>;
253 simple-audio-card,widgets =
254 "Headphone", "Headphone Jack";
255 simple-audio-card,routing =
256 "Headphone Jack", "HPLEFT",
257 "Headphone Jack", "HPRIGHT";
258 simple-audio-card,aux-devs = <&hpa1>;
259
260 sound_cpu: simple-audio-card,cpu {
261 sound-dai = <&ssi2>;
262 };
263
264 sound_codec: simple-audio-card,codec {
265 sound-dai = <&sgtl5000>;
266 clocks = <&clk_26M_snd>;
267 };
268 };
269
270 usbh1phy: usbphy1 {
271 compatible = "usb-nop-xceiv";
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_usbh1phy>;
274 clocks = <&clk_26M_usb>;
275 clock-names = "main_clk";
276 reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
277 vcc-supply = <&vusb_reg>;
278 #phy-cells = <0>;
279 };
280
281 usbh2phy: usbphy2 {
282 compatible = "usb-nop-xceiv";
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_usbh2phy>;
285 clocks = <&clk_26M_usb>;
286 clock-names = "main_clk";
287 reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
288 vcc-supply = <&vusb_reg>;
289 #phy-cells = <0>;
290 };
291 };
292
293 &audmux {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_audmux>;
296 status = "okay";
297
298 ssi2 {
299 fsl,audmux-port = <1>;
300 fsl,port-config = <
301 (IMX_AUDMUX_V2_PTCR_SYN |
302 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
303 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
304 IMX_AUDMUX_V2_PTCR_TFSDIR |
305 IMX_AUDMUX_V2_PTCR_TCLKDIR)
306 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
307 >;
308 };
309
310 aud3 {
311 fsl,audmux-port = <2>;
312 fsl,port-config = <
313 IMX_AUDMUX_V2_PTCR_SYN
314 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
315 >;
316 };
317 };
318
319 &cpu {
320 cpu-supply = <&sw1_reg>;
321 };
322
323 &ecspi1 {
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_ecspi1>;
326 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
327 <&gpio4 25 GPIO_ACTIVE_LOW>;
328 status = "okay";
329
330 pmic@0 {
331 compatible = "fsl,mc13892";
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_pmic>;
334 spi-max-frequency = <6000000>;
335 spi-cs-high;
336 reg = <0>;
337 interrupt-parent = <&gpio1>;
338 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
339 fsl,mc13xxx-uses-adc;
340
341 regulators {
342 sw1_reg: sw1 {
343 regulator-min-microvolt = <600000>;
344 regulator-max-microvolt = <1375000>;
345 regulator-boot-on;
346 regulator-always-on;
347 };
348
349 sw2_reg: sw2 {
350 regulator-min-microvolt = <900000>;
351 regulator-max-microvolt = <1850000>;
352 regulator-boot-on;
353 regulator-always-on;
354 };
355
356 sw3_reg: sw3 {
357 regulator-min-microvolt = <1100000>;
358 regulator-max-microvolt = <1850000>;
359 regulator-boot-on;
360 regulator-always-on;
361 };
362
363 sw4_reg: sw4 {
364 regulator-min-microvolt = <1100000>;
365 regulator-max-microvolt = <1850000>;
366 regulator-boot-on;
367 regulator-always-on;
368 };
369
370 vpll_reg: vpll {
371 regulator-min-microvolt = <1050000>;
372 regulator-max-microvolt = <1800000>;
373 regulator-boot-on;
374 regulator-always-on;
375 };
376
377 vdig_reg: vdig {
378 regulator-min-microvolt = <1650000>;
379 regulator-max-microvolt = <1650000>;
380 regulator-boot-on;
381 };
382
383 vsd_reg: vsd {
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <3150000>;
386 };
387
388 vusb_reg: vusb {
389 regulator-always-on;
390 };
391
392 vusb2_reg: vusb2 {
393 regulator-min-microvolt = <2400000>;
394 regulator-max-microvolt = <2775000>;
395 regulator-boot-on;
396 regulator-always-on;
397 };
398
399 vvideo_reg: vvideo {
400 regulator-min-microvolt = <2775000>;
401 regulator-max-microvolt = <2775000>;
402 };
403
404 vaudio_reg: vaudio {
405 regulator-min-microvolt = <2300000>;
406 regulator-max-microvolt = <3000000>;
407 };
408
409 vcam_reg: vcam {
410 regulator-min-microvolt = <2500000>;
411 regulator-max-microvolt = <3000000>;
412 };
413
414 vgen1_reg: vgen1 {
415 regulator-min-microvolt = <1200000>;
416 regulator-max-microvolt = <1200000>;
417 };
418
419 vgen2_reg: vgen2 {
420 regulator-min-microvolt = <1200000>;
421 regulator-max-microvolt = <3150000>;
422 regulator-always-on;
423 };
424
425 vgen3_reg: vgen3 {
426 regulator-min-microvolt = <1800000>;
427 regulator-max-microvolt = <2900000>;
428 regulator-always-on;
429 };
430 };
431
432 leds {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 led-control = <0x0 0x0 0x3f83f8 0x0>;
436
437 sysled0@3 {
438 reg = <3>;
439 label = "system:green:status";
440 linux,default-trigger = "default-on";
441 };
442
443 sysled1@4 {
444 reg = <4>;
445 label = "system:green:act";
446 linux,default-trigger = "heartbeat";
447 };
448 };
449 };
450
451 flash@1 {
452 #address-cells = <1>;
453 #size-cells = <1>;
454 compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash";
455 spi-max-frequency = <25000000>;
456 reg = <1>;
457 };
458 };
459
460 &esdhc1 {
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_esdhc1>;
463 bus-width = <4>;
464 no-1-8-v;
465 non-removable;
466 no-sdio;
467 no-sd;
468 status = "okay";
469 };
470
471 &fec {
472 pinctrl-names = "default";
473 pinctrl-0 = <&pinctrl_fec>;
474 phy-mode = "mii";
475 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
476 phy-supply = <&vgen3_reg>;
477 status = "okay";
478 };
479
480 &gpio1 {
481 gpio-line-names = "", "", "", "",
482 "", "", "", "",
483 "", "hp-amp-shutdown-b", "", "",
484 "", "", "", "",
485 "", "", "", "",
486 "", "", "", "",
487 "", "", "", "",
488 "", "", "", "";
489
490 unused-sd3-wp-gpio {
491 /*
492 * See pinctrl_esdhc1 below for more details on this
493 */
494 gpio-hog;
495 gpios = <1 GPIO_ACTIVE_HIGH>;
496 output-high;
497 };
498 };
499
500 &i2c2 {
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_i2c2>;
503 status = "okay";
504
505 hpa1: amp@60 {
506 compatible = "ti,tpa6130a2";
507 reg = <0x60>;
508 Vdd-supply = <&reg_3p3v>;
509 };
510
511 ds1341: rtc@68 {
512 compatible = "dallas,ds1341";
513 reg = <0x68>;
514 };
515
516 /* touch nodes default disabled, bootloader will enable the right one */
517
518 touchscreen@4b {
519 compatible = "atmel,maxtouch";
520 reg = <0x4b>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pinctrl_ts>;
523 interrupt-parent = <&gpio3>;
524 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
525 status = "disabled";
526 };
527
528 touchscreen@4c {
529 compatible = "atmel,maxtouch";
530 reg = <0x4c>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_ts>;
533 interrupt-parent = <&gpio3>;
534 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
535 status = "disabled";
536 };
537
538 touchscreen@20 {
539 compatible = "syna,rmi4-i2c";
540 reg = <0x20>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&pinctrl_ts>;
543 interrupt-parent = <&gpio3>;
544 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
545 status = "disabled";
546
547 #address-cells = <1>;
548 #size-cells = <0>;
549
550 rmi4-f01@1 {
551 reg = <0x1>;
552 syna,nosleep-mode = <2>;
553 };
554
555 rmi4-f11@11 {
556 reg = <0x11>;
557 touchscreen-inverted-x;
558 touchscreen-swapped-x-y;
559 syna,sensor-type = <1>;
560 };
561 };
562
563 };
564
565 &ipu_di0_disp1 {
566 remote-endpoint = <&display_in>;
567 };
568
569 &pmu {
570 secure-reg-access;
571 };
572
573 &ssi2 {
574 status = "okay";
575 };
576
577 &uart1 {
578 pinctrl-names = "default";
579 pinctrl-0 = <&pinctrl_uart1>;
580 status = "okay";
581 };
582
583 &uart2 {
584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_uart2>;
586 status = "okay";
587 };
588
589 &uart3 {
590 pinctrl-names = "default";
591 pinctrl-0 = <&pinctrl_uart3>;
592 status = "okay";
593
594 rave-sp {
595 compatible = "zii,rave-sp-rdu1";
596 current-speed = <38400>;
597 #address-cells = <1>;
598 #size-cells = <1>;
599
600 watchdog {
601 compatible = "zii,rave-sp-watchdog";
602 };
603
604 backlight {
605 compatible = "zii,rave-sp-backlight";
606 };
607
608 pwrbutton {
609 compatible = "zii,rave-sp-pwrbutton";
610 };
611
612 eeprom@a3 {
613 compatible = "zii,rave-sp-eeprom";
614 reg = <0xa3 0x2000>;
615 #address-cells = <1>;
616 #size-cells = <1>;
617 zii,eeprom-name = "dds-eeprom";
618 };
619
620 eeprom@a4 {
621 compatible = "zii,rave-sp-eeprom";
622 reg = <0xa4 0x4000>;
623 #address-cells = <1>;
624 #size-cells = <1>;
625 zii,eeprom-name = "main-eeprom";
626 };
627
628 eeprom@ae {
629 compatible = "zii,rave-sp-eeprom";
630 reg = <0xae 0x200>;
631 zii,eeprom-name = "switch-eeprom";
632 /*
633 * Not all RDU1s have this functionality, so we
634 * rely on the bootloader to enable this
635 */
636 status = "disabled";
637 };
638 };
639 };
640
641 &usbh1 {
642 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_usbh1>;
644 dr_mode = "host";
645 phy_type = "ulpi";
646 fsl,usbphy = <&usbh1phy>;
647 disable-over-current;
648 maximum-speed = "full-speed";
649 vbus-supply = <&reg_5p0v_main>;
650 status = "okay";
651 };
652
653 &usbh2 {
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_usbh2>;
656 dr_mode = "host";
657 phy_type = "ulpi";
658 fsl,usbphy = <&usbh2phy>;
659 disable-over-current;
660 vbus-supply = <&reg_5p0v_main>;
661 status = "okay";
662 };
663
664 &usbphy0 {
665 vcc-supply = <&vusb_reg>;
666 };
667
668 &usbotg {
669 dr_mode = "host";
670 disable-over-current;
671 phy_type = "utmi_wide";
672 vbus-supply = <&reg_5p0v_main>;
673 status = "okay";
674 };
675
676 &wdog1 {
677 status = "disabled";
678 };
679
680 &iomuxc {
681 pinctrl-names = "default";
682 pinctrl-0 = <&pinctrl_hog>;
683
684 pinctrl_hog: hoggrp {
685 fsl,pins = <
686 MX51_PAD_GPIO1_9__GPIO1_9 0x5e
687 >;
688 };
689
690 pinctrl_audmux: audmuxgrp {
691 fsl,pins = <
692 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5
693 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85
694 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5
695 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85
696 >;
697 };
698
699 pinctrl_clk26mhz: clk26mhzgrp {
700 fsl,pins = <
701 MX51_PAD_DI1_PIN12__GPIO3_1 0x85
702 >;
703 };
704
705 pinctrl_ecspi1: ecspi1grp {
706 fsl,pins = <
707 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
708 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
709 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
710 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
711 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
712 >;
713 };
714
715 pinctrl_esdhc1: esdhc1grp {
716 fsl,pins = <
717 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
718 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
719 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
720 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
721 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
722 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
723 /*
724 * GPIO1_1 is not directly used by eSDHC1 in
725 * any capacity, but earlier versions of RDU1
726 * used that pin as WP GPIO for eSDHC3 and
727 * because of that that pad has an external
728 * pull-up resistor. This is problematic
729 * because out of reset the pad is configured
730 * as ALT0 which serves as SD1_WP, which, when
731 * pulled high by and external pull-up, will
732 * inhibit execution of any write request to
733 * attached eMMC device.
734 *
735 * To avoid this problem we configure the pad
736 * to ALT1/GPIO and avoid driving SD1_WP
737 * signal high.
738 */
739 MX51_PAD_GPIO1_1__GPIO1_1 0x0000
740 >;
741 };
742
743 pinctrl_fec: fecgrp {
744 fsl,pins = <
745 MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5
746 MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180
747 MX51_PAD_EIM_EB3__FEC_RDATA1 0x180
748 MX51_PAD_EIM_CS2__FEC_RDATA2 0x180
749 MX51_PAD_EIM_CS3__FEC_RDATA3 0x180
750 MX51_PAD_EIM_CS4__FEC_RX_ER 0x180
751 MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084
752 MX51_PAD_EIM_CS5__FEC_CRS 0x180
753 MX51_PAD_NANDF_RB2__FEC_COL 0x2180
754 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180
755 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004
756 MX51_PAD_NANDF_CS3__FEC_MDC 0x2004
757 MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180
758 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004
759 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004
760 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004
761 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
762 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
763 MX51_PAD_EIM_A20__GPIO2_14 0x85
764 >;
765 };
766
767 pinctrl_gpiospi0: gpiospi0grp {
768 fsl,pins = <
769 MX51_PAD_CSI2_D18__GPIO4_11 0x85
770 MX51_PAD_CSI2_D19__GPIO4_12 0x85
771 MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85
772 MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85
773 >;
774 };
775
776 pinctrl_i2c2: i2c2grp {
777 fsl,pins = <
778 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
779 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
780 >;
781 };
782
783 pinctrl_ipu_disp1: ipudisp1grp {
784 fsl,pins = <
785 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
786 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
787 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
788 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
789 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
790 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
791 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
792 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
793 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
794 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
795 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
796 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
797 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
798 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
799 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
800 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
801 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
802 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
803 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
804 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
805 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
806 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
807 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
808 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
809 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
810 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
811 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
812 >;
813 };
814
815 pinctrl_panel: panelgrp {
816 fsl,pins = <
817 MX51_PAD_DI1_D0_CS__GPIO3_3 0x85
818 >;
819 };
820
821 pinctrl_pmic: pmicgrp {
822 fsl,pins = <
823 MX51_PAD_GPIO1_4__GPIO1_4 0x1e0
824 MX51_PAD_GPIO1_8__GPIO1_8 0x21e2
825 >;
826 };
827
828 pinctrl_sndgate26mhz: sndgate26mhzgrp {
829 fsl,pins = <
830 MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
831 >;
832 };
833
834 pinctrl_swi2c: swi2cgrp {
835 fsl,pins = <
836 MX51_PAD_GPIO1_2__GPIO1_2 0xc5
837 MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5
838 >;
839 };
840
841 pinctrl_swmdio: swmdiogrp {
842 fsl,pins = <
843 MX51_PAD_NANDF_D14__GPIO3_26 0x21e6
844 MX51_PAD_NANDF_D15__GPIO3_25 0x21e6
845 >;
846 };
847
848 pinctrl_ts: tsgrp {
849 fsl,pins = <
850 MX51_PAD_CSI1_D8__GPIO3_12 0x04
851 MX51_PAD_CSI1_D9__GPIO3_13 0x85
852 >;
853 };
854
855 pinctrl_uart1: uart1grp {
856 fsl,pins = <
857 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
858 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
859 MX51_PAD_UART1_RTS__UART1_RTS 0x1c4
860 MX51_PAD_UART1_CTS__UART1_CTS 0x1c4
861 >;
862 };
863
864 pinctrl_uart2: uart2grp {
865 fsl,pins = <
866 MX51_PAD_UART2_RXD__UART2_RXD 0xc5
867 MX51_PAD_UART2_TXD__UART2_TXD 0xc5
868 >;
869 };
870
871 pinctrl_uart3: uart3grp {
872 fsl,pins = <
873 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
874 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
875 >;
876 };
877
878 pinctrl_usbgate26mhz: usbgate26mhzgrp {
879 fsl,pins = <
880 MX51_PAD_DISP2_DAT6__GPIO1_19 0x85
881 >;
882 };
883
884 pinctrl_usbh1: usbh1grp {
885 fsl,pins = <
886 MX51_PAD_USBH1_STP__USBH1_STP 0x0
887 MX51_PAD_USBH1_CLK__USBH1_CLK 0x0
888 MX51_PAD_USBH1_DIR__USBH1_DIR 0x0
889 MX51_PAD_USBH1_NXT__USBH1_NXT 0x0
890 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0
891 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0
892 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0
893 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0
894 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0
895 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0
896 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0
897 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0
898 >;
899 };
900
901 pinctrl_usbh1phy: usbh1phygrp {
902 fsl,pins = <
903 MX51_PAD_NANDF_D0__GPIO4_8 0x85
904 >;
905 };
906
907 pinctrl_usbh2: usbh2grp {
908 fsl,pins = <
909 MX51_PAD_EIM_A26__USBH2_STP 0x0
910 MX51_PAD_EIM_A24__USBH2_CLK 0x0
911 MX51_PAD_EIM_A25__USBH2_DIR 0x0
912 MX51_PAD_EIM_A27__USBH2_NXT 0x0
913 MX51_PAD_EIM_D16__USBH2_DATA0 0x0
914 MX51_PAD_EIM_D17__USBH2_DATA1 0x0
915 MX51_PAD_EIM_D18__USBH2_DATA2 0x0
916 MX51_PAD_EIM_D19__USBH2_DATA3 0x0
917 MX51_PAD_EIM_D20__USBH2_DATA4 0x0
918 MX51_PAD_EIM_D21__USBH2_DATA5 0x0
919 MX51_PAD_EIM_D22__USBH2_DATA6 0x0
920 MX51_PAD_EIM_D23__USBH2_DATA7 0x0
921 >;
922 };
923
924 pinctrl_usbh2phy: usbh2phygrp {
925 fsl,pins = <
926 MX51_PAD_NANDF_D1__GPIO4_7 0x85
927 >;
928 };
929 };
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