arch/arm/boot/dts/imx53-mba53.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
   4  * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
   5  */
   6
   7 /dts-v1/;
   8 #include "imx53-tqma53.dtsi"
   9
  10 / {
  11         model = "TQ MBa53 starter kit";
  12         compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
  13
  14         chosen {
  15                 stdout-path = &uart2;
  16         };
  17
  18         backlight {
  19                 compatible = "pwm-backlight";
  20                 pwms = <&pwm2 0 50000>;
  21                 brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
  22                 default-brightness-level = <10>;
  23                 enable-gpios = <&gpio7 7 0>;
  24                 power-supply = <&reg_backlight>;
  25         };
  26
  27         disp1: disp1 {
  28                 compatible = "fsl,imx-parallel-display";
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pinctrl_disp1_1>;
  31                 interface-pix-fmt = "rgb24";
  32                 status = "disabled";
  33
  34                 port {
  35                         display1_in: endpoint {
  36                                 remote-endpoint = <&ipu_di1_disp1>;
  37                         };
  38                 };
  39         };
  40
  41         regulators {
  42                 compatible = "simple-bus";
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 reg_backlight: regulator@0 {
  47                         compatible = "regulator-fixed";
  48                         reg = <0>;
  49                         regulator-name = "lcd-supply";
  50                         gpio = <&gpio2 5 0>;
  51                         startup-delay-us = <5000>;
  52                 };
  53
  54                 reg_3p2v: regulator@1 {
  55                         compatible = "regulator-fixed";
  56                         reg = <1>;
  57                         regulator-name = "3P2V";
  58                         regulator-min-microvolt = <3200000>;
  59                         regulator-max-microvolt = <3200000>;
  60                         regulator-always-on;
  61                 };
  62         };
  63
  64         sound {
  65                 compatible = "tq,imx53-mba53-sgtl5000",
  66                              "fsl,imx-audio-sgtl5000";
  67                 model = "imx53-mba53-sgtl5000";
  68                 ssi-controller = <&ssi2>;
  69                 audio-codec = <&codec>;
  70                 audio-routing =
  71                         "MIC_IN", "Mic Jack",
  72                         "Mic Jack", "Mic Bias",
  73                         "Headphone Jack", "HP_OUT";
  74                 mux-int-port = <2>;
  75                 mux-ext-port = <5>;
  76         };
  77 };
  78
  79 &ldb {
  80         pinctrl-names = "default";
  81         pinctrl-0 = <&pinctrl_lvds1_1>;
  82         status = "disabled";
  83 };
  84
  85 &iomuxc {
  86         lvds1 {
  87                 pinctrl_lvds1_1: lvds1-grp1 {
  88                         fsl,pins = <
  89                                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
  90                                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
  91                                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
  92                                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
  93                                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
  94                         >;
  95                 };
  96
  97                 pinctrl_lvds1_2: lvds1-grp2 {
  98                         fsl,pins = <
  99                                 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
 100                                 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
 101                                 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
 102                                 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
 103                                 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
 104                         >;
 105                 };
 106         };
 107
 108         disp1 {
 109                 pinctrl_disp1_1: disp1-grp1 {
 110                         fsl,pins = <
 111                                 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
 112                                 MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
 113                                 MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
 114                                 MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
 115                                 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
 116                                 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
 117                                 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
 118                                 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
 119                                 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
 120                                 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
 121                                 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
 122                                 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
 123                                 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
 124                                 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
 125                                 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
 126                                 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
 127                                 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
 128                                 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
 129                                 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
 130                                 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
 131                                 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
 132                                 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
 133                                 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
 134                                 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
 135                                 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
 136                                 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
 137                                 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
 138                                 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
 139                         >;
 140                 };
 141         };
 142
 143         tve {
 144                 pinctrl_vga_sync_1: vgasync-grp1 {
 145                         fsl,pins = <
 146                                 /* VGA_VSYNC, HSYNC with max drive strength */
 147                                 MX53_PAD_EIM_CS1__IPU_DI1_PIN6     0xe6
 148                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN4    0xe6
 149                         >;
 150                 };
 151         };
 152 };
 153
 154 &ipu_di1_disp1 {
 155         remote-endpoint = <&display1_in>;
 156 };
 157
 158 &cspi {
 159         status = "okay";
 160 };
 161
 162 &audmux {
 163         status = "okay";
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_audmux>;
 166 };
 167
 168 &i2c2 {
 169         codec: sgtl5000@a {
 170                 compatible = "fsl,sgtl5000";
 171                 reg = <0x0a>;
 172                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
 173                 VDDA-supply = <&reg_3p2v>;
 174                 VDDIO-supply = <&reg_3p2v>;
 175         };
 176
 177         expander: pca9554@20 {
 178                 compatible = "pca9554";
 179                 reg = <0x20>;
 180                 interrupts = <109>;
 181                 #gpio-cells = <2>;
 182                 gpio-controller;
 183         };
 184
 185         sensor2: lm75@49 {
 186                 compatible = "lm75";
 187                 reg = <0x49>;
 188         };
 189 };
 190
 191 &fec {
 192         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 193         status = "okay";
 194 };
 195
 196 &esdhc2 {
 197         status = "okay";
 198 };
 199
 200 &uart3 {
 201         status = "okay";
 202 };
 203
 204 &ecspi1 {
 205         status = "okay";
 206 };
 207
 208 &usbotg {
 209         dr_mode = "host";
 210         status = "okay";
 211 };
 212
 213 &usbh1 {
 214         status = "okay";
 215 };
 216
 217 &uart1 {
 218         status = "okay";
 219 };
 220
 221 &ssi2 {
 222         status = "okay";
 223 };
 224
 225 &uart2 {
 226         status = "okay";
 227 };
 228
 229 &can1 {
 230         status = "okay";
 231 };
 232
 233 &can2 {
 234         status = "okay";
 235 };
 236
 237 &i2c3 {
 238         status = "okay";
 239 };
 240
 241 &tve {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_vga_sync_1>;
 244         ddc-i2c-bus = <&i2c3>;
 245         fsl,tve-mode = "vga";
 246         fsl,hsync-pin = <4>;
 247         fsl,vsync-pin = <6>;
 248         status = "okay";
 249 };