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Merge tag 'v4.20' into for-linus
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx53.dtsi
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include "imx53-pinfunc.h"
14 #include <dt-bindings/clock/imx5-clock.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18
19 / {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 /*
23 * The decompressor and also some bootloaders rely on a
24 * pre-existing /chosen node to be available to insert the
25 * command line and merge other ATAGS info.
26 * Also for U-Boot there must be a pre-existing /memory node.
27 */
28 chosen {};
29 memory { device_type = "memory"; };
30
31 aliases {
32 ethernet0 = &fec;
33 gpio0 = &gpio1;
34 gpio1 = &gpio2;
35 gpio2 = &gpio3;
36 gpio3 = &gpio4;
37 gpio4 = &gpio5;
38 gpio5 = &gpio6;
39 gpio6 = &gpio7;
40 i2c0 = &i2c1;
41 i2c1 = &i2c2;
42 i2c2 = &i2c3;
43 mmc0 = &esdhc1;
44 mmc1 = &esdhc2;
45 mmc2 = &esdhc3;
46 mmc3 = &esdhc4;
47 serial0 = &uart1;
48 serial1 = &uart2;
49 serial2 = &uart3;
50 serial3 = &uart4;
51 serial4 = &uart5;
52 spi0 = &ecspi1;
53 spi1 = &ecspi2;
54 spi2 = &cspi;
55 };
56
57 cpus {
58 #address-cells = <1>;
59 #size-cells = <0>;
60 cpu0: cpu@0 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a8";
63 reg = <0x0>;
64 clocks = <&clks IMX5_CLK_ARM>;
65 clock-latency = <61036>;
66 voltage-tolerance = <5>;
67 operating-points = <
68 /* kHz */
69 166666 850000
70 400000 900000
71 800000 1050000
72 1000000 1200000
73 1200000 1300000
74 >;
75 };
76 };
77
78 display-subsystem {
79 compatible = "fsl,imx-display-subsystem";
80 ports = <&ipu_di0>, <&ipu_di1>;
81 };
82
83 tzic: tz-interrupt-controller@fffc000 {
84 compatible = "fsl,imx53-tzic", "fsl,tzic";
85 interrupt-controller;
86 #interrupt-cells = <1>;
87 reg = <0x0fffc000 0x4000>;
88 };
89
90 clocks {
91 ckil {
92 compatible = "fsl,imx-ckil", "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <32768>;
95 };
96
97 ckih1 {
98 compatible = "fsl,imx-ckih1", "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <22579200>;
101 };
102
103 ckih2 {
104 compatible = "fsl,imx-ckih2", "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <0>;
107 };
108
109 osc {
110 compatible = "fsl,imx-osc", "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <24000000>;
113 };
114 };
115
116 pmu: pmu {
117 compatible = "arm,cortex-a8-pmu";
118 interrupt-parent = <&tzic>;
119 interrupts = <77>;
120 };
121
122 usbphy0: usbphy-0 {
123 compatible = "usb-nop-xceiv";
124 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
125 clock-names = "main_clk";
126 #phy-cells = <0>;
127 status = "okay";
128 };
129
130 usbphy1: usbphy-1 {
131 compatible = "usb-nop-xceiv";
132 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
133 clock-names = "main_clk";
134 #phy-cells = <0>;
135 status = "okay";
136 };
137
138 soc {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 compatible = "simple-bus";
142 interrupt-parent = <&tzic>;
143 ranges;
144
145 sata: sata@10000000 {
146 compatible = "fsl,imx53-ahci";
147 reg = <0x10000000 0x1000>;
148 interrupts = <28>;
149 clocks = <&clks IMX5_CLK_SATA_GATE>,
150 <&clks IMX5_CLK_SATA_REF>,
151 <&clks IMX5_CLK_AHB>;
152 clock-names = "sata", "sata_ref", "ahb";
153 status = "disabled";
154 };
155
156 ipu: ipu@18000000 {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "fsl,imx53-ipu";
160 reg = <0x18000000 0x08000000>;
161 interrupts = <11 10>;
162 clocks = <&clks IMX5_CLK_IPU_GATE>,
163 <&clks IMX5_CLK_IPU_DI0_GATE>,
164 <&clks IMX5_CLK_IPU_DI1_GATE>;
165 clock-names = "bus", "di0", "di1";
166 resets = <&src 2>;
167
168 ipu_csi0: port@0 {
169 reg = <0>;
170 };
171
172 ipu_csi1: port@1 {
173 reg = <1>;
174 };
175
176 ipu_di0: port@2 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 reg = <2>;
180
181 ipu_di0_disp0: endpoint@0 {
182 reg = <0>;
183 };
184
185 ipu_di0_lvds0: endpoint@1 {
186 reg = <1>;
187 remote-endpoint = <&lvds0_in>;
188 };
189 };
190
191 ipu_di1: port@3 {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 reg = <3>;
195
196 ipu_di1_disp1: endpoint@0 {
197 reg = <0>;
198 };
199
200 ipu_di1_lvds1: endpoint@1 {
201 reg = <1>;
202 remote-endpoint = <&lvds1_in>;
203 };
204
205 ipu_di1_tve: endpoint@2 {
206 reg = <2>;
207 remote-endpoint = <&tve_in>;
208 };
209 };
210 };
211
212 aips@50000000 { /* AIPS1 */
213 compatible = "fsl,aips-bus", "simple-bus";
214 #address-cells = <1>;
215 #size-cells = <1>;
216 reg = <0x50000000 0x10000000>;
217 ranges;
218
219 spba@50000000 {
220 compatible = "fsl,spba-bus", "simple-bus";
221 #address-cells = <1>;
222 #size-cells = <1>;
223 reg = <0x50000000 0x40000>;
224 ranges;
225
226 esdhc1: esdhc@50004000 {
227 compatible = "fsl,imx53-esdhc";
228 reg = <0x50004000 0x4000>;
229 interrupts = <1>;
230 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
231 <&clks IMX5_CLK_DUMMY>,
232 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
233 clock-names = "ipg", "ahb", "per";
234 bus-width = <4>;
235 status = "disabled";
236 };
237
238 esdhc2: esdhc@50008000 {
239 compatible = "fsl,imx53-esdhc";
240 reg = <0x50008000 0x4000>;
241 interrupts = <2>;
242 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
243 <&clks IMX5_CLK_DUMMY>,
244 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
245 clock-names = "ipg", "ahb", "per";
246 bus-width = <4>;
247 status = "disabled";
248 };
249
250 uart3: serial@5000c000 {
251 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
252 reg = <0x5000c000 0x4000>;
253 interrupts = <33>;
254 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
255 <&clks IMX5_CLK_UART3_PER_GATE>;
256 clock-names = "ipg", "per";
257 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
258 dma-names = "rx", "tx";
259 status = "disabled";
260 };
261
262 ecspi1: spi@50010000 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
266 reg = <0x50010000 0x4000>;
267 interrupts = <36>;
268 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
269 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
270 clock-names = "ipg", "per";
271 status = "disabled";
272 };
273
274 ssi2: ssi@50014000 {
275 #sound-dai-cells = <0>;
276 compatible = "fsl,imx53-ssi",
277 "fsl,imx51-ssi",
278 "fsl,imx21-ssi";
279 reg = <0x50014000 0x4000>;
280 interrupts = <30>;
281 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
282 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
283 clock-names = "ipg", "baud";
284 dmas = <&sdma 24 1 0>,
285 <&sdma 25 1 0>;
286 dma-names = "rx", "tx";
287 fsl,fifo-depth = <15>;
288 status = "disabled";
289 };
290
291 esdhc3: esdhc@50020000 {
292 compatible = "fsl,imx53-esdhc";
293 reg = <0x50020000 0x4000>;
294 interrupts = <3>;
295 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
296 <&clks IMX5_CLK_DUMMY>,
297 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
298 clock-names = "ipg", "ahb", "per";
299 bus-width = <4>;
300 status = "disabled";
301 };
302
303 esdhc4: esdhc@50024000 {
304 compatible = "fsl,imx53-esdhc";
305 reg = <0x50024000 0x4000>;
306 interrupts = <4>;
307 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
308 <&clks IMX5_CLK_DUMMY>,
309 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
310 clock-names = "ipg", "ahb", "per";
311 bus-width = <4>;
312 status = "disabled";
313 };
314 };
315
316 aipstz1: bridge@53f00000 {
317 compatible = "fsl,imx53-aipstz";
318 reg = <0x53f00000 0x60>;
319 };
320
321 usbotg: usb@53f80000 {
322 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
323 reg = <0x53f80000 0x0200>;
324 interrupts = <18>;
325 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
326 fsl,usbmisc = <&usbmisc 0>;
327 fsl,usbphy = <&usbphy0>;
328 status = "disabled";
329 };
330
331 usbh1: usb@53f80200 {
332 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
333 reg = <0x53f80200 0x0200>;
334 interrupts = <14>;
335 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
336 fsl,usbmisc = <&usbmisc 1>;
337 fsl,usbphy = <&usbphy1>;
338 dr_mode = "host";
339 status = "disabled";
340 };
341
342 usbh2: usb@53f80400 {
343 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
344 reg = <0x53f80400 0x0200>;
345 interrupts = <16>;
346 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
347 fsl,usbmisc = <&usbmisc 2>;
348 dr_mode = "host";
349 status = "disabled";
350 };
351
352 usbh3: usb@53f80600 {
353 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
354 reg = <0x53f80600 0x0200>;
355 interrupts = <17>;
356 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
357 fsl,usbmisc = <&usbmisc 3>;
358 dr_mode = "host";
359 status = "disabled";
360 };
361
362 usbmisc: usbmisc@53f80800 {
363 #index-cells = <1>;
364 compatible = "fsl,imx53-usbmisc";
365 reg = <0x53f80800 0x200>;
366 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
367 };
368
369 gpio1: gpio@53f84000 {
370 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
371 reg = <0x53f84000 0x4000>;
372 interrupts = <50 51>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
377 };
378
379 gpio2: gpio@53f88000 {
380 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
381 reg = <0x53f88000 0x4000>;
382 interrupts = <52 53>;
383 gpio-controller;
384 #gpio-cells = <2>;
385 interrupt-controller;
386 #interrupt-cells = <2>;
387 };
388
389 gpio3: gpio@53f8c000 {
390 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
391 reg = <0x53f8c000 0x4000>;
392 interrupts = <54 55>;
393 gpio-controller;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 };
398
399 gpio4: gpio@53f90000 {
400 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
401 reg = <0x53f90000 0x4000>;
402 interrupts = <56 57>;
403 gpio-controller;
404 #gpio-cells = <2>;
405 interrupt-controller;
406 #interrupt-cells = <2>;
407 };
408
409 kpp: kpp@53f94000 {
410 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
411 reg = <0x53f94000 0x4000>;
412 interrupts = <60>;
413 clocks = <&clks IMX5_CLK_DUMMY>;
414 status = "disabled";
415 };
416
417 wdog1: wdog@53f98000 {
418 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
419 reg = <0x53f98000 0x4000>;
420 interrupts = <58>;
421 clocks = <&clks IMX5_CLK_DUMMY>;
422 };
423
424 wdog2: wdog@53f9c000 {
425 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
426 reg = <0x53f9c000 0x4000>;
427 interrupts = <59>;
428 clocks = <&clks IMX5_CLK_DUMMY>;
429 status = "disabled";
430 };
431
432 gpt: timer@53fa0000 {
433 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
434 reg = <0x53fa0000 0x4000>;
435 interrupts = <39>;
436 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
437 <&clks IMX5_CLK_GPT_HF_GATE>;
438 clock-names = "ipg", "per";
439 };
440
441 srtc: rtc@53fa4000 {
442 compatible = "fsl,imx53-rtc";
443 reg = <0x53fa4000 0x4000>;
444 interrupts = <24>;
445 clocks = <&clks IMX5_CLK_SRTC_GATE>;
446 };
447
448 iomuxc: iomuxc@53fa8000 {
449 compatible = "fsl,imx53-iomuxc";
450 reg = <0x53fa8000 0x4000>;
451 };
452
453 gpr: iomuxc-gpr@53fa8000 {
454 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
455 reg = <0x53fa8000 0xc>;
456 };
457
458 ldb: ldb@53fa8008 {
459 #address-cells = <1>;
460 #size-cells = <0>;
461 compatible = "fsl,imx53-ldb";
462 reg = <0x53fa8008 0x4>;
463 gpr = <&gpr>;
464 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
465 <&clks IMX5_CLK_LDB_DI1_SEL>,
466 <&clks IMX5_CLK_IPU_DI0_SEL>,
467 <&clks IMX5_CLK_IPU_DI1_SEL>,
468 <&clks IMX5_CLK_LDB_DI0_GATE>,
469 <&clks IMX5_CLK_LDB_DI1_GATE>;
470 clock-names = "di0_pll", "di1_pll",
471 "di0_sel", "di1_sel",
472 "di0", "di1";
473 status = "disabled";
474
475 lvds-channel@0 {
476 #address-cells = <1>;
477 #size-cells = <0>;
478 reg = <0>;
479 status = "disabled";
480
481 port@0 {
482 reg = <0>;
483
484 lvds0_in: endpoint {
485 remote-endpoint = <&ipu_di0_lvds0>;
486 };
487 };
488
489 port@2 {
490 reg = <2>;
491 };
492 };
493
494 lvds-channel@1 {
495 #address-cells = <1>;
496 #size-cells = <0>;
497 reg = <1>;
498 status = "disabled";
499
500 port@1 {
501 reg = <1>;
502
503 lvds1_in: endpoint {
504 remote-endpoint = <&ipu_di1_lvds1>;
505 };
506 };
507
508 port@2 {
509 reg = <2>;
510 };
511 };
512 };
513
514 pwm1: pwm@53fb4000 {
515 #pwm-cells = <2>;
516 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
517 reg = <0x53fb4000 0x4000>;
518 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
519 <&clks IMX5_CLK_PWM1_HF_GATE>;
520 clock-names = "ipg", "per";
521 interrupts = <61>;
522 };
523
524 pwm2: pwm@53fb8000 {
525 #pwm-cells = <2>;
526 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
527 reg = <0x53fb8000 0x4000>;
528 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
529 <&clks IMX5_CLK_PWM2_HF_GATE>;
530 clock-names = "ipg", "per";
531 interrupts = <94>;
532 };
533
534 uart1: serial@53fbc000 {
535 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
536 reg = <0x53fbc000 0x4000>;
537 interrupts = <31>;
538 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
539 <&clks IMX5_CLK_UART1_PER_GATE>;
540 clock-names = "ipg", "per";
541 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
542 dma-names = "rx", "tx";
543 status = "disabled";
544 };
545
546 uart2: serial@53fc0000 {
547 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
548 reg = <0x53fc0000 0x4000>;
549 interrupts = <32>;
550 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
551 <&clks IMX5_CLK_UART2_PER_GATE>;
552 clock-names = "ipg", "per";
553 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
554 dma-names = "rx", "tx";
555 status = "disabled";
556 };
557
558 can1: can@53fc8000 {
559 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
560 reg = <0x53fc8000 0x4000>;
561 interrupts = <82>;
562 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
563 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
564 clock-names = "ipg", "per";
565 status = "disabled";
566 };
567
568 can2: can@53fcc000 {
569 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
570 reg = <0x53fcc000 0x4000>;
571 interrupts = <83>;
572 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
573 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
574 clock-names = "ipg", "per";
575 status = "disabled";
576 };
577
578 src: src@53fd0000 {
579 compatible = "fsl,imx53-src", "fsl,imx51-src";
580 reg = <0x53fd0000 0x4000>;
581 #reset-cells = <1>;
582 };
583
584 clks: ccm@53fd4000{
585 compatible = "fsl,imx53-ccm";
586 reg = <0x53fd4000 0x4000>;
587 interrupts = <0 71 0x04 0 72 0x04>;
588 #clock-cells = <1>;
589 };
590
591 gpio5: gpio@53fdc000 {
592 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
593 reg = <0x53fdc000 0x4000>;
594 interrupts = <103 104>;
595 gpio-controller;
596 #gpio-cells = <2>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 };
600
601 gpio6: gpio@53fe0000 {
602 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
603 reg = <0x53fe0000 0x4000>;
604 interrupts = <105 106>;
605 gpio-controller;
606 #gpio-cells = <2>;
607 interrupt-controller;
608 #interrupt-cells = <2>;
609 };
610
611 gpio7: gpio@53fe4000 {
612 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
613 reg = <0x53fe4000 0x4000>;
614 interrupts = <107 108>;
615 gpio-controller;
616 #gpio-cells = <2>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
619 };
620
621 i2c3: i2c@53fec000 {
622 #address-cells = <1>;
623 #size-cells = <0>;
624 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
625 reg = <0x53fec000 0x4000>;
626 interrupts = <64>;
627 clocks = <&clks IMX5_CLK_I2C3_GATE>;
628 status = "disabled";
629 };
630
631 uart4: serial@53ff0000 {
632 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
633 reg = <0x53ff0000 0x4000>;
634 interrupts = <13>;
635 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
636 <&clks IMX5_CLK_UART4_PER_GATE>;
637 clock-names = "ipg", "per";
638 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
639 dma-names = "rx", "tx";
640 status = "disabled";
641 };
642 };
643
644 aips@60000000 { /* AIPS2 */
645 compatible = "fsl,aips-bus", "simple-bus";
646 #address-cells = <1>;
647 #size-cells = <1>;
648 reg = <0x60000000 0x10000000>;
649 ranges;
650
651 aipstz2: bridge@63f00000 {
652 compatible = "fsl,imx53-aipstz";
653 reg = <0x63f00000 0x60>;
654 };
655
656 iim: iim@63f98000 {
657 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
658 reg = <0x63f98000 0x4000>;
659 interrupts = <69>;
660 clocks = <&clks IMX5_CLK_IIM_GATE>;
661 };
662
663 uart5: serial@63f90000 {
664 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
665 reg = <0x63f90000 0x4000>;
666 interrupts = <86>;
667 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
668 <&clks IMX5_CLK_UART5_PER_GATE>;
669 clock-names = "ipg", "per";
670 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
671 dma-names = "rx", "tx";
672 status = "disabled";
673 };
674
675 tigerp: tigerp@63fa0000 {
676 compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp";
677 reg = <0x63fa0000 0x28>;
678 };
679
680 owire: owire@63fa4000 {
681 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
682 reg = <0x63fa4000 0x4000>;
683 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
684 status = "disabled";
685 };
686
687 ecspi2: spi@63fac000 {
688 #address-cells = <1>;
689 #size-cells = <0>;
690 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
691 reg = <0x63fac000 0x4000>;
692 interrupts = <37>;
693 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
694 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
695 clock-names = "ipg", "per";
696 status = "disabled";
697 };
698
699 sdma: sdma@63fb0000 {
700 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
701 reg = <0x63fb0000 0x4000>;
702 interrupts = <6>;
703 clocks = <&clks IMX5_CLK_SDMA_GATE>,
704 <&clks IMX5_CLK_SDMA_GATE>;
705 clock-names = "ipg", "ahb";
706 #dma-cells = <3>;
707 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
708 };
709
710 cspi: spi@63fc0000 {
711 #address-cells = <1>;
712 #size-cells = <0>;
713 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
714 reg = <0x63fc0000 0x4000>;
715 interrupts = <38>;
716 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
717 <&clks IMX5_CLK_CSPI_IPG_GATE>;
718 clock-names = "ipg", "per";
719 status = "disabled";
720 };
721
722 i2c2: i2c@63fc4000 {
723 #address-cells = <1>;
724 #size-cells = <0>;
725 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
726 reg = <0x63fc4000 0x4000>;
727 interrupts = <63>;
728 clocks = <&clks IMX5_CLK_I2C2_GATE>;
729 status = "disabled";
730 };
731
732 i2c1: i2c@63fc8000 {
733 #address-cells = <1>;
734 #size-cells = <0>;
735 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
736 reg = <0x63fc8000 0x4000>;
737 interrupts = <62>;
738 clocks = <&clks IMX5_CLK_I2C1_GATE>;
739 status = "disabled";
740 };
741
742 ssi1: ssi@63fcc000 {
743 #sound-dai-cells = <0>;
744 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
745 "fsl,imx21-ssi";
746 reg = <0x63fcc000 0x4000>;
747 interrupts = <29>;
748 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
749 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
750 clock-names = "ipg", "baud";
751 dmas = <&sdma 28 0 0>,
752 <&sdma 29 0 0>;
753 dma-names = "rx", "tx";
754 fsl,fifo-depth = <15>;
755 status = "disabled";
756 };
757
758 audmux: audmux@63fd0000 {
759 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
760 reg = <0x63fd0000 0x4000>;
761 status = "disabled";
762 };
763
764 nfc: nand@63fdb000 {
765 compatible = "fsl,imx53-nand";
766 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
767 interrupts = <8>;
768 clocks = <&clks IMX5_CLK_NFC_GATE>;
769 status = "disabled";
770 };
771
772 ssi3: ssi@63fe8000 {
773 #sound-dai-cells = <0>;
774 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
775 "fsl,imx21-ssi";
776 reg = <0x63fe8000 0x4000>;
777 interrupts = <96>;
778 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
779 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
780 clock-names = "ipg", "baud";
781 dmas = <&sdma 46 0 0>,
782 <&sdma 47 0 0>;
783 dma-names = "rx", "tx";
784 fsl,fifo-depth = <15>;
785 status = "disabled";
786 };
787
788 fec: ethernet@63fec000 {
789 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
790 reg = <0x63fec000 0x4000>;
791 interrupts = <87>;
792 clocks = <&clks IMX5_CLK_FEC_GATE>,
793 <&clks IMX5_CLK_FEC_GATE>,
794 <&clks IMX5_CLK_FEC_GATE>;
795 clock-names = "ipg", "ahb", "ptp";
796 status = "disabled";
797 };
798
799 tve: tve@63ff0000 {
800 compatible = "fsl,imx53-tve";
801 reg = <0x63ff0000 0x1000>;
802 interrupts = <92>;
803 clocks = <&clks IMX5_CLK_TVE_GATE>,
804 <&clks IMX5_CLK_IPU_DI1_SEL>;
805 clock-names = "tve", "di_sel";
806 status = "disabled";
807
808 port {
809 tve_in: endpoint {
810 remote-endpoint = <&ipu_di1_tve>;
811 };
812 };
813 };
814
815 vpu: vpu@63ff4000 {
816 compatible = "fsl,imx53-vpu", "cnm,coda7541";
817 reg = <0x63ff4000 0x1000>;
818 interrupts = <9>;
819 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
820 <&clks IMX5_CLK_VPU_GATE>;
821 clock-names = "per", "ahb";
822 resets = <&src 1>;
823 iram = <&ocram>;
824 };
825
826 sahara: crypto@63ff8000 {
827 compatible = "fsl,imx53-sahara";
828 reg = <0x63ff8000 0x4000>;
829 interrupts = <19 20>;
830 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
831 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
832 clock-names = "ipg", "ahb";
833 };
834 };
835
836 ocram: sram@f8000000 {
837 compatible = "mmio-sram";
838 reg = <0xf8000000 0x20000>;
839 clocks = <&clks IMX5_CLK_OCRAM>;
840 };
841 };
842 };
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