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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / imx6q.dtsi
1
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "imx6q-pinfunc.h"
13 #include "imx6qdl.dtsi"
14
15 / {
16 aliases {
17 ipu1 = &ipu2;
18 spi4 = &ecspi5;
19 };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 compatible = "arm,cortex-a9";
27 device_type = "cpu";
28 reg = <0>;
29 next-level-cache = <&L2>;
30 operating-points = <
31 /* kHz uV */
32 1200000 1275000
33 996000 1250000
34 852000 1250000
35 792000 1175000
36 396000 975000
37 >;
38 fsl,soc-operating-points = <
39 /* ARM kHz SOC-PU uV */
40 1200000 1275000
41 996000 1250000
42 852000 1250000
43 792000 1175000
44 396000 1175000
45 >;
46 clock-latency = <61036>; /* two CLK32 periods */
47 #cooling-cells = <2>;
48 clocks = <&clks IMX6QDL_CLK_ARM>,
49 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
50 <&clks IMX6QDL_CLK_STEP>,
51 <&clks IMX6QDL_CLK_PLL1_SW>,
52 <&clks IMX6QDL_CLK_PLL1_SYS>;
53 clock-names = "arm", "pll2_pfd2_396m", "step",
54 "pll1_sw", "pll1_sys";
55 arm-supply = <&reg_arm>;
56 pu-supply = <&reg_pu>;
57 soc-supply = <&reg_soc>;
58 };
59
60 cpu1: cpu@1 {
61 compatible = "arm,cortex-a9";
62 device_type = "cpu";
63 reg = <1>;
64 next-level-cache = <&L2>;
65 operating-points = <
66 /* kHz uV */
67 1200000 1275000
68 996000 1250000
69 852000 1250000
70 792000 1175000
71 396000 975000
72 >;
73 fsl,soc-operating-points = <
74 /* ARM kHz SOC-PU uV */
75 1200000 1275000
76 996000 1250000
77 852000 1250000
78 792000 1175000
79 396000 1175000
80 >;
81 clock-latency = <61036>; /* two CLK32 periods */
82 clocks = <&clks IMX6QDL_CLK_ARM>,
83 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
84 <&clks IMX6QDL_CLK_STEP>,
85 <&clks IMX6QDL_CLK_PLL1_SW>,
86 <&clks IMX6QDL_CLK_PLL1_SYS>;
87 clock-names = "arm", "pll2_pfd2_396m", "step",
88 "pll1_sw", "pll1_sys";
89 arm-supply = <&reg_arm>;
90 pu-supply = <&reg_pu>;
91 soc-supply = <&reg_soc>;
92 };
93
94 cpu2: cpu@2 {
95 compatible = "arm,cortex-a9";
96 device_type = "cpu";
97 reg = <2>;
98 next-level-cache = <&L2>;
99 operating-points = <
100 /* kHz uV */
101 1200000 1275000
102 996000 1250000
103 852000 1250000
104 792000 1175000
105 396000 975000
106 >;
107 fsl,soc-operating-points = <
108 /* ARM kHz SOC-PU uV */
109 1200000 1275000
110 996000 1250000
111 852000 1250000
112 792000 1175000
113 396000 1175000
114 >;
115 clock-latency = <61036>; /* two CLK32 periods */
116 clocks = <&clks IMX6QDL_CLK_ARM>,
117 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
118 <&clks IMX6QDL_CLK_STEP>,
119 <&clks IMX6QDL_CLK_PLL1_SW>,
120 <&clks IMX6QDL_CLK_PLL1_SYS>;
121 clock-names = "arm", "pll2_pfd2_396m", "step",
122 "pll1_sw", "pll1_sys";
123 arm-supply = <&reg_arm>;
124 pu-supply = <&reg_pu>;
125 soc-supply = <&reg_soc>;
126 };
127
128 cpu3: cpu@3 {
129 compatible = "arm,cortex-a9";
130 device_type = "cpu";
131 reg = <3>;
132 next-level-cache = <&L2>;
133 operating-points = <
134 /* kHz uV */
135 1200000 1275000
136 996000 1250000
137 852000 1250000
138 792000 1175000
139 396000 975000
140 >;
141 fsl,soc-operating-points = <
142 /* ARM kHz SOC-PU uV */
143 1200000 1275000
144 996000 1250000
145 852000 1250000
146 792000 1175000
147 396000 1175000
148 >;
149 clock-latency = <61036>; /* two CLK32 periods */
150 clocks = <&clks IMX6QDL_CLK_ARM>,
151 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
152 <&clks IMX6QDL_CLK_STEP>,
153 <&clks IMX6QDL_CLK_PLL1_SW>,
154 <&clks IMX6QDL_CLK_PLL1_SYS>;
155 clock-names = "arm", "pll2_pfd2_396m", "step",
156 "pll1_sw", "pll1_sys";
157 arm-supply = <&reg_arm>;
158 pu-supply = <&reg_pu>;
159 soc-supply = <&reg_soc>;
160 };
161 };
162
163 soc {
164 ocram: sram@900000 {
165 compatible = "mmio-sram";
166 reg = <0x00900000 0x40000>;
167 clocks = <&clks IMX6QDL_CLK_OCRAM>;
168 };
169
170 aips-bus@2000000 { /* AIPS1 */
171 spba-bus@2000000 {
172 ecspi5: ecspi@2018000 {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
176 reg = <0x02018000 0x4000>;
177 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&clks IMX6Q_CLK_ECSPI5>,
179 <&clks IMX6Q_CLK_ECSPI5>;
180 clock-names = "ipg", "per";
181 dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
182 dma-names = "rx", "tx";
183 status = "disabled";
184 };
185 };
186
187 iomuxc: iomuxc@20e0000 {
188 compatible = "fsl,imx6q-iomuxc";
189 };
190 };
191
192 sata: sata@2200000 {
193 compatible = "fsl,imx6q-ahci";
194 reg = <0x02200000 0x4000>;
195 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&clks IMX6QDL_CLK_SATA>,
197 <&clks IMX6QDL_CLK_SATA_REF_100M>,
198 <&clks IMX6QDL_CLK_AHB>;
199 clock-names = "sata", "sata_ref", "ahb";
200 status = "disabled";
201 };
202
203 gpu_vg: gpu@2204000 {
204 compatible = "vivante,gc";
205 reg = <0x02204000 0x4000>;
206 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
208 <&clks IMX6QDL_CLK_GPU2D_CORE>;
209 clock-names = "bus", "core";
210 power-domains = <&pd_pu>;
211 #cooling-cells = <2>;
212 };
213
214 ipu2: ipu@2800000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,imx6q-ipu";
218 reg = <0x02800000 0x400000>;
219 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
220 <0 7 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&clks IMX6QDL_CLK_IPU2>,
222 <&clks IMX6QDL_CLK_IPU2_DI0>,
223 <&clks IMX6QDL_CLK_IPU2_DI1>;
224 clock-names = "bus", "di0", "di1";
225 resets = <&src 4>;
226
227 ipu2_csi0: port@0 {
228 reg = <0>;
229
230 ipu2_csi0_from_mipi_vc2: endpoint {
231 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
232 };
233 };
234
235 ipu2_csi1: port@1 {
236 reg = <1>;
237
238 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
239 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
240 };
241 };
242
243 ipu2_di0: port@2 {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 reg = <2>;
247
248 ipu2_di0_disp0: disp0-endpoint {
249 };
250
251 ipu2_di0_hdmi: hdmi-endpoint {
252 remote-endpoint = <&hdmi_mux_2>;
253 };
254
255 ipu2_di0_mipi: mipi-endpoint {
256 remote-endpoint = <&mipi_mux_2>;
257 };
258
259 ipu2_di0_lvds0: lvds0-endpoint {
260 remote-endpoint = <&lvds0_mux_2>;
261 };
262
263 ipu2_di0_lvds1: lvds1-endpoint {
264 remote-endpoint = <&lvds1_mux_2>;
265 };
266 };
267
268 ipu2_di1: port@3 {
269 #address-cells = <1>;
270 #size-cells = <0>;
271 reg = <3>;
272
273 ipu2_di1_hdmi: hdmi-endpoint {
274 remote-endpoint = <&hdmi_mux_3>;
275 };
276
277 ipu2_di1_mipi: mipi-endpoint {
278 remote-endpoint = <&mipi_mux_3>;
279 };
280
281 ipu2_di1_lvds0: lvds0-endpoint {
282 remote-endpoint = <&lvds0_mux_3>;
283 };
284
285 ipu2_di1_lvds1: lvds1-endpoint {
286 remote-endpoint = <&lvds1_mux_3>;
287 };
288 };
289 };
290 };
291
292 capture-subsystem {
293 compatible = "fsl,imx-capture-subsystem";
294 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
295 };
296
297 display-subsystem {
298 compatible = "fsl,imx-display-subsystem";
299 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
300 };
301
302 gpu-subsystem {
303 compatible = "fsl,imx-gpu-subsystem";
304 cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
305 };
306 };
307
308 &gpio1 {
309 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
310 <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
311 <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
312 <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
313 <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
314 <&iomuxc 22 116 10>;
315 };
316
317 &gpio2 {
318 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
319 <&iomuxc 31 44 1>;
320 };
321
322 &gpio3 {
323 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
324 };
325
326 &gpio4 {
327 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
328 };
329
330 &gpio5 {
331 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
332 <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
333 };
334
335 &gpio6 {
336 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
337 <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
338 <&iomuxc 31 86 1>;
339 };
340
341 &gpio7 {
342 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
343 };
344
345 &gpr {
346 ipu1_csi0_mux {
347 compatible = "video-mux";
348 mux-controls = <&mux 0>;
349 #address-cells = <1>;
350 #size-cells = <0>;
351
352 port@0 {
353 reg = <0>;
354
355 ipu1_csi0_mux_from_mipi_vc0: endpoint {
356 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
357 };
358 };
359
360 port@1 {
361 reg = <1>;
362
363 ipu1_csi0_mux_from_parallel_sensor: endpoint {
364 };
365 };
366
367 port@2 {
368 reg = <2>;
369
370 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
371 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
372 };
373 };
374 };
375
376 ipu2_csi1_mux {
377 compatible = "video-mux";
378 mux-controls = <&mux 1>;
379 #address-cells = <1>;
380 #size-cells = <0>;
381
382 port@0 {
383 reg = <0>;
384
385 ipu2_csi1_mux_from_mipi_vc3: endpoint {
386 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
387 };
388 };
389
390 port@1 {
391 reg = <1>;
392
393 ipu2_csi1_mux_from_parallel_sensor: endpoint {
394 };
395 };
396
397 port@2 {
398 reg = <2>;
399
400 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
401 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
402 };
403 };
404 };
405 };
406
407 &hdmi {
408 compatible = "fsl,imx6q-hdmi";
409
410 port@2 {
411 reg = <2>;
412
413 hdmi_mux_2: endpoint {
414 remote-endpoint = <&ipu2_di0_hdmi>;
415 };
416 };
417
418 port@3 {
419 reg = <3>;
420
421 hdmi_mux_3: endpoint {
422 remote-endpoint = <&ipu2_di1_hdmi>;
423 };
424 };
425 };
426
427 &ipu1_csi1 {
428 ipu1_csi1_from_mipi_vc1: endpoint {
429 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
430 };
431 };
432
433 &ldb {
434 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
435 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
436 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
437 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
438 clock-names = "di0_pll", "di1_pll",
439 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
440 "di0", "di1";
441
442 lvds-channel@0 {
443 port@2 {
444 reg = <2>;
445
446 lvds0_mux_2: endpoint {
447 remote-endpoint = <&ipu2_di0_lvds0>;
448 };
449 };
450
451 port@3 {
452 reg = <3>;
453
454 lvds0_mux_3: endpoint {
455 remote-endpoint = <&ipu2_di1_lvds0>;
456 };
457 };
458 };
459
460 lvds-channel@1 {
461 port@2 {
462 reg = <2>;
463
464 lvds1_mux_2: endpoint {
465 remote-endpoint = <&ipu2_di0_lvds1>;
466 };
467 };
468
469 port@3 {
470 reg = <3>;
471
472 lvds1_mux_3: endpoint {
473 remote-endpoint = <&ipu2_di1_lvds1>;
474 };
475 };
476 };
477 };
478
479 &mipi_csi {
480 port@1 {
481 reg = <1>;
482
483 mipi_vc0_to_ipu1_csi0_mux: endpoint {
484 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
485 };
486 };
487
488 port@2 {
489 reg = <2>;
490
491 mipi_vc1_to_ipu1_csi1: endpoint {
492 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
493 };
494 };
495
496 port@3 {
497 reg = <3>;
498
499 mipi_vc2_to_ipu2_csi0: endpoint {
500 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
501 };
502 };
503
504 port@4 {
505 reg = <4>;
506
507 mipi_vc3_to_ipu2_csi1_mux: endpoint {
508 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
509 };
510 };
511 };
512
513 &mipi_dsi {
514 ports {
515 port@2 {
516 reg = <2>;
517
518 mipi_mux_2: endpoint {
519 remote-endpoint = <&ipu2_di0_mipi>;
520 };
521 };
522
523 port@3 {
524 reg = <3>;
525
526 mipi_mux_3: endpoint {
527 remote-endpoint = <&ipu2_di1_mipi>;
528 };
529 };
530 };
531 };
532
533 &mux {
534 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
535 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
536 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
537 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
538 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
539 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
540 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
541 };
542
543 &vpu {
544 compatible = "fsl,imx6q-vpu", "cnm,coda960";
545 };
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