2 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/gpio/gpio.h>
15 model = "Phytec phyFLEX-i.MX6 Quad";
16 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
19 device_type = "memory";
20 reg = <0x10000000 0x80000000>;
24 compatible = "simple-bus";
28 reg_usb_otg_vbus: regulator@0 {
29 compatible = "regulator-fixed";
31 regulator-name = "usb_otg_vbus";
32 regulator-min-microvolt = <5000000>;
33 regulator-max-microvolt = <5000000>;
38 reg_usb_h1_vbus: regulator@1 {
39 compatible = "regulator-fixed";
41 regulator-name = "usb_h1_vbus";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
50 compatible = "gpio-leds";
53 label = "phyflex:green";
54 gpios = <&gpio1 30 0>;
58 label = "phyflex:red";
59 gpios = <&gpio2 31 0>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_audmux>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_flexcan1>;
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_ecspi3>;
80 cs-gpios = <&gpio4 24 0>;
83 compatible = "m25p80", "jedec,spi-nor";
84 spi-max-frequency = <20000000>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet>;
92 phy-handle = <ðphy>;
94 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
95 phy-supply = <&vdd_eth_io_reg>;
102 ethphy: ethernet-phy@0 {
103 compatible = "ethernet-phy-ieee802.3-c22";
105 txc-skew-ps = <1680>;
106 rxc-skew-ps = <1860>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_gpmi_nand>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_i2c1>;
124 compatible = "atmel,24c32";
129 compatible = "dlg,da9063";
131 interrupt-parent = <&gpio2>;
132 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
133 interrupt-controller;
136 vddcore_reg: bcore1 {
137 regulator-min-microvolt = <730000>;
138 regulator-max-microvolt = <1380000>;
143 regulator-min-microvolt = <730000>;
144 regulator-max-microvolt = <1380000>;
149 regulator-min-microvolt = <1500000>;
150 regulator-max-microvolt = <1500000>;
155 regulator-min-microvolt = <3300000>;
156 regulator-max-microvolt = <3300000>;
160 vdd_buckmem_reg: bmem {
161 regulator-min-microvolt = <3300000>;
162 regulator-max-microvolt = <3300000>;
167 regulator-min-microvolt = <1200000>;
168 regulator-max-microvolt = <1200000>;
172 vdd_eth_io_reg: ldo4 {
173 regulator-min-microvolt = <2500000>;
174 regulator-max-microvolt = <2500000>;
178 vdd_mx6_snvs_reg: ldo5 {
179 regulator-min-microvolt = <3000000>;
180 regulator-max-microvolt = <3000000>;
184 vdd_3v3_pmic_io_reg: ldo6 {
185 regulator-min-microvolt = <3300000>;
186 regulator-max-microvolt = <3300000>;
191 regulator-min-microvolt = <3300000>;
192 regulator-max-microvolt = <3300000>;
196 regulator-min-microvolt = <3300000>;
197 regulator-max-microvolt = <3300000>;
200 vdd_mx6_high_reg: ldo11 {
201 regulator-min-microvolt = <3000000>;
202 regulator-max-microvolt = <3000000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c2>;
212 clock-frequency = <100000>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_i2c3>;
218 clock-frequency = <100000>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_hog>;
225 imx6q-phytec-pfla02 {
226 pinctrl_hog: hoggrp {
228 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
229 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
230 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */
231 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
232 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
236 pinctrl_ecspi3: ecspi3grp {
238 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
239 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
240 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
244 pinctrl_enet: enetgrp {
246 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
247 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
248 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
249 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
250 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
251 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
252 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
253 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
254 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
255 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
256 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
257 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
258 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
259 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
260 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
261 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
265 pinctrl_flexcan1: flexcan1grp {
267 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
268 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
272 pinctrl_gpmi_nand: gpminandgrp {
274 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
275 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
276 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
277 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
278 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
279 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
280 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
281 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
282 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
283 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
284 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
285 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
286 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
287 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
288 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
289 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
290 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
294 pinctrl_i2c1: i2c1grp {
296 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
297 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
301 pinctrl_i2c2: i2c2grp {
303 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
304 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
308 pinctrl_i2c3: i2c3grp {
310 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
311 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
315 pinctrl_pcie: pciegrp {
316 fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
319 pinctrl_uart3: uart3grp {
321 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
322 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
323 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
324 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
328 pinctrl_uart4: uart4grp {
330 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
331 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
335 pinctrl_usbh1: usbh1grp {
337 MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
341 pinctrl_usbotg: usbotggrp {
343 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
344 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
345 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
349 pinctrl_usdhc2: usdhc2grp {
351 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
352 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
353 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
354 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
355 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
356 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
360 pinctrl_usdhc3: usdhc3grp {
362 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
363 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
364 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
365 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
366 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
367 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
371 pinctrl_usdhc3_cdwp: usdhc3cdwp {
373 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
374 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
378 pinctrl_audmux: audmuxgrp {
380 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
381 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
382 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
383 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_pcie>;
392 reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
397 vin-supply = <&vddcore_reg>;
401 vin-supply = <&vddsoc_reg>;
405 vin-supply = <&vddsoc_reg>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_uart3>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_uart4>;
421 vbus-supply = <®_usb_h1_vbus>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_usbh1>;
428 vbus-supply = <®_usb_otg_vbus>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pinctrl_usbotg>;
431 disable-over-current;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_usdhc2>;
438 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
439 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_usdhc3
446 &pinctrl_usdhc3_cdwp>;
447 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
448 wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;