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Merge tag 'v5.0-rc5' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6qdl-sabreauto.dtsi
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2012 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8
9 / {
10 chosen {
11 stdout-path = &uart4;
12 };
13
14 memory@10000000 {
15 device_type = "memory";
16 reg = <0x10000000 0x80000000>;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_gpio_leds>;
23
24 user {
25 label = "debug";
26 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
27 };
28 };
29
30 gpio-keys {
31 compatible = "gpio-keys";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_gpio_keys>;
34
35 home {
36 label = "Home";
37 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
38 linux,code = <KEY_HOME>;
39 wakeup-source;
40 };
41
42 back {
43 label = "Back";
44 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
45 linux,code = <KEY_BACK>;
46 wakeup-source;
47 };
48
49 program {
50 label = "Program";
51 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
52 linux,code = <KEY_PROGRAM>;
53 wakeup-source;
54 };
55
56 volume-up {
57 label = "Volume Up";
58 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
59 linux,code = <KEY_VOLUMEUP>;
60 wakeup-source;
61 };
62
63 volume-down {
64 label = "Volume Down";
65 gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
66 linux,code = <KEY_VOLUMEDOWN>;
67 wakeup-source;
68 };
69 };
70
71 clocks {
72 codec_osc: anaclk2 {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <24576000>;
76 };
77 };
78
79 reg_audio: regulator-audio {
80 compatible = "regulator-fixed";
81 regulator-name = "cs42888_supply";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 regulator-always-on;
85 };
86
87 reg_usb_h1_vbus: regulator-usb-h1-vbus {
88 compatible = "regulator-fixed";
89 regulator-name = "usb_h1_vbus";
90 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>;
92 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
93 enable-active-high;
94 };
95
96 reg_usb_otg_vbus: regulator-usb-otg-vbus {
97 compatible = "regulator-fixed";
98 regulator-name = "usb_otg_vbus";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
101 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
102 enable-active-high;
103 };
104
105 reg_can_en: regulator-can-en {
106 compatible = "regulator-fixed";
107 regulator-name = "can-en";
108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <3300000>;
110 gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
111 enable-active-high;
112 };
113
114 reg_can_stby: regulator-can-stby {
115 compatible = "regulator-fixed";
116 regulator-name = "can-stby";
117 regulator-min-microvolt = <3300000>;
118 regulator-max-microvolt = <3300000>;
119 gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
120 enable-active-high;
121 vin-supply = <&reg_can_en>;
122 };
123
124 sound-cs42888 {
125 compatible = "fsl,imx6-sabreauto-cs42888",
126 "fsl,imx-audio-cs42888";
127 model = "imx-cs42888";
128 audio-cpu = <&esai>;
129 audio-asrc = <&asrc>;
130 audio-codec = <&codec>;
131 audio-routing =
132 "Line Out Jack", "AOUT1L",
133 "Line Out Jack", "AOUT1R",
134 "Line Out Jack", "AOUT2L",
135 "Line Out Jack", "AOUT2R",
136 "Line Out Jack", "AOUT3L",
137 "Line Out Jack", "AOUT3R",
138 "Line Out Jack", "AOUT4L",
139 "Line Out Jack", "AOUT4R",
140 "AIN1L", "Line In Jack",
141 "AIN1R", "Line In Jack",
142 "AIN2L", "Line In Jack",
143 "AIN2R", "Line In Jack";
144 };
145
146 sound-spdif {
147 compatible = "fsl,imx-audio-spdif",
148 "fsl,imx-sabreauto-spdif";
149 model = "imx-spdif";
150 spdif-controller = <&spdif>;
151 spdif-in;
152 };
153
154 backlight {
155 compatible = "pwm-backlight";
156 pwms = <&pwm3 0 5000000>;
157 brightness-levels = <0 4 8 16 32 64 128 255>;
158 default-brightness-level = <7>;
159 status = "okay";
160 };
161
162 i2cmux {
163 compatible = "i2c-mux-gpio";
164 #address-cells = <1>;
165 #size-cells = <0>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c3mux>;
168 mux-gpios = <&gpio5 4 0>;
169 i2c-parent = <&i2c3>;
170 idle-state = <0>;
171
172 i2c@1 {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 reg = <1>;
176
177 adv7180: camera@21 {
178 compatible = "adi,adv7180";
179 reg = <0x21>;
180 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
181 interrupt-parent = <&gpio1>;
182 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
183
184 port {
185 adv7180_to_ipu1_csi0_mux: endpoint {
186 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
187 bus-width = <8>;
188 };
189 };
190 };
191
192 max7310_a: gpio@30 {
193 compatible = "maxim,max7310";
194 reg = <0x30>;
195 gpio-controller;
196 #gpio-cells = <2>;
197 };
198
199 max7310_b: gpio@32 {
200 compatible = "maxim,max7310";
201 reg = <0x32>;
202 gpio-controller;
203 #gpio-cells = <2>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_max7310>;
206 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
207 };
208
209 max7310_c: gpio@34 {
210 compatible = "maxim,max7310";
211 reg = <0x34>;
212 gpio-controller;
213 #gpio-cells = <2>;
214 };
215
216 light-sensor@44 {
217 compatible = "isil,isl29023";
218 reg = <0x44>;
219 interrupt-parent = <&gpio5>;
220 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
221 };
222
223 magnetometer@e {
224 compatible = "fsl,mag3110";
225 reg = <0x0e>;
226 interrupt-parent = <&gpio2>;
227 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
228 };
229
230 accelerometer@1c {
231 compatible = "fsl,mma8451";
232 reg = <0x1c>;
233 interrupt-parent = <&gpio6>;
234 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
235 };
236 };
237 };
238 };
239
240 &ipu1_csi0_from_ipu1_csi0_mux {
241 bus-width = <8>;
242 };
243
244 &ipu1_csi0_mux_from_parallel_sensor {
245 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
246 bus-width = <8>;
247 };
248
249 &ipu1_csi0 {
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_ipu1_csi0>;
252 };
253
254 &clks {
255 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
256 <&clks IMX6QDL_PLL4_BYPASS>,
257 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
258 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
259 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
260 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
261 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
262 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
263 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
264 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
265 };
266
267 &ecspi1 {
268 cs-gpios = <&gpio3 19 0>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
271 status = "disabled"; /* pin conflict with WEIM NOR */
272
273 flash: m25p80@0 {
274 #address-cells = <1>;
275 #size-cells = <1>;
276 compatible = "st,m25p32", "jedec,spi-nor";
277 spi-max-frequency = <20000000>;
278 reg = <0>;
279 };
280 };
281
282 &esai {
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_esai>;
285 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
286 <&clks IMX6QDL_CLK_ESAI_EXTAL>;
287 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
288 assigned-clock-rates = <0>, <24576000>;
289 status = "okay";
290 };
291
292 &fec {
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_enet>;
295 phy-mode = "rgmii";
296 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
297 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
298 fsl,err006687-workaround-present;
299 status = "okay";
300 };
301
302 &can1 {
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_flexcan1>;
305 xceiver-supply = <&reg_can_stby>;
306 status = "disabled"; /* pin conflict with fec */
307 };
308
309 &can2 {
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_flexcan2>;
312 xceiver-supply = <&reg_can_stby>;
313 status = "okay";
314 };
315
316 &gpmi {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_gpmi_nand>;
319 status = "okay";
320 };
321
322 &hdmi {
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_hdmi_cec>;
325 ddc-i2c-bus = <&i2c2>;
326 status = "okay";
327 };
328
329 &i2c2 {
330 clock-frequency = <100000>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_i2c2>;
333 status = "okay";
334
335 pmic: pfuze100@8 {
336 compatible = "fsl,pfuze100";
337 reg = <0x08>;
338
339 regulators {
340 sw1a_reg: sw1ab {
341 regulator-min-microvolt = <300000>;
342 regulator-max-microvolt = <1875000>;
343 regulator-boot-on;
344 regulator-always-on;
345 regulator-ramp-delay = <6250>;
346 };
347
348 sw1c_reg: sw1c {
349 regulator-min-microvolt = <300000>;
350 regulator-max-microvolt = <1875000>;
351 regulator-boot-on;
352 regulator-always-on;
353 regulator-ramp-delay = <6250>;
354 };
355
356 sw2_reg: sw2 {
357 regulator-min-microvolt = <800000>;
358 regulator-max-microvolt = <3300000>;
359 regulator-boot-on;
360 regulator-always-on;
361 };
362
363 sw3a_reg: sw3a {
364 regulator-min-microvolt = <400000>;
365 regulator-max-microvolt = <1975000>;
366 regulator-boot-on;
367 regulator-always-on;
368 };
369
370 sw3b_reg: sw3b {
371 regulator-min-microvolt = <400000>;
372 regulator-max-microvolt = <1975000>;
373 regulator-boot-on;
374 regulator-always-on;
375 };
376
377 sw4_reg: sw4 {
378 regulator-min-microvolt = <800000>;
379 regulator-max-microvolt = <3300000>;
380 };
381
382 swbst_reg: swbst {
383 regulator-min-microvolt = <5000000>;
384 regulator-max-microvolt = <5150000>;
385 };
386
387 snvs_reg: vsnvs {
388 regulator-min-microvolt = <1000000>;
389 regulator-max-microvolt = <3000000>;
390 regulator-boot-on;
391 regulator-always-on;
392 };
393
394 vref_reg: vrefddr {
395 regulator-boot-on;
396 regulator-always-on;
397 };
398
399 vgen1_reg: vgen1 {
400 regulator-min-microvolt = <800000>;
401 regulator-max-microvolt = <1550000>;
402 };
403
404 vgen2_reg: vgen2 {
405 regulator-min-microvolt = <800000>;
406 regulator-max-microvolt = <1550000>;
407 };
408
409 vgen3_reg: vgen3 {
410 regulator-min-microvolt = <1800000>;
411 regulator-max-microvolt = <3300000>;
412 };
413
414 vgen4_reg: vgen4 {
415 regulator-min-microvolt = <1800000>;
416 regulator-max-microvolt = <3300000>;
417 regulator-always-on;
418 };
419
420 vgen5_reg: vgen5 {
421 regulator-min-microvolt = <1800000>;
422 regulator-max-microvolt = <3300000>;
423 regulator-always-on;
424 };
425
426 vgen6_reg: vgen6 {
427 regulator-min-microvolt = <1800000>;
428 regulator-max-microvolt = <3300000>;
429 regulator-always-on;
430 };
431 };
432 };
433
434 codec: cs42888@48 {
435 compatible = "cirrus,cs42888";
436 reg = <0x48>;
437 clocks = <&codec_osc>;
438 clock-names = "mclk";
439 VA-supply = <&reg_audio>;
440 VD-supply = <&reg_audio>;
441 VLS-supply = <&reg_audio>;
442 VLC-supply = <&reg_audio>;
443 };
444
445 touchscreen@4 {
446 compatible = "eeti,egalax_ts";
447 reg = <0x04>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_egalax_int>;
450 interrupt-parent = <&gpio2>;
451 interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
452 wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
453 };
454 };
455
456 &i2c3 {
457 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_i2c3>;
459 status = "okay";
460 };
461
462 &iomuxc {
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_hog>;
465
466 imx6qdl-sabreauto {
467 pinctrl_hog: hoggrp {
468 fsl,pins = <
469 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
470 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
471 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
472 >;
473 };
474
475 pinctrl_ecspi1: ecspi1grp {
476 fsl,pins = <
477 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
478 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
479 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
480 >;
481 };
482
483 pinctrl_ecspi1_cs: ecspi1cs {
484 fsl,pins = <
485 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
486 >;
487 };
488
489 pinctrl_egalax_int: egalax-intgrp {
490 fsl,pins = <
491 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
492 >;
493 };
494
495 pinctrl_enet: enetgrp {
496 fsl,pins = <
497 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
498 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
499 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
500 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
501 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
502 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
503 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
504 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
505 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
506 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
507 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
508 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
509 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
510 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
511 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
512 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
513 >;
514 };
515
516 pinctrl_esai: esaigrp {
517 fsl,pins = <
518 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
519 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
520 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
521 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
522 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
523 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
524 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
525 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
526 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
527 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
528 >;
529 };
530
531 pinctrl_flexcan1: flexcan1grp {
532 fsl,pins = <
533 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059
534 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059
535 >;
536 };
537
538 pinctrl_flexcan2: flexcan2grp {
539 fsl,pins = <
540 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059
541 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059
542 >;
543 };
544
545 pinctrl_gpio_keys: gpiokeysgrp {
546 fsl,pins = <
547 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
548 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
549 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
550 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
551 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
552 >;
553 };
554
555 pinctrl_gpio_leds: gpioledsgrp {
556 fsl,pins = <
557 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
558 >;
559 };
560
561 pinctrl_gpmi_nand: gpminandgrp {
562 fsl,pins = <
563 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
564 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
565 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
566 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
567 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
568 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
569 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
570 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
571 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
572 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
573 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
574 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
575 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
576 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
577 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
578 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
579 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
580 >;
581 };
582
583 pinctrl_hdmi_cec: hdmicecgrp {
584 fsl,pins = <
585 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
586 >;
587 };
588
589 pinctrl_i2c2: i2c2grp {
590 fsl,pins = <
591 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
592 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
593 >;
594 };
595
596 pinctrl_i2c3: i2c3grp {
597 fsl,pins = <
598 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
599 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
600 >;
601 };
602
603 pinctrl_i2c3mux: i2c3muxgrp {
604 fsl,pins = <
605 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
606 >;
607 };
608
609 pinctrl_ipu1_csi0: ipu1csi0grp {
610 fsl,pins = <
611 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
612 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
613 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
614 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
615 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
616 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
617 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
618 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
619 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
620 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
621 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
622 >;
623 };
624
625 pinctrl_max7310: max7310grp {
626 fsl,pins = <
627 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
628 >;
629 };
630
631 pinctrl_pwm3: pwm1grp {
632 fsl,pins = <
633 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
634 >;
635 };
636
637 pinctrl_gpt_input_capture0: gptinputcapture0grp {
638 fsl,pins = <
639 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
640 >;
641 };
642
643 pinctrl_gpt_input_capture1: gptinputcapture1grp {
644 fsl,pins = <
645 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
646 >;
647 };
648
649 pinctrl_spdif: spdifgrp {
650 fsl,pins = <
651 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
652 >;
653 };
654
655 pinctrl_uart4: uart4grp {
656 fsl,pins = <
657 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
658 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
659 >;
660 };
661
662 pinctrl_usbotg: usbotggrp {
663 fsl,pins = <
664 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
665 >;
666 };
667
668 pinctrl_usdhc3: usdhc3grp {
669 fsl,pins = <
670 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
671 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
672 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
673 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
674 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
675 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
676 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
677 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
678 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
679 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
680 >;
681 };
682
683 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
684 fsl,pins = <
685 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
686 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
687 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
688 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
689 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
690 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
691 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
692 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
693 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
694 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
695 >;
696 };
697
698 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
699 fsl,pins = <
700 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
701 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
702 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
703 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
704 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
705 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
706 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
707 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
708 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
709 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
710 >;
711 };
712
713 pinctrl_weim_cs0: weimcs0grp {
714 fsl,pins = <
715 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
716 >;
717 };
718
719 pinctrl_weim_nor: weimnorgrp {
720 fsl,pins = <
721 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
722 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
723 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
724 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
725 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
726 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
727 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
728 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
729 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
730 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
731 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
732 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
733 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
734 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
735 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
736 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
737 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
738 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
739 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
740 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
741 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
742 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
743 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
744 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
745 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
746 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
747 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
748 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
749 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
750 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
751 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
752 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
753 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
754 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
755 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
756 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
757 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
758 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
759 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
760 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
761 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
762 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
763 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
764 >;
765 };
766 };
767 };
768
769 &ldb {
770 status = "okay";
771
772 lvds-channel@0 {
773 fsl,data-mapping = "spwg";
774 fsl,data-width = <18>;
775 status = "okay";
776
777 display-timings {
778 native-mode = <&timing0>;
779 timing0: hsd100pxn1 {
780 clock-frequency = <65000000>;
781 hactive = <1024>;
782 vactive = <768>;
783 hback-porch = <220>;
784 hfront-porch = <40>;
785 vback-porch = <21>;
786 vfront-porch = <7>;
787 hsync-len = <60>;
788 vsync-len = <10>;
789 };
790 };
791 };
792 };
793
794 &pwm3 {
795 pinctrl-names = "default";
796 pinctrl-0 = <&pinctrl_pwm3>;
797 status = "okay";
798 };
799
800 &pcie {
801 status = "okay";
802 };
803
804 &spdif {
805 pinctrl-names = "default";
806 pinctrl-0 = <&pinctrl_spdif>;
807 status = "okay";
808 };
809
810 &uart4 {
811 pinctrl-names = "default";
812 pinctrl-0 = <&pinctrl_uart4>;
813 status = "okay";
814 };
815
816 &usbh1 {
817 vbus-supply = <&reg_usb_h1_vbus>;
818 status = "okay";
819 };
820
821 &usbotg {
822 vbus-supply = <&reg_usb_otg_vbus>;
823 pinctrl-names = "default";
824 pinctrl-0 = <&pinctrl_usbotg>;
825 status = "okay";
826 };
827
828 &usdhc3 {
829 pinctrl-names = "default", "state_100mhz", "state_200mhz";
830 pinctrl-0 = <&pinctrl_usdhc3>;
831 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
832 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
833 cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
834 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
835 status = "okay";
836 };
837
838 &weim {
839 pinctrl-names = "default";
840 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
841 ranges = <0 0 0x08000000 0x08000000>;
842 status = "disabled"; /* pin conflict with SPI NOR */
843
844 nor@0,0 {
845 compatible = "cfi-flash";
846 reg = <0 0 0x02000000>;
847 #address-cells = <1>;
848 #size-cells = <1>;
849 bank-width = <2>;
850 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
851 0x0000c000 0x1404a38e 0x00000000>;
852 };
853 };
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