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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/nab/target...
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / imx6qdl.dtsi
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include <dt-bindings/clock/imx6qdl-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15
16 #include "skeleton.dtsi"
17
18 / {
19 aliases {
20 ethernet0 = &fec;
21 can0 = &can1;
22 can1 = &can2;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
33 mmc0 = &usdhc1;
34 mmc1 = &usdhc2;
35 mmc2 = &usdhc3;
36 mmc3 = &usdhc4;
37 serial0 = &uart1;
38 serial1 = &uart2;
39 serial2 = &uart3;
40 serial3 = &uart4;
41 serial4 = &uart5;
42 spi0 = &ecspi1;
43 spi1 = &ecspi2;
44 spi2 = &ecspi3;
45 spi3 = &ecspi4;
46 usbphy0 = &usbphy1;
47 usbphy1 = &usbphy2;
48 };
49
50 intc: interrupt-controller@00a01000 {
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
53 interrupt-controller;
54 reg = <0x00a01000 0x1000>,
55 <0x00a00100 0x100>;
56 };
57
58 clocks {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 ckil {
63 compatible = "fsl,imx-ckil", "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <32768>;
66 };
67
68 ckih1 {
69 compatible = "fsl,imx-ckih1", "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
73
74 osc {
75 compatible = "fsl,imx-osc", "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <24000000>;
78 };
79 };
80
81 soc {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 compatible = "simple-bus";
85 interrupt-parent = <&intc>;
86 ranges;
87
88 dma_apbh: dma-apbh@00110000 {
89 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
90 reg = <0x00110000 0x2000>;
91 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
92 <0 13 IRQ_TYPE_LEVEL_HIGH>,
93 <0 13 IRQ_TYPE_LEVEL_HIGH>,
94 <0 13 IRQ_TYPE_LEVEL_HIGH>;
95 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
96 #dma-cells = <1>;
97 dma-channels = <4>;
98 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
99 };
100
101 gpmi: gpmi-nand@00112000 {
102 compatible = "fsl,imx6q-gpmi-nand";
103 #address-cells = <1>;
104 #size-cells = <1>;
105 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
106 reg-names = "gpmi-nand", "bch";
107 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-names = "bch";
109 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
110 <&clks IMX6QDL_CLK_GPMI_APB>,
111 <&clks IMX6QDL_CLK_GPMI_BCH>,
112 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
113 <&clks IMX6QDL_CLK_PER1_BCH>;
114 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
115 "gpmi_bch_apb", "per1_bch";
116 dmas = <&dma_apbh 0>;
117 dma-names = "rx-tx";
118 status = "disabled";
119 };
120
121 timer@00a00600 {
122 compatible = "arm,cortex-a9-twd-timer";
123 reg = <0x00a00600 0x20>;
124 interrupts = <1 13 0xf01>;
125 clocks = <&clks IMX6QDL_CLK_TWD>;
126 };
127
128 L2: l2-cache@00a02000 {
129 compatible = "arm,pl310-cache";
130 reg = <0x00a02000 0x1000>;
131 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
132 cache-unified;
133 cache-level = <2>;
134 arm,tag-latency = <4 2 3>;
135 arm,data-latency = <4 2 3>;
136 };
137
138 pcie: pcie@0x01000000 {
139 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
140 reg = <0x01ffc000 0x04000>,
141 <0x01f00000 0x80000>;
142 reg-names = "dbi", "config";
143 #address-cells = <3>;
144 #size-cells = <2>;
145 device_type = "pci";
146 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
147 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
148 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
149 num-lanes = <1>;
150 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-names = "msi";
152 #interrupt-cells = <1>;
153 interrupt-map-mask = <0 0 0 0x7>;
154 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
155 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
156 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
157 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
159 <&clks IMX6QDL_CLK_LVDS1_GATE>,
160 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
161 clock-names = "pcie", "pcie_bus", "pcie_phy";
162 status = "disabled";
163 };
164
165 pmu {
166 compatible = "arm,cortex-a9-pmu";
167 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
168 };
169
170 aips-bus@02000000 { /* AIPS1 */
171 compatible = "fsl,aips-bus", "simple-bus";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0x02000000 0x100000>;
175 ranges;
176
177 spba-bus@02000000 {
178 compatible = "fsl,spba-bus", "simple-bus";
179 #address-cells = <1>;
180 #size-cells = <1>;
181 reg = <0x02000000 0x40000>;
182 ranges;
183
184 spdif: spdif@02004000 {
185 compatible = "fsl,imx35-spdif";
186 reg = <0x02004000 0x4000>;
187 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
188 dmas = <&sdma 14 18 0>,
189 <&sdma 15 18 0>;
190 dma-names = "rx", "tx";
191 clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
192 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
193 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
194 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
195 <&clks IMX6QDL_CLK_DUMMY>;
196 clock-names = "core", "rxtx0",
197 "rxtx1", "rxtx2",
198 "rxtx3", "rxtx4",
199 "rxtx5", "rxtx6",
200 "rxtx7";
201 status = "disabled";
202 };
203
204 ecspi1: ecspi@02008000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
208 reg = <0x02008000 0x4000>;
209 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
211 <&clks IMX6QDL_CLK_ECSPI1>;
212 clock-names = "ipg", "per";
213 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
214 dma-names = "rx", "tx";
215 status = "disabled";
216 };
217
218 ecspi2: ecspi@0200c000 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
222 reg = <0x0200c000 0x4000>;
223 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
225 <&clks IMX6QDL_CLK_ECSPI2>;
226 clock-names = "ipg", "per";
227 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
228 dma-names = "rx", "tx";
229 status = "disabled";
230 };
231
232 ecspi3: ecspi@02010000 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
236 reg = <0x02010000 0x4000>;
237 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
239 <&clks IMX6QDL_CLK_ECSPI3>;
240 clock-names = "ipg", "per";
241 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
242 dma-names = "rx", "tx";
243 status = "disabled";
244 };
245
246 ecspi4: ecspi@02014000 {
247 #address-cells = <1>;
248 #size-cells = <0>;
249 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
250 reg = <0x02014000 0x4000>;
251 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
253 <&clks IMX6QDL_CLK_ECSPI4>;
254 clock-names = "ipg", "per";
255 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
256 dma-names = "rx", "tx";
257 status = "disabled";
258 };
259
260 uart1: serial@02020000 {
261 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
262 reg = <0x02020000 0x4000>;
263 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
265 <&clks IMX6QDL_CLK_UART_SERIAL>;
266 clock-names = "ipg", "per";
267 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
268 dma-names = "rx", "tx";
269 status = "disabled";
270 };
271
272 esai: esai@02024000 {
273 reg = <0x02024000 0x4000>;
274 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
275 };
276
277 ssi1: ssi@02028000 {
278 #sound-dai-cells = <0>;
279 compatible = "fsl,imx6q-ssi",
280 "fsl,imx51-ssi";
281 reg = <0x02028000 0x4000>;
282 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
284 <&clks IMX6QDL_CLK_SSI1>;
285 clock-names = "ipg", "baud";
286 dmas = <&sdma 37 1 0>,
287 <&sdma 38 1 0>;
288 dma-names = "rx", "tx";
289 fsl,fifo-depth = <15>;
290 status = "disabled";
291 };
292
293 ssi2: ssi@0202c000 {
294 #sound-dai-cells = <0>;
295 compatible = "fsl,imx6q-ssi",
296 "fsl,imx51-ssi";
297 reg = <0x0202c000 0x4000>;
298 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
300 <&clks IMX6QDL_CLK_SSI2>;
301 clock-names = "ipg", "baud";
302 dmas = <&sdma 41 1 0>,
303 <&sdma 42 1 0>;
304 dma-names = "rx", "tx";
305 fsl,fifo-depth = <15>;
306 status = "disabled";
307 };
308
309 ssi3: ssi@02030000 {
310 #sound-dai-cells = <0>;
311 compatible = "fsl,imx6q-ssi",
312 "fsl,imx51-ssi";
313 reg = <0x02030000 0x4000>;
314 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
316 <&clks IMX6QDL_CLK_SSI3>;
317 clock-names = "ipg", "baud";
318 dmas = <&sdma 45 1 0>,
319 <&sdma 46 1 0>;
320 dma-names = "rx", "tx";
321 fsl,fifo-depth = <15>;
322 status = "disabled";
323 };
324
325 asrc: asrc@02034000 {
326 reg = <0x02034000 0x4000>;
327 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
328 };
329
330 spba@0203c000 {
331 reg = <0x0203c000 0x4000>;
332 };
333 };
334
335 vpu: vpu@02040000 {
336 compatible = "cnm,coda960";
337 reg = <0x02040000 0x3c000>;
338 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
339 <0 3 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "bit", "jpeg";
341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
343 clock-names = "per", "ahb";
344 resets = <&src 1>;
345 iram = <&ocram>;
346 };
347
348 aipstz@0207c000 { /* AIPSTZ1 */
349 reg = <0x0207c000 0x4000>;
350 };
351
352 pwm1: pwm@02080000 {
353 #pwm-cells = <2>;
354 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
355 reg = <0x02080000 0x4000>;
356 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6QDL_CLK_IPG>,
358 <&clks IMX6QDL_CLK_PWM1>;
359 clock-names = "ipg", "per";
360 };
361
362 pwm2: pwm@02084000 {
363 #pwm-cells = <2>;
364 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
365 reg = <0x02084000 0x4000>;
366 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clks IMX6QDL_CLK_IPG>,
368 <&clks IMX6QDL_CLK_PWM2>;
369 clock-names = "ipg", "per";
370 };
371
372 pwm3: pwm@02088000 {
373 #pwm-cells = <2>;
374 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
375 reg = <0x02088000 0x4000>;
376 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6QDL_CLK_IPG>,
378 <&clks IMX6QDL_CLK_PWM3>;
379 clock-names = "ipg", "per";
380 };
381
382 pwm4: pwm@0208c000 {
383 #pwm-cells = <2>;
384 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
385 reg = <0x0208c000 0x4000>;
386 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6QDL_CLK_IPG>,
388 <&clks IMX6QDL_CLK_PWM4>;
389 clock-names = "ipg", "per";
390 };
391
392 can1: flexcan@02090000 {
393 compatible = "fsl,imx6q-flexcan";
394 reg = <0x02090000 0x4000>;
395 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
397 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
398 clock-names = "ipg", "per";
399 status = "disabled";
400 };
401
402 can2: flexcan@02094000 {
403 compatible = "fsl,imx6q-flexcan";
404 reg = <0x02094000 0x4000>;
405 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
407 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
408 clock-names = "ipg", "per";
409 status = "disabled";
410 };
411
412 gpt: gpt@02098000 {
413 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
414 reg = <0x02098000 0x4000>;
415 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
417 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
418 <&clks IMX6QDL_CLK_GPT_3M>;
419 clock-names = "ipg", "per", "osc_per";
420 };
421
422 gpio1: gpio@0209c000 {
423 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
424 reg = <0x0209c000 0x4000>;
425 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
426 <0 67 IRQ_TYPE_LEVEL_HIGH>;
427 gpio-controller;
428 #gpio-cells = <2>;
429 interrupt-controller;
430 #interrupt-cells = <2>;
431 };
432
433 gpio2: gpio@020a0000 {
434 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
435 reg = <0x020a0000 0x4000>;
436 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
437 <0 69 IRQ_TYPE_LEVEL_HIGH>;
438 gpio-controller;
439 #gpio-cells = <2>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 };
443
444 gpio3: gpio@020a4000 {
445 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
446 reg = <0x020a4000 0x4000>;
447 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
448 <0 71 IRQ_TYPE_LEVEL_HIGH>;
449 gpio-controller;
450 #gpio-cells = <2>;
451 interrupt-controller;
452 #interrupt-cells = <2>;
453 };
454
455 gpio4: gpio@020a8000 {
456 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
457 reg = <0x020a8000 0x4000>;
458 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
459 <0 73 IRQ_TYPE_LEVEL_HIGH>;
460 gpio-controller;
461 #gpio-cells = <2>;
462 interrupt-controller;
463 #interrupt-cells = <2>;
464 };
465
466 gpio5: gpio@020ac000 {
467 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
468 reg = <0x020ac000 0x4000>;
469 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
470 <0 75 IRQ_TYPE_LEVEL_HIGH>;
471 gpio-controller;
472 #gpio-cells = <2>;
473 interrupt-controller;
474 #interrupt-cells = <2>;
475 };
476
477 gpio6: gpio@020b0000 {
478 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
479 reg = <0x020b0000 0x4000>;
480 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
481 <0 77 IRQ_TYPE_LEVEL_HIGH>;
482 gpio-controller;
483 #gpio-cells = <2>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 };
487
488 gpio7: gpio@020b4000 {
489 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
490 reg = <0x020b4000 0x4000>;
491 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
492 <0 79 IRQ_TYPE_LEVEL_HIGH>;
493 gpio-controller;
494 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 };
498
499 kpp: kpp@020b8000 {
500 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
501 reg = <0x020b8000 0x4000>;
502 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX6QDL_CLK_IPG>;
504 status = "disabled";
505 };
506
507 wdog1: wdog@020bc000 {
508 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
509 reg = <0x020bc000 0x4000>;
510 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&clks IMX6QDL_CLK_DUMMY>;
512 };
513
514 wdog2: wdog@020c0000 {
515 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
516 reg = <0x020c0000 0x4000>;
517 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clks IMX6QDL_CLK_DUMMY>;
519 status = "disabled";
520 };
521
522 clks: ccm@020c4000 {
523 compatible = "fsl,imx6q-ccm";
524 reg = <0x020c4000 0x4000>;
525 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
526 <0 88 IRQ_TYPE_LEVEL_HIGH>;
527 #clock-cells = <1>;
528 };
529
530 anatop: anatop@020c8000 {
531 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
532 reg = <0x020c8000 0x1000>;
533 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
534 <0 54 IRQ_TYPE_LEVEL_HIGH>,
535 <0 127 IRQ_TYPE_LEVEL_HIGH>;
536
537 regulator-1p1@110 {
538 compatible = "fsl,anatop-regulator";
539 regulator-name = "vdd1p1";
540 regulator-min-microvolt = <800000>;
541 regulator-max-microvolt = <1375000>;
542 regulator-always-on;
543 anatop-reg-offset = <0x110>;
544 anatop-vol-bit-shift = <8>;
545 anatop-vol-bit-width = <5>;
546 anatop-min-bit-val = <4>;
547 anatop-min-voltage = <800000>;
548 anatop-max-voltage = <1375000>;
549 };
550
551 regulator-3p0@120 {
552 compatible = "fsl,anatop-regulator";
553 regulator-name = "vdd3p0";
554 regulator-min-microvolt = <2800000>;
555 regulator-max-microvolt = <3150000>;
556 regulator-always-on;
557 anatop-reg-offset = <0x120>;
558 anatop-vol-bit-shift = <8>;
559 anatop-vol-bit-width = <5>;
560 anatop-min-bit-val = <0>;
561 anatop-min-voltage = <2625000>;
562 anatop-max-voltage = <3400000>;
563 };
564
565 regulator-2p5@130 {
566 compatible = "fsl,anatop-regulator";
567 regulator-name = "vdd2p5";
568 regulator-min-microvolt = <2000000>;
569 regulator-max-microvolt = <2750000>;
570 regulator-always-on;
571 anatop-reg-offset = <0x130>;
572 anatop-vol-bit-shift = <8>;
573 anatop-vol-bit-width = <5>;
574 anatop-min-bit-val = <0>;
575 anatop-min-voltage = <2000000>;
576 anatop-max-voltage = <2750000>;
577 };
578
579 reg_arm: regulator-vddcore@140 {
580 compatible = "fsl,anatop-regulator";
581 regulator-name = "vddarm";
582 regulator-min-microvolt = <725000>;
583 regulator-max-microvolt = <1450000>;
584 regulator-always-on;
585 anatop-reg-offset = <0x140>;
586 anatop-vol-bit-shift = <0>;
587 anatop-vol-bit-width = <5>;
588 anatop-delay-reg-offset = <0x170>;
589 anatop-delay-bit-shift = <24>;
590 anatop-delay-bit-width = <2>;
591 anatop-min-bit-val = <1>;
592 anatop-min-voltage = <725000>;
593 anatop-max-voltage = <1450000>;
594 };
595
596 reg_pu: regulator-vddpu@140 {
597 compatible = "fsl,anatop-regulator";
598 regulator-name = "vddpu";
599 regulator-min-microvolt = <725000>;
600 regulator-max-microvolt = <1450000>;
601 regulator-always-on;
602 anatop-reg-offset = <0x140>;
603 anatop-vol-bit-shift = <9>;
604 anatop-vol-bit-width = <5>;
605 anatop-delay-reg-offset = <0x170>;
606 anatop-delay-bit-shift = <26>;
607 anatop-delay-bit-width = <2>;
608 anatop-min-bit-val = <1>;
609 anatop-min-voltage = <725000>;
610 anatop-max-voltage = <1450000>;
611 };
612
613 reg_soc: regulator-vddsoc@140 {
614 compatible = "fsl,anatop-regulator";
615 regulator-name = "vddsoc";
616 regulator-min-microvolt = <725000>;
617 regulator-max-microvolt = <1450000>;
618 regulator-always-on;
619 anatop-reg-offset = <0x140>;
620 anatop-vol-bit-shift = <18>;
621 anatop-vol-bit-width = <5>;
622 anatop-delay-reg-offset = <0x170>;
623 anatop-delay-bit-shift = <28>;
624 anatop-delay-bit-width = <2>;
625 anatop-min-bit-val = <1>;
626 anatop-min-voltage = <725000>;
627 anatop-max-voltage = <1450000>;
628 };
629 };
630
631 tempmon: tempmon {
632 compatible = "fsl,imx6q-tempmon";
633 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
634 fsl,tempmon = <&anatop>;
635 fsl,tempmon-data = <&ocotp>;
636 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
637 };
638
639 usbphy1: usbphy@020c9000 {
640 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
641 reg = <0x020c9000 0x1000>;
642 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
644 fsl,anatop = <&anatop>;
645 };
646
647 usbphy2: usbphy@020ca000 {
648 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
649 reg = <0x020ca000 0x1000>;
650 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
652 fsl,anatop = <&anatop>;
653 };
654
655 snvs@020cc000 {
656 compatible = "fsl,sec-v4.0-mon", "simple-bus";
657 #address-cells = <1>;
658 #size-cells = <1>;
659 ranges = <0 0x020cc000 0x4000>;
660
661 snvs-rtc-lp@34 {
662 compatible = "fsl,sec-v4.0-mon-rtc-lp";
663 reg = <0x34 0x58>;
664 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
665 <0 20 IRQ_TYPE_LEVEL_HIGH>;
666 };
667
668 snvs_poweroff: snvs-poweroff@38 {
669 compatible = "fsl,sec-v4.0-poweroff";
670 reg = <0x38 0x4>;
671 status = "disabled";
672 };
673 };
674
675 epit1: epit@020d0000 { /* EPIT1 */
676 reg = <0x020d0000 0x4000>;
677 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
678 };
679
680 epit2: epit@020d4000 { /* EPIT2 */
681 reg = <0x020d4000 0x4000>;
682 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
683 };
684
685 src: src@020d8000 {
686 compatible = "fsl,imx6q-src", "fsl,imx51-src";
687 reg = <0x020d8000 0x4000>;
688 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
689 <0 96 IRQ_TYPE_LEVEL_HIGH>;
690 #reset-cells = <1>;
691 };
692
693 gpc: gpc@020dc000 {
694 compatible = "fsl,imx6q-gpc";
695 reg = <0x020dc000 0x4000>;
696 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
697 <0 90 IRQ_TYPE_LEVEL_HIGH>;
698 };
699
700 gpr: iomuxc-gpr@020e0000 {
701 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
702 reg = <0x020e0000 0x38>;
703 };
704
705 iomuxc: iomuxc@020e0000 {
706 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
707 reg = <0x020e0000 0x4000>;
708 };
709
710 ldb: ldb@020e0008 {
711 #address-cells = <1>;
712 #size-cells = <0>;
713 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
714 gpr = <&gpr>;
715 status = "disabled";
716
717 lvds-channel@0 {
718 #address-cells = <1>;
719 #size-cells = <0>;
720 reg = <0>;
721 status = "disabled";
722
723 port@0 {
724 reg = <0>;
725
726 lvds0_mux_0: endpoint {
727 remote-endpoint = <&ipu1_di0_lvds0>;
728 };
729 };
730
731 port@1 {
732 reg = <1>;
733
734 lvds0_mux_1: endpoint {
735 remote-endpoint = <&ipu1_di1_lvds0>;
736 };
737 };
738 };
739
740 lvds-channel@1 {
741 #address-cells = <1>;
742 #size-cells = <0>;
743 reg = <1>;
744 status = "disabled";
745
746 port@0 {
747 reg = <0>;
748
749 lvds1_mux_0: endpoint {
750 remote-endpoint = <&ipu1_di0_lvds1>;
751 };
752 };
753
754 port@1 {
755 reg = <1>;
756
757 lvds1_mux_1: endpoint {
758 remote-endpoint = <&ipu1_di1_lvds1>;
759 };
760 };
761 };
762 };
763
764 hdmi: hdmi@0120000 {
765 #address-cells = <1>;
766 #size-cells = <0>;
767 reg = <0x00120000 0x9000>;
768 interrupts = <0 115 0x04>;
769 gpr = <&gpr>;
770 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
771 <&clks IMX6QDL_CLK_HDMI_ISFR>;
772 clock-names = "iahb", "isfr";
773 status = "disabled";
774
775 port@0 {
776 reg = <0>;
777
778 hdmi_mux_0: endpoint {
779 remote-endpoint = <&ipu1_di0_hdmi>;
780 };
781 };
782
783 port@1 {
784 reg = <1>;
785
786 hdmi_mux_1: endpoint {
787 remote-endpoint = <&ipu1_di1_hdmi>;
788 };
789 };
790 };
791
792 dcic1: dcic@020e4000 {
793 reg = <0x020e4000 0x4000>;
794 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
795 };
796
797 dcic2: dcic@020e8000 {
798 reg = <0x020e8000 0x4000>;
799 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
800 };
801
802 sdma: sdma@020ec000 {
803 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
804 reg = <0x020ec000 0x4000>;
805 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks IMX6QDL_CLK_SDMA>,
807 <&clks IMX6QDL_CLK_SDMA>;
808 clock-names = "ipg", "ahb";
809 #dma-cells = <3>;
810 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
811 };
812 };
813
814 aips-bus@02100000 { /* AIPS2 */
815 compatible = "fsl,aips-bus", "simple-bus";
816 #address-cells = <1>;
817 #size-cells = <1>;
818 reg = <0x02100000 0x100000>;
819 ranges;
820
821 caam@02100000 {
822 reg = <0x02100000 0x40000>;
823 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
824 <0 106 IRQ_TYPE_LEVEL_HIGH>;
825 };
826
827 aipstz@0217c000 { /* AIPSTZ2 */
828 reg = <0x0217c000 0x4000>;
829 };
830
831 usbotg: usb@02184000 {
832 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
833 reg = <0x02184000 0x200>;
834 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clks IMX6QDL_CLK_USBOH3>;
836 fsl,usbphy = <&usbphy1>;
837 fsl,usbmisc = <&usbmisc 0>;
838 status = "disabled";
839 };
840
841 usbh1: usb@02184200 {
842 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
843 reg = <0x02184200 0x200>;
844 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&clks IMX6QDL_CLK_USBOH3>;
846 fsl,usbphy = <&usbphy2>;
847 fsl,usbmisc = <&usbmisc 1>;
848 status = "disabled";
849 };
850
851 usbh2: usb@02184400 {
852 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
853 reg = <0x02184400 0x200>;
854 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clks IMX6QDL_CLK_USBOH3>;
856 fsl,usbmisc = <&usbmisc 2>;
857 status = "disabled";
858 };
859
860 usbh3: usb@02184600 {
861 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
862 reg = <0x02184600 0x200>;
863 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&clks IMX6QDL_CLK_USBOH3>;
865 fsl,usbmisc = <&usbmisc 3>;
866 status = "disabled";
867 };
868
869 usbmisc: usbmisc@02184800 {
870 #index-cells = <1>;
871 compatible = "fsl,imx6q-usbmisc";
872 reg = <0x02184800 0x200>;
873 clocks = <&clks IMX6QDL_CLK_USBOH3>;
874 };
875
876 fec: ethernet@02188000 {
877 compatible = "fsl,imx6q-fec";
878 reg = <0x02188000 0x4000>;
879 interrupts-extended =
880 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
881 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clks IMX6QDL_CLK_ENET>,
883 <&clks IMX6QDL_CLK_ENET>,
884 <&clks IMX6QDL_CLK_ENET_REF>;
885 clock-names = "ipg", "ahb", "ptp";
886 status = "disabled";
887 };
888
889 mlb@0218c000 {
890 reg = <0x0218c000 0x4000>;
891 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
892 <0 117 IRQ_TYPE_LEVEL_HIGH>,
893 <0 126 IRQ_TYPE_LEVEL_HIGH>;
894 };
895
896 usdhc1: usdhc@02190000 {
897 compatible = "fsl,imx6q-usdhc";
898 reg = <0x02190000 0x4000>;
899 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&clks IMX6QDL_CLK_USDHC1>,
901 <&clks IMX6QDL_CLK_USDHC1>,
902 <&clks IMX6QDL_CLK_USDHC1>;
903 clock-names = "ipg", "ahb", "per";
904 bus-width = <4>;
905 status = "disabled";
906 };
907
908 usdhc2: usdhc@02194000 {
909 compatible = "fsl,imx6q-usdhc";
910 reg = <0x02194000 0x4000>;
911 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&clks IMX6QDL_CLK_USDHC2>,
913 <&clks IMX6QDL_CLK_USDHC2>,
914 <&clks IMX6QDL_CLK_USDHC2>;
915 clock-names = "ipg", "ahb", "per";
916 bus-width = <4>;
917 status = "disabled";
918 };
919
920 usdhc3: usdhc@02198000 {
921 compatible = "fsl,imx6q-usdhc";
922 reg = <0x02198000 0x4000>;
923 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&clks IMX6QDL_CLK_USDHC3>,
925 <&clks IMX6QDL_CLK_USDHC3>,
926 <&clks IMX6QDL_CLK_USDHC3>;
927 clock-names = "ipg", "ahb", "per";
928 bus-width = <4>;
929 status = "disabled";
930 };
931
932 usdhc4: usdhc@0219c000 {
933 compatible = "fsl,imx6q-usdhc";
934 reg = <0x0219c000 0x4000>;
935 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6QDL_CLK_USDHC4>,
937 <&clks IMX6QDL_CLK_USDHC4>,
938 <&clks IMX6QDL_CLK_USDHC4>;
939 clock-names = "ipg", "ahb", "per";
940 bus-width = <4>;
941 status = "disabled";
942 };
943
944 i2c1: i2c@021a0000 {
945 #address-cells = <1>;
946 #size-cells = <0>;
947 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
948 reg = <0x021a0000 0x4000>;
949 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&clks IMX6QDL_CLK_I2C1>;
951 status = "disabled";
952 };
953
954 i2c2: i2c@021a4000 {
955 #address-cells = <1>;
956 #size-cells = <0>;
957 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
958 reg = <0x021a4000 0x4000>;
959 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&clks IMX6QDL_CLK_I2C2>;
961 status = "disabled";
962 };
963
964 i2c3: i2c@021a8000 {
965 #address-cells = <1>;
966 #size-cells = <0>;
967 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
968 reg = <0x021a8000 0x4000>;
969 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&clks IMX6QDL_CLK_I2C3>;
971 status = "disabled";
972 };
973
974 romcp@021ac000 {
975 reg = <0x021ac000 0x4000>;
976 };
977
978 mmdc0: mmdc@021b0000 { /* MMDC0 */
979 compatible = "fsl,imx6q-mmdc";
980 reg = <0x021b0000 0x4000>;
981 };
982
983 mmdc1: mmdc@021b4000 { /* MMDC1 */
984 reg = <0x021b4000 0x4000>;
985 };
986
987 weim: weim@021b8000 {
988 compatible = "fsl,imx6q-weim";
989 reg = <0x021b8000 0x4000>;
990 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
992 };
993
994 ocotp: ocotp@021bc000 {
995 compatible = "fsl,imx6q-ocotp", "syscon";
996 reg = <0x021bc000 0x4000>;
997 };
998
999 tzasc@021d0000 { /* TZASC1 */
1000 reg = <0x021d0000 0x4000>;
1001 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1002 };
1003
1004 tzasc@021d4000 { /* TZASC2 */
1005 reg = <0x021d4000 0x4000>;
1006 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1007 };
1008
1009 audmux: audmux@021d8000 {
1010 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1011 reg = <0x021d8000 0x4000>;
1012 status = "disabled";
1013 };
1014
1015 mipi_csi: mipi@021dc000 {
1016 reg = <0x021dc000 0x4000>;
1017 };
1018
1019 mipi_dsi: mipi@021e0000 {
1020 #address-cells = <1>;
1021 #size-cells = <0>;
1022 reg = <0x021e0000 0x4000>;
1023 status = "disabled";
1024
1025 port@0 {
1026 reg = <0>;
1027
1028 mipi_mux_0: endpoint {
1029 remote-endpoint = <&ipu1_di0_mipi>;
1030 };
1031 };
1032
1033 port@1 {
1034 reg = <1>;
1035
1036 mipi_mux_1: endpoint {
1037 remote-endpoint = <&ipu1_di1_mipi>;
1038 };
1039 };
1040 };
1041
1042 vdoa@021e4000 {
1043 reg = <0x021e4000 0x4000>;
1044 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1045 };
1046
1047 uart2: serial@021e8000 {
1048 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1049 reg = <0x021e8000 0x4000>;
1050 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1051 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1052 <&clks IMX6QDL_CLK_UART_SERIAL>;
1053 clock-names = "ipg", "per";
1054 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1055 dma-names = "rx", "tx";
1056 status = "disabled";
1057 };
1058
1059 uart3: serial@021ec000 {
1060 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1061 reg = <0x021ec000 0x4000>;
1062 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1064 <&clks IMX6QDL_CLK_UART_SERIAL>;
1065 clock-names = "ipg", "per";
1066 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1067 dma-names = "rx", "tx";
1068 status = "disabled";
1069 };
1070
1071 uart4: serial@021f0000 {
1072 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1073 reg = <0x021f0000 0x4000>;
1074 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1076 <&clks IMX6QDL_CLK_UART_SERIAL>;
1077 clock-names = "ipg", "per";
1078 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1079 dma-names = "rx", "tx";
1080 status = "disabled";
1081 };
1082
1083 uart5: serial@021f4000 {
1084 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1085 reg = <0x021f4000 0x4000>;
1086 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1087 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1088 <&clks IMX6QDL_CLK_UART_SERIAL>;
1089 clock-names = "ipg", "per";
1090 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1091 dma-names = "rx", "tx";
1092 status = "disabled";
1093 };
1094 };
1095
1096 ipu1: ipu@02400000 {
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1099 compatible = "fsl,imx6q-ipu";
1100 reg = <0x02400000 0x400000>;
1101 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1102 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&clks IMX6QDL_CLK_IPU1>,
1104 <&clks IMX6QDL_CLK_IPU1_DI0>,
1105 <&clks IMX6QDL_CLK_IPU1_DI1>;
1106 clock-names = "bus", "di0", "di1";
1107 resets = <&src 2>;
1108
1109 ipu1_csi0: port@0 {
1110 reg = <0>;
1111 };
1112
1113 ipu1_csi1: port@1 {
1114 reg = <1>;
1115 };
1116
1117 ipu1_di0: port@2 {
1118 #address-cells = <1>;
1119 #size-cells = <0>;
1120 reg = <2>;
1121
1122 ipu1_di0_disp0: endpoint@0 {
1123 };
1124
1125 ipu1_di0_hdmi: endpoint@1 {
1126 remote-endpoint = <&hdmi_mux_0>;
1127 };
1128
1129 ipu1_di0_mipi: endpoint@2 {
1130 remote-endpoint = <&mipi_mux_0>;
1131 };
1132
1133 ipu1_di0_lvds0: endpoint@3 {
1134 remote-endpoint = <&lvds0_mux_0>;
1135 };
1136
1137 ipu1_di0_lvds1: endpoint@4 {
1138 remote-endpoint = <&lvds1_mux_0>;
1139 };
1140 };
1141
1142 ipu1_di1: port@3 {
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 reg = <3>;
1146
1147 ipu1_di0_disp1: endpoint@0 {
1148 };
1149
1150 ipu1_di1_hdmi: endpoint@1 {
1151 remote-endpoint = <&hdmi_mux_1>;
1152 };
1153
1154 ipu1_di1_mipi: endpoint@2 {
1155 remote-endpoint = <&mipi_mux_1>;
1156 };
1157
1158 ipu1_di1_lvds0: endpoint@3 {
1159 remote-endpoint = <&lvds0_mux_1>;
1160 };
1161
1162 ipu1_di1_lvds1: endpoint@4 {
1163 remote-endpoint = <&lvds1_mux_1>;
1164 };
1165 };
1166 };
1167 };
1168 };
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