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Merge branches 'iommu/fixes', 'arm/exynos', 'arm/renesas', 'arm/smmu', 'arm/mediatek...
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / imx6qdl.dtsi
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include <dt-bindings/clock/imx6qdl-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &fec;
22 can0 = &can1;
23 can1 = &can2;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 gpio5 = &gpio6;
30 gpio6 = &gpio7;
31 i2c0 = &i2c1;
32 i2c1 = &i2c2;
33 i2c2 = &i2c3;
34 ipu0 = &ipu1;
35 mmc0 = &usdhc1;
36 mmc1 = &usdhc2;
37 mmc2 = &usdhc3;
38 mmc3 = &usdhc4;
39 serial0 = &uart1;
40 serial1 = &uart2;
41 serial2 = &uart3;
42 serial3 = &uart4;
43 serial4 = &uart5;
44 spi0 = &ecspi1;
45 spi1 = &ecspi2;
46 spi2 = &ecspi3;
47 spi3 = &ecspi4;
48 usbphy0 = &usbphy1;
49 usbphy1 = &usbphy2;
50 };
51
52 clocks {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 ckil {
57 compatible = "fsl,imx-ckil", "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <32768>;
60 };
61
62 ckih1 {
63 compatible = "fsl,imx-ckih1", "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
67
68 osc {
69 compatible = "fsl,imx-osc", "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <24000000>;
72 };
73 };
74
75 soc {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "simple-bus";
79 interrupt-parent = <&gpc>;
80 ranges;
81
82 dma_apbh: dma-apbh@00110000 {
83 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
84 reg = <0x00110000 0x2000>;
85 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
86 <0 13 IRQ_TYPE_LEVEL_HIGH>,
87 <0 13 IRQ_TYPE_LEVEL_HIGH>,
88 <0 13 IRQ_TYPE_LEVEL_HIGH>;
89 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
90 #dma-cells = <1>;
91 dma-channels = <4>;
92 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
93 };
94
95 gpmi: gpmi-nand@00112000 {
96 compatible = "fsl,imx6q-gpmi-nand";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
100 reg-names = "gpmi-nand", "bch";
101 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-names = "bch";
103 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
104 <&clks IMX6QDL_CLK_GPMI_APB>,
105 <&clks IMX6QDL_CLK_GPMI_BCH>,
106 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
107 <&clks IMX6QDL_CLK_PER1_BCH>;
108 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
109 "gpmi_bch_apb", "per1_bch";
110 dmas = <&dma_apbh 0>;
111 dma-names = "rx-tx";
112 status = "disabled";
113 };
114
115 hdmi: hdmi@0120000 {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 reg = <0x00120000 0x9000>;
119 interrupts = <0 115 0x04>;
120 gpr = <&gpr>;
121 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
122 <&clks IMX6QDL_CLK_HDMI_ISFR>;
123 clock-names = "iahb", "isfr";
124 status = "disabled";
125
126 port@0 {
127 reg = <0>;
128
129 hdmi_mux_0: endpoint {
130 remote-endpoint = <&ipu1_di0_hdmi>;
131 };
132 };
133
134 port@1 {
135 reg = <1>;
136
137 hdmi_mux_1: endpoint {
138 remote-endpoint = <&ipu1_di1_hdmi>;
139 };
140 };
141 };
142
143 gpu_3d: gpu@00130000 {
144 compatible = "vivante,gc";
145 reg = <0x00130000 0x4000>;
146 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
148 <&clks IMX6QDL_CLK_GPU3D_CORE>,
149 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
150 clock-names = "bus", "core", "shader";
151 power-domains = <&gpc 1>;
152 };
153
154 gpu_2d: gpu@00134000 {
155 compatible = "vivante,gc";
156 reg = <0x00134000 0x4000>;
157 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
159 <&clks IMX6QDL_CLK_GPU2D_CORE>;
160 clock-names = "bus", "core";
161 power-domains = <&gpc 1>;
162 };
163
164 timer@00a00600 {
165 compatible = "arm,cortex-a9-twd-timer";
166 reg = <0x00a00600 0x20>;
167 interrupts = <1 13 0xf01>;
168 interrupt-parent = <&intc>;
169 clocks = <&clks IMX6QDL_CLK_TWD>;
170 };
171
172 intc: interrupt-controller@00a01000 {
173 compatible = "arm,cortex-a9-gic";
174 #interrupt-cells = <3>;
175 interrupt-controller;
176 reg = <0x00a01000 0x1000>,
177 <0x00a00100 0x100>;
178 interrupt-parent = <&intc>;
179 };
180
181 L2: l2-cache@00a02000 {
182 compatible = "arm,pl310-cache";
183 reg = <0x00a02000 0x1000>;
184 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
185 cache-unified;
186 cache-level = <2>;
187 arm,tag-latency = <4 2 3>;
188 arm,data-latency = <4 2 3>;
189 arm,shared-override;
190 };
191
192 pcie: pcie@0x01000000 {
193 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
194 reg = <0x01ffc000 0x04000>,
195 <0x01f00000 0x80000>;
196 reg-names = "dbi", "config";
197 #address-cells = <3>;
198 #size-cells = <2>;
199 device_type = "pci";
200 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
201 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
202 num-lanes = <1>;
203 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
204 interrupt-names = "msi";
205 #interrupt-cells = <1>;
206 interrupt-map-mask = <0 0 0 0x7>;
207 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
208 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
209 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
210 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
212 <&clks IMX6QDL_CLK_LVDS1_GATE>,
213 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
214 clock-names = "pcie", "pcie_bus", "pcie_phy";
215 status = "disabled";
216 };
217
218 pmu {
219 compatible = "arm,cortex-a9-pmu";
220 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
221 };
222
223 aips-bus@02000000 { /* AIPS1 */
224 compatible = "fsl,aips-bus", "simple-bus";
225 #address-cells = <1>;
226 #size-cells = <1>;
227 reg = <0x02000000 0x100000>;
228 ranges;
229
230 spba-bus@02000000 {
231 compatible = "fsl,spba-bus", "simple-bus";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 reg = <0x02000000 0x40000>;
235 ranges;
236
237 spdif: spdif@02004000 {
238 compatible = "fsl,imx35-spdif";
239 reg = <0x02004000 0x4000>;
240 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
241 dmas = <&sdma 14 18 0>,
242 <&sdma 15 18 0>;
243 dma-names = "rx", "tx";
244 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
245 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
246 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
247 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
248 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
249 clock-names = "core", "rxtx0",
250 "rxtx1", "rxtx2",
251 "rxtx3", "rxtx4",
252 "rxtx5", "rxtx6",
253 "rxtx7", "spba";
254 status = "disabled";
255 };
256
257 ecspi1: ecspi@02008000 {
258 #address-cells = <1>;
259 #size-cells = <0>;
260 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
261 reg = <0x02008000 0x4000>;
262 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
264 <&clks IMX6QDL_CLK_ECSPI1>;
265 clock-names = "ipg", "per";
266 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
267 dma-names = "rx", "tx";
268 status = "disabled";
269 };
270
271 ecspi2: ecspi@0200c000 {
272 #address-cells = <1>;
273 #size-cells = <0>;
274 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
275 reg = <0x0200c000 0x4000>;
276 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
278 <&clks IMX6QDL_CLK_ECSPI2>;
279 clock-names = "ipg", "per";
280 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
281 dma-names = "rx", "tx";
282 status = "disabled";
283 };
284
285 ecspi3: ecspi@02010000 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
289 reg = <0x02010000 0x4000>;
290 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
292 <&clks IMX6QDL_CLK_ECSPI3>;
293 clock-names = "ipg", "per";
294 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
295 dma-names = "rx", "tx";
296 status = "disabled";
297 };
298
299 ecspi4: ecspi@02014000 {
300 #address-cells = <1>;
301 #size-cells = <0>;
302 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
303 reg = <0x02014000 0x4000>;
304 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
306 <&clks IMX6QDL_CLK_ECSPI4>;
307 clock-names = "ipg", "per";
308 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
309 dma-names = "rx", "tx";
310 status = "disabled";
311 };
312
313 uart1: serial@02020000 {
314 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
315 reg = <0x02020000 0x4000>;
316 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
318 <&clks IMX6QDL_CLK_UART_SERIAL>;
319 clock-names = "ipg", "per";
320 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
321 dma-names = "rx", "tx";
322 status = "disabled";
323 };
324
325 esai: esai@02024000 {
326 #sound-dai-cells = <0>;
327 compatible = "fsl,imx35-esai";
328 reg = <0x02024000 0x4000>;
329 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
331 <&clks IMX6QDL_CLK_ESAI_MEM>,
332 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
333 <&clks IMX6QDL_CLK_ESAI_IPG>,
334 <&clks IMX6QDL_CLK_SPBA>;
335 clock-names = "core", "mem", "extal", "fsys", "spba";
336 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
337 dma-names = "rx", "tx";
338 status = "disabled";
339 };
340
341 ssi1: ssi@02028000 {
342 #sound-dai-cells = <0>;
343 compatible = "fsl,imx6q-ssi",
344 "fsl,imx51-ssi";
345 reg = <0x02028000 0x4000>;
346 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
348 <&clks IMX6QDL_CLK_SSI1>;
349 clock-names = "ipg", "baud";
350 dmas = <&sdma 37 1 0>,
351 <&sdma 38 1 0>;
352 dma-names = "rx", "tx";
353 fsl,fifo-depth = <15>;
354 status = "disabled";
355 };
356
357 ssi2: ssi@0202c000 {
358 #sound-dai-cells = <0>;
359 compatible = "fsl,imx6q-ssi",
360 "fsl,imx51-ssi";
361 reg = <0x0202c000 0x4000>;
362 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
364 <&clks IMX6QDL_CLK_SSI2>;
365 clock-names = "ipg", "baud";
366 dmas = <&sdma 41 1 0>,
367 <&sdma 42 1 0>;
368 dma-names = "rx", "tx";
369 fsl,fifo-depth = <15>;
370 status = "disabled";
371 };
372
373 ssi3: ssi@02030000 {
374 #sound-dai-cells = <0>;
375 compatible = "fsl,imx6q-ssi",
376 "fsl,imx51-ssi";
377 reg = <0x02030000 0x4000>;
378 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
380 <&clks IMX6QDL_CLK_SSI3>;
381 clock-names = "ipg", "baud";
382 dmas = <&sdma 45 1 0>,
383 <&sdma 46 1 0>;
384 dma-names = "rx", "tx";
385 fsl,fifo-depth = <15>;
386 status = "disabled";
387 };
388
389 asrc: asrc@02034000 {
390 compatible = "fsl,imx53-asrc";
391 reg = <0x02034000 0x4000>;
392 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
394 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
395 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
396 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
397 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
398 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
399 <&clks IMX6QDL_CLK_SPBA>;
400 clock-names = "mem", "ipg", "asrck_0",
401 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
402 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
403 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
404 "asrck_d", "asrck_e", "asrck_f", "spba";
405 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
406 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
407 dma-names = "rxa", "rxb", "rxc",
408 "txa", "txb", "txc";
409 fsl,asrc-rate = <48000>;
410 fsl,asrc-width = <16>;
411 status = "okay";
412 };
413
414 spba@0203c000 {
415 reg = <0x0203c000 0x4000>;
416 };
417 };
418
419 vpu: vpu@02040000 {
420 compatible = "cnm,coda960";
421 reg = <0x02040000 0x3c000>;
422 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
423 <0 3 IRQ_TYPE_LEVEL_HIGH>;
424 interrupt-names = "bit", "jpeg";
425 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
426 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
427 clock-names = "per", "ahb";
428 power-domains = <&gpc 1>;
429 resets = <&src 1>;
430 iram = <&ocram>;
431 };
432
433 aipstz@0207c000 { /* AIPSTZ1 */
434 reg = <0x0207c000 0x4000>;
435 };
436
437 pwm1: pwm@02080000 {
438 #pwm-cells = <2>;
439 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
440 reg = <0x02080000 0x4000>;
441 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&clks IMX6QDL_CLK_IPG>,
443 <&clks IMX6QDL_CLK_PWM1>;
444 clock-names = "ipg", "per";
445 status = "disabled";
446 };
447
448 pwm2: pwm@02084000 {
449 #pwm-cells = <2>;
450 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
451 reg = <0x02084000 0x4000>;
452 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clks IMX6QDL_CLK_IPG>,
454 <&clks IMX6QDL_CLK_PWM2>;
455 clock-names = "ipg", "per";
456 status = "disabled";
457 };
458
459 pwm3: pwm@02088000 {
460 #pwm-cells = <2>;
461 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
462 reg = <0x02088000 0x4000>;
463 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clks IMX6QDL_CLK_IPG>,
465 <&clks IMX6QDL_CLK_PWM3>;
466 clock-names = "ipg", "per";
467 status = "disabled";
468 };
469
470 pwm4: pwm@0208c000 {
471 #pwm-cells = <2>;
472 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
473 reg = <0x0208c000 0x4000>;
474 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clks IMX6QDL_CLK_IPG>,
476 <&clks IMX6QDL_CLK_PWM4>;
477 clock-names = "ipg", "per";
478 status = "disabled";
479 };
480
481 can1: flexcan@02090000 {
482 compatible = "fsl,imx6q-flexcan";
483 reg = <0x02090000 0x4000>;
484 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
486 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
487 clock-names = "ipg", "per";
488 status = "disabled";
489 };
490
491 can2: flexcan@02094000 {
492 compatible = "fsl,imx6q-flexcan";
493 reg = <0x02094000 0x4000>;
494 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
496 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
497 clock-names = "ipg", "per";
498 status = "disabled";
499 };
500
501 gpt: gpt@02098000 {
502 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
503 reg = <0x02098000 0x4000>;
504 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
506 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
507 <&clks IMX6QDL_CLK_GPT_3M>;
508 clock-names = "ipg", "per", "osc_per";
509 };
510
511 gpio1: gpio@0209c000 {
512 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
513 reg = <0x0209c000 0x4000>;
514 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
515 <0 67 IRQ_TYPE_LEVEL_HIGH>;
516 gpio-controller;
517 #gpio-cells = <2>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
520 };
521
522 gpio2: gpio@020a0000 {
523 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
524 reg = <0x020a0000 0x4000>;
525 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
526 <0 69 IRQ_TYPE_LEVEL_HIGH>;
527 gpio-controller;
528 #gpio-cells = <2>;
529 interrupt-controller;
530 #interrupt-cells = <2>;
531 };
532
533 gpio3: gpio@020a4000 {
534 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
535 reg = <0x020a4000 0x4000>;
536 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
537 <0 71 IRQ_TYPE_LEVEL_HIGH>;
538 gpio-controller;
539 #gpio-cells = <2>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 };
543
544 gpio4: gpio@020a8000 {
545 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
546 reg = <0x020a8000 0x4000>;
547 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
548 <0 73 IRQ_TYPE_LEVEL_HIGH>;
549 gpio-controller;
550 #gpio-cells = <2>;
551 interrupt-controller;
552 #interrupt-cells = <2>;
553 };
554
555 gpio5: gpio@020ac000 {
556 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
557 reg = <0x020ac000 0x4000>;
558 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
559 <0 75 IRQ_TYPE_LEVEL_HIGH>;
560 gpio-controller;
561 #gpio-cells = <2>;
562 interrupt-controller;
563 #interrupt-cells = <2>;
564 };
565
566 gpio6: gpio@020b0000 {
567 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
568 reg = <0x020b0000 0x4000>;
569 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
570 <0 77 IRQ_TYPE_LEVEL_HIGH>;
571 gpio-controller;
572 #gpio-cells = <2>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 };
576
577 gpio7: gpio@020b4000 {
578 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
579 reg = <0x020b4000 0x4000>;
580 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
581 <0 79 IRQ_TYPE_LEVEL_HIGH>;
582 gpio-controller;
583 #gpio-cells = <2>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 };
587
588 kpp: kpp@020b8000 {
589 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
590 reg = <0x020b8000 0x4000>;
591 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clks IMX6QDL_CLK_IPG>;
593 status = "disabled";
594 };
595
596 wdog1: wdog@020bc000 {
597 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
598 reg = <0x020bc000 0x4000>;
599 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clks IMX6QDL_CLK_DUMMY>;
601 };
602
603 wdog2: wdog@020c0000 {
604 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
605 reg = <0x020c0000 0x4000>;
606 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&clks IMX6QDL_CLK_DUMMY>;
608 status = "disabled";
609 };
610
611 clks: ccm@020c4000 {
612 compatible = "fsl,imx6q-ccm";
613 reg = <0x020c4000 0x4000>;
614 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
615 <0 88 IRQ_TYPE_LEVEL_HIGH>;
616 #clock-cells = <1>;
617 };
618
619 anatop: anatop@020c8000 {
620 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
621 reg = <0x020c8000 0x1000>;
622 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
623 <0 54 IRQ_TYPE_LEVEL_HIGH>,
624 <0 127 IRQ_TYPE_LEVEL_HIGH>;
625
626 regulator-1p1 {
627 compatible = "fsl,anatop-regulator";
628 regulator-name = "vdd1p1";
629 regulator-min-microvolt = <800000>;
630 regulator-max-microvolt = <1375000>;
631 regulator-always-on;
632 anatop-reg-offset = <0x110>;
633 anatop-vol-bit-shift = <8>;
634 anatop-vol-bit-width = <5>;
635 anatop-min-bit-val = <4>;
636 anatop-min-voltage = <800000>;
637 anatop-max-voltage = <1375000>;
638 };
639
640 regulator-3p0 {
641 compatible = "fsl,anatop-regulator";
642 regulator-name = "vdd3p0";
643 regulator-min-microvolt = <2800000>;
644 regulator-max-microvolt = <3150000>;
645 regulator-always-on;
646 anatop-reg-offset = <0x120>;
647 anatop-vol-bit-shift = <8>;
648 anatop-vol-bit-width = <5>;
649 anatop-min-bit-val = <0>;
650 anatop-min-voltage = <2625000>;
651 anatop-max-voltage = <3400000>;
652 };
653
654 regulator-2p5 {
655 compatible = "fsl,anatop-regulator";
656 regulator-name = "vdd2p5";
657 regulator-min-microvolt = <2000000>;
658 regulator-max-microvolt = <2750000>;
659 regulator-always-on;
660 anatop-reg-offset = <0x130>;
661 anatop-vol-bit-shift = <8>;
662 anatop-vol-bit-width = <5>;
663 anatop-min-bit-val = <0>;
664 anatop-min-voltage = <2000000>;
665 anatop-max-voltage = <2750000>;
666 };
667
668 reg_arm: regulator-vddcore {
669 compatible = "fsl,anatop-regulator";
670 regulator-name = "vddarm";
671 regulator-min-microvolt = <725000>;
672 regulator-max-microvolt = <1450000>;
673 regulator-always-on;
674 anatop-reg-offset = <0x140>;
675 anatop-vol-bit-shift = <0>;
676 anatop-vol-bit-width = <5>;
677 anatop-delay-reg-offset = <0x170>;
678 anatop-delay-bit-shift = <24>;
679 anatop-delay-bit-width = <2>;
680 anatop-min-bit-val = <1>;
681 anatop-min-voltage = <725000>;
682 anatop-max-voltage = <1450000>;
683 };
684
685 reg_pu: regulator-vddpu {
686 compatible = "fsl,anatop-regulator";
687 regulator-name = "vddpu";
688 regulator-min-microvolt = <725000>;
689 regulator-max-microvolt = <1450000>;
690 regulator-enable-ramp-delay = <150>;
691 anatop-reg-offset = <0x140>;
692 anatop-vol-bit-shift = <9>;
693 anatop-vol-bit-width = <5>;
694 anatop-delay-reg-offset = <0x170>;
695 anatop-delay-bit-shift = <26>;
696 anatop-delay-bit-width = <2>;
697 anatop-min-bit-val = <1>;
698 anatop-min-voltage = <725000>;
699 anatop-max-voltage = <1450000>;
700 };
701
702 reg_soc: regulator-vddsoc {
703 compatible = "fsl,anatop-regulator";
704 regulator-name = "vddsoc";
705 regulator-min-microvolt = <725000>;
706 regulator-max-microvolt = <1450000>;
707 regulator-always-on;
708 anatop-reg-offset = <0x140>;
709 anatop-vol-bit-shift = <18>;
710 anatop-vol-bit-width = <5>;
711 anatop-delay-reg-offset = <0x170>;
712 anatop-delay-bit-shift = <28>;
713 anatop-delay-bit-width = <2>;
714 anatop-min-bit-val = <1>;
715 anatop-min-voltage = <725000>;
716 anatop-max-voltage = <1450000>;
717 };
718 };
719
720 tempmon: tempmon {
721 compatible = "fsl,imx6q-tempmon";
722 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
723 fsl,tempmon = <&anatop>;
724 fsl,tempmon-data = <&ocotp>;
725 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
726 };
727
728 usbphy1: usbphy@020c9000 {
729 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
730 reg = <0x020c9000 0x1000>;
731 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
733 fsl,anatop = <&anatop>;
734 };
735
736 usbphy2: usbphy@020ca000 {
737 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
738 reg = <0x020ca000 0x1000>;
739 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
741 fsl,anatop = <&anatop>;
742 };
743
744 snvs: snvs@020cc000 {
745 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
746 reg = <0x020cc000 0x4000>;
747
748 snvs_rtc: snvs-rtc-lp {
749 compatible = "fsl,sec-v4.0-mon-rtc-lp";
750 regmap = <&snvs>;
751 offset = <0x34>;
752 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
753 <0 20 IRQ_TYPE_LEVEL_HIGH>;
754 };
755
756 snvs_poweroff: snvs-poweroff {
757 compatible = "syscon-poweroff";
758 regmap = <&snvs>;
759 offset = <0x38>;
760 mask = <0x60>;
761 status = "disabled";
762 };
763 };
764
765 epit1: epit@020d0000 { /* EPIT1 */
766 reg = <0x020d0000 0x4000>;
767 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
768 };
769
770 epit2: epit@020d4000 { /* EPIT2 */
771 reg = <0x020d4000 0x4000>;
772 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
773 };
774
775 src: src@020d8000 {
776 compatible = "fsl,imx6q-src", "fsl,imx51-src";
777 reg = <0x020d8000 0x4000>;
778 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
779 <0 96 IRQ_TYPE_LEVEL_HIGH>;
780 #reset-cells = <1>;
781 };
782
783 gpc: gpc@020dc000 {
784 compatible = "fsl,imx6q-gpc";
785 reg = <0x020dc000 0x4000>;
786 interrupt-controller;
787 #interrupt-cells = <3>;
788 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
789 <0 90 IRQ_TYPE_LEVEL_HIGH>;
790 interrupt-parent = <&intc>;
791 pu-supply = <&reg_pu>;
792 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
793 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
794 <&clks IMX6QDL_CLK_GPU2D_CORE>,
795 <&clks IMX6QDL_CLK_GPU2D_AXI>,
796 <&clks IMX6QDL_CLK_OPENVG_AXI>,
797 <&clks IMX6QDL_CLK_VPU_AXI>;
798 #power-domain-cells = <1>;
799 };
800
801 gpr: iomuxc-gpr@020e0000 {
802 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
803 reg = <0x020e0000 0x38>;
804 };
805
806 iomuxc: iomuxc@020e0000 {
807 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
808 reg = <0x020e0000 0x4000>;
809 };
810
811 ldb: ldb@020e0008 {
812 #address-cells = <1>;
813 #size-cells = <0>;
814 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
815 gpr = <&gpr>;
816 status = "disabled";
817
818 lvds-channel@0 {
819 #address-cells = <1>;
820 #size-cells = <0>;
821 reg = <0>;
822 status = "disabled";
823
824 port@0 {
825 reg = <0>;
826
827 lvds0_mux_0: endpoint {
828 remote-endpoint = <&ipu1_di0_lvds0>;
829 };
830 };
831
832 port@1 {
833 reg = <1>;
834
835 lvds0_mux_1: endpoint {
836 remote-endpoint = <&ipu1_di1_lvds0>;
837 };
838 };
839 };
840
841 lvds-channel@1 {
842 #address-cells = <1>;
843 #size-cells = <0>;
844 reg = <1>;
845 status = "disabled";
846
847 port@0 {
848 reg = <0>;
849
850 lvds1_mux_0: endpoint {
851 remote-endpoint = <&ipu1_di0_lvds1>;
852 };
853 };
854
855 port@1 {
856 reg = <1>;
857
858 lvds1_mux_1: endpoint {
859 remote-endpoint = <&ipu1_di1_lvds1>;
860 };
861 };
862 };
863 };
864
865 dcic1: dcic@020e4000 {
866 reg = <0x020e4000 0x4000>;
867 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
868 };
869
870 dcic2: dcic@020e8000 {
871 reg = <0x020e8000 0x4000>;
872 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
873 };
874
875 sdma: sdma@020ec000 {
876 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
877 reg = <0x020ec000 0x4000>;
878 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clks IMX6QDL_CLK_SDMA>,
880 <&clks IMX6QDL_CLK_SDMA>;
881 clock-names = "ipg", "ahb";
882 #dma-cells = <3>;
883 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
884 };
885 };
886
887 aips-bus@02100000 { /* AIPS2 */
888 compatible = "fsl,aips-bus", "simple-bus";
889 #address-cells = <1>;
890 #size-cells = <1>;
891 reg = <0x02100000 0x100000>;
892 ranges;
893
894 crypto: caam@2100000 {
895 compatible = "fsl,sec-v4.0";
896 fsl,sec-era = <4>;
897 #address-cells = <1>;
898 #size-cells = <1>;
899 reg = <0x2100000 0x10000>;
900 ranges = <0 0x2100000 0x10000>;
901 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
902 <&clks IMX6QDL_CLK_CAAM_ACLK>,
903 <&clks IMX6QDL_CLK_CAAM_IPG>,
904 <&clks IMX6QDL_CLK_EIM_SLOW>;
905 clock-names = "mem", "aclk", "ipg", "emi_slow";
906
907 sec_jr0: jr0@1000 {
908 compatible = "fsl,sec-v4.0-job-ring";
909 reg = <0x1000 0x1000>;
910 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
911 };
912
913 sec_jr1: jr1@2000 {
914 compatible = "fsl,sec-v4.0-job-ring";
915 reg = <0x2000 0x1000>;
916 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
917 };
918 };
919
920 aipstz@0217c000 { /* AIPSTZ2 */
921 reg = <0x0217c000 0x4000>;
922 };
923
924 usbotg: usb@02184000 {
925 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
926 reg = <0x02184000 0x200>;
927 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clks IMX6QDL_CLK_USBOH3>;
929 fsl,usbphy = <&usbphy1>;
930 fsl,usbmisc = <&usbmisc 0>;
931 ahb-burst-config = <0x0>;
932 tx-burst-size-dword = <0x10>;
933 rx-burst-size-dword = <0x10>;
934 status = "disabled";
935 };
936
937 usbh1: usb@02184200 {
938 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
939 reg = <0x02184200 0x200>;
940 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
941 clocks = <&clks IMX6QDL_CLK_USBOH3>;
942 fsl,usbphy = <&usbphy2>;
943 fsl,usbmisc = <&usbmisc 1>;
944 dr_mode = "host";
945 ahb-burst-config = <0x0>;
946 tx-burst-size-dword = <0x10>;
947 rx-burst-size-dword = <0x10>;
948 status = "disabled";
949 };
950
951 usbh2: usb@02184400 {
952 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
953 reg = <0x02184400 0x200>;
954 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&clks IMX6QDL_CLK_USBOH3>;
956 fsl,usbmisc = <&usbmisc 2>;
957 dr_mode = "host";
958 ahb-burst-config = <0x0>;
959 tx-burst-size-dword = <0x10>;
960 rx-burst-size-dword = <0x10>;
961 status = "disabled";
962 };
963
964 usbh3: usb@02184600 {
965 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
966 reg = <0x02184600 0x200>;
967 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&clks IMX6QDL_CLK_USBOH3>;
969 fsl,usbmisc = <&usbmisc 3>;
970 dr_mode = "host";
971 ahb-burst-config = <0x0>;
972 tx-burst-size-dword = <0x10>;
973 rx-burst-size-dword = <0x10>;
974 status = "disabled";
975 };
976
977 usbmisc: usbmisc@02184800 {
978 #index-cells = <1>;
979 compatible = "fsl,imx6q-usbmisc";
980 reg = <0x02184800 0x200>;
981 clocks = <&clks IMX6QDL_CLK_USBOH3>;
982 };
983
984 fec: ethernet@02188000 {
985 compatible = "fsl,imx6q-fec";
986 reg = <0x02188000 0x4000>;
987 interrupts-extended =
988 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
989 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&clks IMX6QDL_CLK_ENET>,
991 <&clks IMX6QDL_CLK_ENET>,
992 <&clks IMX6QDL_CLK_ENET_REF>;
993 clock-names = "ipg", "ahb", "ptp";
994 status = "disabled";
995 };
996
997 mlb@0218c000 {
998 reg = <0x0218c000 0x4000>;
999 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1000 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1001 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1002 };
1003
1004 usdhc1: usdhc@02190000 {
1005 compatible = "fsl,imx6q-usdhc";
1006 reg = <0x02190000 0x4000>;
1007 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1009 <&clks IMX6QDL_CLK_USDHC1>,
1010 <&clks IMX6QDL_CLK_USDHC1>;
1011 clock-names = "ipg", "ahb", "per";
1012 bus-width = <4>;
1013 status = "disabled";
1014 };
1015
1016 usdhc2: usdhc@02194000 {
1017 compatible = "fsl,imx6q-usdhc";
1018 reg = <0x02194000 0x4000>;
1019 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1021 <&clks IMX6QDL_CLK_USDHC2>,
1022 <&clks IMX6QDL_CLK_USDHC2>;
1023 clock-names = "ipg", "ahb", "per";
1024 bus-width = <4>;
1025 status = "disabled";
1026 };
1027
1028 usdhc3: usdhc@02198000 {
1029 compatible = "fsl,imx6q-usdhc";
1030 reg = <0x02198000 0x4000>;
1031 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1033 <&clks IMX6QDL_CLK_USDHC3>,
1034 <&clks IMX6QDL_CLK_USDHC3>;
1035 clock-names = "ipg", "ahb", "per";
1036 bus-width = <4>;
1037 status = "disabled";
1038 };
1039
1040 usdhc4: usdhc@0219c000 {
1041 compatible = "fsl,imx6q-usdhc";
1042 reg = <0x0219c000 0x4000>;
1043 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1045 <&clks IMX6QDL_CLK_USDHC4>,
1046 <&clks IMX6QDL_CLK_USDHC4>;
1047 clock-names = "ipg", "ahb", "per";
1048 bus-width = <4>;
1049 status = "disabled";
1050 };
1051
1052 i2c1: i2c@021a0000 {
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1056 reg = <0x021a0000 0x4000>;
1057 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1058 clocks = <&clks IMX6QDL_CLK_I2C1>;
1059 status = "disabled";
1060 };
1061
1062 i2c2: i2c@021a4000 {
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1066 reg = <0x021a4000 0x4000>;
1067 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&clks IMX6QDL_CLK_I2C2>;
1069 status = "disabled";
1070 };
1071
1072 i2c3: i2c@021a8000 {
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1075 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1076 reg = <0x021a8000 0x4000>;
1077 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&clks IMX6QDL_CLK_I2C3>;
1079 status = "disabled";
1080 };
1081
1082 romcp@021ac000 {
1083 reg = <0x021ac000 0x4000>;
1084 };
1085
1086 mmdc0: mmdc@021b0000 { /* MMDC0 */
1087 compatible = "fsl,imx6q-mmdc";
1088 reg = <0x021b0000 0x4000>;
1089 };
1090
1091 mmdc1: mmdc@021b4000 { /* MMDC1 */
1092 reg = <0x021b4000 0x4000>;
1093 };
1094
1095 weim: weim@021b8000 {
1096 #address-cells = <2>;
1097 #size-cells = <1>;
1098 compatible = "fsl,imx6q-weim";
1099 reg = <0x021b8000 0x4000>;
1100 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1101 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1102 fsl,weim-cs-gpr = <&gpr>;
1103 status = "disabled";
1104 };
1105
1106 ocotp: ocotp@021bc000 {
1107 compatible = "fsl,imx6q-ocotp", "syscon";
1108 reg = <0x021bc000 0x4000>;
1109 clocks = <&clks IMX6QDL_CLK_IIM>;
1110 };
1111
1112 tzasc@021d0000 { /* TZASC1 */
1113 reg = <0x021d0000 0x4000>;
1114 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1115 };
1116
1117 tzasc@021d4000 { /* TZASC2 */
1118 reg = <0x021d4000 0x4000>;
1119 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1120 };
1121
1122 audmux: audmux@021d8000 {
1123 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1124 reg = <0x021d8000 0x4000>;
1125 status = "disabled";
1126 };
1127
1128 mipi_csi: mipi@021dc000 {
1129 reg = <0x021dc000 0x4000>;
1130 };
1131
1132 mipi_dsi: mipi@021e0000 {
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1135 reg = <0x021e0000 0x4000>;
1136 status = "disabled";
1137
1138 ports {
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141
1142 port@0 {
1143 reg = <0>;
1144
1145 mipi_mux_0: endpoint {
1146 remote-endpoint = <&ipu1_di0_mipi>;
1147 };
1148 };
1149
1150 port@1 {
1151 reg = <1>;
1152
1153 mipi_mux_1: endpoint {
1154 remote-endpoint = <&ipu1_di1_mipi>;
1155 };
1156 };
1157 };
1158 };
1159
1160 vdoa@021e4000 {
1161 reg = <0x021e4000 0x4000>;
1162 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1163 };
1164
1165 uart2: serial@021e8000 {
1166 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1167 reg = <0x021e8000 0x4000>;
1168 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1170 <&clks IMX6QDL_CLK_UART_SERIAL>;
1171 clock-names = "ipg", "per";
1172 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1173 dma-names = "rx", "tx";
1174 status = "disabled";
1175 };
1176
1177 uart3: serial@021ec000 {
1178 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1179 reg = <0x021ec000 0x4000>;
1180 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1182 <&clks IMX6QDL_CLK_UART_SERIAL>;
1183 clock-names = "ipg", "per";
1184 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1185 dma-names = "rx", "tx";
1186 status = "disabled";
1187 };
1188
1189 uart4: serial@021f0000 {
1190 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1191 reg = <0x021f0000 0x4000>;
1192 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1194 <&clks IMX6QDL_CLK_UART_SERIAL>;
1195 clock-names = "ipg", "per";
1196 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1197 dma-names = "rx", "tx";
1198 status = "disabled";
1199 };
1200
1201 uart5: serial@021f4000 {
1202 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1203 reg = <0x021f4000 0x4000>;
1204 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1206 <&clks IMX6QDL_CLK_UART_SERIAL>;
1207 clock-names = "ipg", "per";
1208 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1209 dma-names = "rx", "tx";
1210 status = "disabled";
1211 };
1212 };
1213
1214 ipu1: ipu@02400000 {
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217 compatible = "fsl,imx6q-ipu";
1218 reg = <0x02400000 0x400000>;
1219 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1220 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1221 clocks = <&clks IMX6QDL_CLK_IPU1>,
1222 <&clks IMX6QDL_CLK_IPU1_DI0>,
1223 <&clks IMX6QDL_CLK_IPU1_DI1>;
1224 clock-names = "bus", "di0", "di1";
1225 resets = <&src 2>;
1226
1227 ipu1_csi0: port@0 {
1228 reg = <0>;
1229 };
1230
1231 ipu1_csi1: port@1 {
1232 reg = <1>;
1233 };
1234
1235 ipu1_di0: port@2 {
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1238 reg = <2>;
1239
1240 ipu1_di0_disp0: disp0-endpoint {
1241 };
1242
1243 ipu1_di0_hdmi: hdmi-endpoint {
1244 remote-endpoint = <&hdmi_mux_0>;
1245 };
1246
1247 ipu1_di0_mipi: mipi-endpoint {
1248 remote-endpoint = <&mipi_mux_0>;
1249 };
1250
1251 ipu1_di0_lvds0: lvds0-endpoint {
1252 remote-endpoint = <&lvds0_mux_0>;
1253 };
1254
1255 ipu1_di0_lvds1: lvds1-endpoint {
1256 remote-endpoint = <&lvds1_mux_0>;
1257 };
1258 };
1259
1260 ipu1_di1: port@3 {
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1263 reg = <3>;
1264
1265 ipu1_di1_disp1: disp1-endpoint {
1266 };
1267
1268 ipu1_di1_hdmi: hdmi-endpoint {
1269 remote-endpoint = <&hdmi_mux_1>;
1270 };
1271
1272 ipu1_di1_mipi: mipi-endpoint {
1273 remote-endpoint = <&mipi_mux_1>;
1274 };
1275
1276 ipu1_di1_lvds0: lvds0-endpoint {
1277 remote-endpoint = <&lvds0_mux_1>;
1278 };
1279
1280 ipu1_di1_lvds1: lvds1-endpoint {
1281 remote-endpoint = <&lvds1_mux_1>;
1282 };
1283 };
1284 };
1285 };
1286 };
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