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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / imx6sl.dtsi
1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "skeleton.dtsi"
12 #include "imx6sl-pinfunc.h"
13 #include <dt-bindings/clock/imx6sl-clock.h>
14
15 / {
16 aliases {
17 ethernet0 = &fec;
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 serial3 = &uart4;
27 serial4 = &uart5;
28 spi0 = &ecspi1;
29 spi1 = &ecspi2;
30 spi2 = &ecspi3;
31 spi3 = &ecspi4;
32 usbphy0 = &usbphy1;
33 usbphy1 = &usbphy2;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0x0>;
44 next-level-cache = <&L2>;
45 operating-points = <
46 /* kHz uV */
47 996000 1275000
48 792000 1175000
49 396000 975000
50 >;
51 fsl,soc-operating-points = <
52 /* ARM kHz SOC-PU uV */
53 996000 1225000
54 792000 1175000
55 396000 1175000
56 >;
57 clock-latency = <61036>; /* two CLK32 periods */
58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
61 clock-names = "arm", "pll2_pfd2_396m", "step",
62 "pll1_sw", "pll1_sys";
63 arm-supply = <&reg_arm>;
64 pu-supply = <&reg_pu>;
65 soc-supply = <&reg_soc>;
66 };
67 };
68
69 intc: interrupt-controller@00a01000 {
70 compatible = "arm,cortex-a9-gic";
71 #interrupt-cells = <3>;
72 interrupt-controller;
73 reg = <0x00a01000 0x1000>,
74 <0x00a00100 0x100>;
75 interrupt-parent = <&intc>;
76 };
77
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 ckil {
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <32768>;
86 };
87
88 osc {
89 compatible = "fixed-clock";
90 #clock-cells = <0>;
91 clock-frequency = <24000000>;
92 };
93 };
94
95 soc {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "simple-bus";
99 interrupt-parent = <&gpc>;
100 ranges;
101
102 ocram: sram@00900000 {
103 compatible = "mmio-sram";
104 reg = <0x00900000 0x20000>;
105 clocks = <&clks IMX6SL_CLK_OCRAM>;
106 };
107
108 L2: l2-cache@00a02000 {
109 compatible = "arm,pl310-cache";
110 reg = <0x00a02000 0x1000>;
111 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
112 cache-unified;
113 cache-level = <2>;
114 arm,tag-latency = <4 2 3>;
115 arm,data-latency = <4 2 3>;
116 };
117
118 pmu {
119 compatible = "arm,cortex-a9-pmu";
120 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
121 };
122
123 aips1: aips-bus@02000000 {
124 compatible = "fsl,aips-bus", "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 reg = <0x02000000 0x100000>;
128 ranges;
129
130 spba: spba-bus@02000000 {
131 compatible = "fsl,spba-bus", "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 reg = <0x02000000 0x40000>;
135 ranges;
136
137 spdif: spdif@02004000 {
138 compatible = "fsl,imx6sl-spdif",
139 "fsl,imx35-spdif";
140 reg = <0x02004000 0x4000>;
141 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
142 dmas = <&sdma 14 18 0>,
143 <&sdma 15 18 0>;
144 dma-names = "rx", "tx";
145 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
146 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
147 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
148 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
149 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
150 clock-names = "core", "rxtx0",
151 "rxtx1", "rxtx2",
152 "rxtx3", "rxtx4",
153 "rxtx5", "rxtx6",
154 "rxtx7", "spba";
155 status = "disabled";
156 };
157
158 ecspi1: ecspi@02008000 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
162 reg = <0x02008000 0x4000>;
163 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&clks IMX6SL_CLK_ECSPI1>,
165 <&clks IMX6SL_CLK_ECSPI1>;
166 clock-names = "ipg", "per";
167 status = "disabled";
168 };
169
170 ecspi2: ecspi@0200c000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
174 reg = <0x0200c000 0x4000>;
175 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6SL_CLK_ECSPI2>,
177 <&clks IMX6SL_CLK_ECSPI2>;
178 clock-names = "ipg", "per";
179 status = "disabled";
180 };
181
182 ecspi3: ecspi@02010000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02010000 0x4000>;
187 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clks IMX6SL_CLK_ECSPI3>,
189 <&clks IMX6SL_CLK_ECSPI3>;
190 clock-names = "ipg", "per";
191 status = "disabled";
192 };
193
194 ecspi4: ecspi@02014000 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
198 reg = <0x02014000 0x4000>;
199 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clks IMX6SL_CLK_ECSPI4>,
201 <&clks IMX6SL_CLK_ECSPI4>;
202 clock-names = "ipg", "per";
203 status = "disabled";
204 };
205
206 uart5: serial@02018000 {
207 compatible = "fsl,imx6sl-uart",
208 "fsl,imx6q-uart", "fsl,imx21-uart";
209 reg = <0x02018000 0x4000>;
210 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clks IMX6SL_CLK_UART>,
212 <&clks IMX6SL_CLK_UART_SERIAL>;
213 clock-names = "ipg", "per";
214 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
215 dma-names = "rx", "tx";
216 status = "disabled";
217 };
218
219 uart1: serial@02020000 {
220 compatible = "fsl,imx6sl-uart",
221 "fsl,imx6q-uart", "fsl,imx21-uart";
222 reg = <0x02020000 0x4000>;
223 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6SL_CLK_UART>,
225 <&clks IMX6SL_CLK_UART_SERIAL>;
226 clock-names = "ipg", "per";
227 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
228 dma-names = "rx", "tx";
229 status = "disabled";
230 };
231
232 uart2: serial@02024000 {
233 compatible = "fsl,imx6sl-uart",
234 "fsl,imx6q-uart", "fsl,imx21-uart";
235 reg = <0x02024000 0x4000>;
236 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&clks IMX6SL_CLK_UART>,
238 <&clks IMX6SL_CLK_UART_SERIAL>;
239 clock-names = "ipg", "per";
240 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
241 dma-names = "rx", "tx";
242 status = "disabled";
243 };
244
245 ssi1: ssi@02028000 {
246 #sound-dai-cells = <0>;
247 compatible = "fsl,imx6sl-ssi",
248 "fsl,imx51-ssi";
249 reg = <0x02028000 0x4000>;
250 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
252 <&clks IMX6SL_CLK_SSI1>;
253 clock-names = "ipg", "baud";
254 dmas = <&sdma 37 1 0>,
255 <&sdma 38 1 0>;
256 dma-names = "rx", "tx";
257 fsl,fifo-depth = <15>;
258 status = "disabled";
259 };
260
261 ssi2: ssi@0202c000 {
262 #sound-dai-cells = <0>;
263 compatible = "fsl,imx6sl-ssi",
264 "fsl,imx51-ssi";
265 reg = <0x0202c000 0x4000>;
266 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
268 <&clks IMX6SL_CLK_SSI2>;
269 clock-names = "ipg", "baud";
270 dmas = <&sdma 41 1 0>,
271 <&sdma 42 1 0>;
272 dma-names = "rx", "tx";
273 fsl,fifo-depth = <15>;
274 status = "disabled";
275 };
276
277 ssi3: ssi@02030000 {
278 #sound-dai-cells = <0>;
279 compatible = "fsl,imx6sl-ssi",
280 "fsl,imx51-ssi";
281 reg = <0x02030000 0x4000>;
282 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
284 <&clks IMX6SL_CLK_SSI3>;
285 clock-names = "ipg", "baud";
286 dmas = <&sdma 45 1 0>,
287 <&sdma 46 1 0>;
288 dma-names = "rx", "tx";
289 fsl,fifo-depth = <15>;
290 status = "disabled";
291 };
292
293 uart3: serial@02034000 {
294 compatible = "fsl,imx6sl-uart",
295 "fsl,imx6q-uart", "fsl,imx21-uart";
296 reg = <0x02034000 0x4000>;
297 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&clks IMX6SL_CLK_UART>,
299 <&clks IMX6SL_CLK_UART_SERIAL>;
300 clock-names = "ipg", "per";
301 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
302 dma-names = "rx", "tx";
303 status = "disabled";
304 };
305
306 uart4: serial@02038000 {
307 compatible = "fsl,imx6sl-uart",
308 "fsl,imx6q-uart", "fsl,imx21-uart";
309 reg = <0x02038000 0x4000>;
310 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clks IMX6SL_CLK_UART>,
312 <&clks IMX6SL_CLK_UART_SERIAL>;
313 clock-names = "ipg", "per";
314 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
315 dma-names = "rx", "tx";
316 status = "disabled";
317 };
318 };
319
320 pwm1: pwm@02080000 {
321 #pwm-cells = <2>;
322 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
323 reg = <0x02080000 0x4000>;
324 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clks IMX6SL_CLK_PWM1>,
326 <&clks IMX6SL_CLK_PWM1>;
327 clock-names = "ipg", "per";
328 };
329
330 pwm2: pwm@02084000 {
331 #pwm-cells = <2>;
332 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
333 reg = <0x02084000 0x4000>;
334 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&clks IMX6SL_CLK_PWM2>,
336 <&clks IMX6SL_CLK_PWM2>;
337 clock-names = "ipg", "per";
338 };
339
340 pwm3: pwm@02088000 {
341 #pwm-cells = <2>;
342 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
343 reg = <0x02088000 0x4000>;
344 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6SL_CLK_PWM3>,
346 <&clks IMX6SL_CLK_PWM3>;
347 clock-names = "ipg", "per";
348 };
349
350 pwm4: pwm@0208c000 {
351 #pwm-cells = <2>;
352 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
353 reg = <0x0208c000 0x4000>;
354 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clks IMX6SL_CLK_PWM4>,
356 <&clks IMX6SL_CLK_PWM4>;
357 clock-names = "ipg", "per";
358 };
359
360 gpt: gpt@02098000 {
361 compatible = "fsl,imx6sl-gpt";
362 reg = <0x02098000 0x4000>;
363 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6SL_CLK_GPT>,
365 <&clks IMX6SL_CLK_GPT_SERIAL>;
366 clock-names = "ipg", "per";
367 };
368
369 gpio1: gpio@0209c000 {
370 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
371 reg = <0x0209c000 0x4000>;
372 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
373 <0 67 IRQ_TYPE_LEVEL_HIGH>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
379 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
380 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
381 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
382 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
383 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
384 };
385
386 gpio2: gpio@020a0000 {
387 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
388 reg = <0x020a0000 0x4000>;
389 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
390 <0 69 IRQ_TYPE_LEVEL_HIGH>;
391 gpio-controller;
392 #gpio-cells = <2>;
393 interrupt-controller;
394 #interrupt-cells = <2>;
395 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
396 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
397 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
398 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
399 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
400 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
401 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
402 };
403
404 gpio3: gpio@020a4000 {
405 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
406 reg = <0x020a4000 0x4000>;
407 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
408 <0 71 IRQ_TYPE_LEVEL_HIGH>;
409 gpio-controller;
410 #gpio-cells = <2>;
411 interrupt-controller;
412 #interrupt-cells = <2>;
413 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
414 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
415 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
416 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
417 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
418 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
419 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
420 <&iomuxc 31 102 1>;
421 };
422
423 gpio4: gpio@020a8000 {
424 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
425 reg = <0x020a8000 0x4000>;
426 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
427 <0 73 IRQ_TYPE_LEVEL_HIGH>;
428 gpio-controller;
429 #gpio-cells = <2>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
433 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
434 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
435 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
436 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
437 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
438 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
439 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
440 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
441 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
442 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
443 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
444 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
445 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
446 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
447 };
448
449 gpio5: gpio@020ac000 {
450 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
451 reg = <0x020ac000 0x4000>;
452 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
453 <0 75 IRQ_TYPE_LEVEL_HIGH>;
454 gpio-controller;
455 #gpio-cells = <2>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
458 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
459 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
460 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
461 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
462 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
463 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
464 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
465 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
466 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
467 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
468 <&iomuxc 21 161 1>;
469 };
470
471 kpp: kpp@020b8000 {
472 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
473 reg = <0x020b8000 0x4000>;
474 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clks IMX6SL_CLK_DUMMY>;
476 status = "disabled";
477 };
478
479 wdog1: wdog@020bc000 {
480 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
481 reg = <0x020bc000 0x4000>;
482 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clks IMX6SL_CLK_DUMMY>;
484 };
485
486 wdog2: wdog@020c0000 {
487 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
488 reg = <0x020c0000 0x4000>;
489 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&clks IMX6SL_CLK_DUMMY>;
491 status = "disabled";
492 };
493
494 clks: ccm@020c4000 {
495 compatible = "fsl,imx6sl-ccm";
496 reg = <0x020c4000 0x4000>;
497 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
498 <0 88 IRQ_TYPE_LEVEL_HIGH>;
499 #clock-cells = <1>;
500 };
501
502 anatop: anatop@020c8000 {
503 compatible = "fsl,imx6sl-anatop",
504 "fsl,imx6q-anatop",
505 "syscon", "simple-bus";
506 reg = <0x020c8000 0x1000>;
507 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
508 <0 54 IRQ_TYPE_LEVEL_HIGH>,
509 <0 127 IRQ_TYPE_LEVEL_HIGH>;
510
511 regulator-1p1 {
512 compatible = "fsl,anatop-regulator";
513 regulator-name = "vdd1p1";
514 regulator-min-microvolt = <800000>;
515 regulator-max-microvolt = <1375000>;
516 regulator-always-on;
517 anatop-reg-offset = <0x110>;
518 anatop-vol-bit-shift = <8>;
519 anatop-vol-bit-width = <5>;
520 anatop-min-bit-val = <4>;
521 anatop-min-voltage = <800000>;
522 anatop-max-voltage = <1375000>;
523 };
524
525 regulator-3p0 {
526 compatible = "fsl,anatop-regulator";
527 regulator-name = "vdd3p0";
528 regulator-min-microvolt = <2800000>;
529 regulator-max-microvolt = <3150000>;
530 regulator-always-on;
531 anatop-reg-offset = <0x120>;
532 anatop-vol-bit-shift = <8>;
533 anatop-vol-bit-width = <5>;
534 anatop-min-bit-val = <0>;
535 anatop-min-voltage = <2625000>;
536 anatop-max-voltage = <3400000>;
537 };
538
539 regulator-2p5 {
540 compatible = "fsl,anatop-regulator";
541 regulator-name = "vdd2p5";
542 regulator-min-microvolt = <2100000>;
543 regulator-max-microvolt = <2850000>;
544 regulator-always-on;
545 anatop-reg-offset = <0x130>;
546 anatop-vol-bit-shift = <8>;
547 anatop-vol-bit-width = <5>;
548 anatop-min-bit-val = <0>;
549 anatop-min-voltage = <2100000>;
550 anatop-max-voltage = <2850000>;
551 };
552
553 reg_arm: regulator-vddcore {
554 compatible = "fsl,anatop-regulator";
555 regulator-name = "vddarm";
556 regulator-min-microvolt = <725000>;
557 regulator-max-microvolt = <1450000>;
558 regulator-always-on;
559 anatop-reg-offset = <0x140>;
560 anatop-vol-bit-shift = <0>;
561 anatop-vol-bit-width = <5>;
562 anatop-delay-reg-offset = <0x170>;
563 anatop-delay-bit-shift = <24>;
564 anatop-delay-bit-width = <2>;
565 anatop-min-bit-val = <1>;
566 anatop-min-voltage = <725000>;
567 anatop-max-voltage = <1450000>;
568 };
569
570 reg_pu: regulator-vddpu {
571 compatible = "fsl,anatop-regulator";
572 regulator-name = "vddpu";
573 regulator-min-microvolt = <725000>;
574 regulator-max-microvolt = <1450000>;
575 regulator-always-on;
576 anatop-reg-offset = <0x140>;
577 anatop-vol-bit-shift = <9>;
578 anatop-vol-bit-width = <5>;
579 anatop-delay-reg-offset = <0x170>;
580 anatop-delay-bit-shift = <26>;
581 anatop-delay-bit-width = <2>;
582 anatop-min-bit-val = <1>;
583 anatop-min-voltage = <725000>;
584 anatop-max-voltage = <1450000>;
585 };
586
587 reg_soc: regulator-vddsoc {
588 compatible = "fsl,anatop-regulator";
589 regulator-name = "vddsoc";
590 regulator-min-microvolt = <725000>;
591 regulator-max-microvolt = <1450000>;
592 regulator-always-on;
593 anatop-reg-offset = <0x140>;
594 anatop-vol-bit-shift = <18>;
595 anatop-vol-bit-width = <5>;
596 anatop-delay-reg-offset = <0x170>;
597 anatop-delay-bit-shift = <28>;
598 anatop-delay-bit-width = <2>;
599 anatop-min-bit-val = <1>;
600 anatop-min-voltage = <725000>;
601 anatop-max-voltage = <1450000>;
602 };
603 };
604
605 tempmon: tempmon {
606 compatible = "fsl,imx6q-tempmon";
607 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
608 fsl,tempmon = <&anatop>;
609 fsl,tempmon-data = <&ocotp>;
610 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
611 };
612
613 usbphy1: usbphy@020c9000 {
614 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
615 reg = <0x020c9000 0x1000>;
616 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&clks IMX6SL_CLK_USBPHY1>;
618 fsl,anatop = <&anatop>;
619 };
620
621 usbphy2: usbphy@020ca000 {
622 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
623 reg = <0x020ca000 0x1000>;
624 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clks IMX6SL_CLK_USBPHY2>;
626 fsl,anatop = <&anatop>;
627 };
628
629 snvs: snvs@020cc000 {
630 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
631 reg = <0x020cc000 0x4000>;
632
633 snvs_rtc: snvs-rtc-lp {
634 compatible = "fsl,sec-v4.0-mon-rtc-lp";
635 regmap = <&snvs>;
636 offset = <0x34>;
637 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
638 <0 20 IRQ_TYPE_LEVEL_HIGH>;
639 };
640
641 snvs_poweroff: snvs-poweroff {
642 compatible = "syscon-poweroff";
643 regmap = <&snvs>;
644 offset = <0x38>;
645 mask = <0x60>;
646 status = "disabled";
647 };
648 };
649
650 epit1: epit@020d0000 {
651 reg = <0x020d0000 0x4000>;
652 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
653 };
654
655 epit2: epit@020d4000 {
656 reg = <0x020d4000 0x4000>;
657 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
658 };
659
660 src: src@020d8000 {
661 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
662 reg = <0x020d8000 0x4000>;
663 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
664 <0 96 IRQ_TYPE_LEVEL_HIGH>;
665 #reset-cells = <1>;
666 };
667
668 gpc: gpc@020dc000 {
669 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
670 reg = <0x020dc000 0x4000>;
671 interrupt-controller;
672 #interrupt-cells = <3>;
673 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
674 interrupt-parent = <&intc>;
675 pu-supply = <&reg_pu>;
676 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
677 <&clks IMX6SL_CLK_GPU2D_PODF>;
678 #power-domain-cells = <1>;
679 };
680
681 gpr: iomuxc-gpr@020e0000 {
682 compatible = "fsl,imx6sl-iomuxc-gpr",
683 "fsl,imx6q-iomuxc-gpr", "syscon";
684 reg = <0x020e0000 0x38>;
685 };
686
687 iomuxc: iomuxc@020e0000 {
688 compatible = "fsl,imx6sl-iomuxc";
689 reg = <0x020e0000 0x4000>;
690 };
691
692 csi: csi@020e4000 {
693 reg = <0x020e4000 0x4000>;
694 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
695 };
696
697 spdc: spdc@020e8000 {
698 reg = <0x020e8000 0x4000>;
699 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
700 };
701
702 sdma: sdma@020ec000 {
703 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
704 reg = <0x020ec000 0x4000>;
705 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&clks IMX6SL_CLK_SDMA>,
707 <&clks IMX6SL_CLK_SDMA>;
708 clock-names = "ipg", "ahb";
709 #dma-cells = <3>;
710 /* imx6sl reuses imx6q sdma firmware */
711 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
712 };
713
714 pxp: pxp@020f0000 {
715 reg = <0x020f0000 0x4000>;
716 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
717 };
718
719 epdc: epdc@020f4000 {
720 reg = <0x020f4000 0x4000>;
721 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
722 };
723
724 lcdif: lcdif@020f8000 {
725 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
726 reg = <0x020f8000 0x4000>;
727 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
729 <&clks IMX6SL_CLK_LCDIF_AXI>,
730 <&clks IMX6SL_CLK_DUMMY>;
731 clock-names = "pix", "axi", "disp_axi";
732 status = "disabled";
733 };
734
735 dcp: dcp@020fc000 {
736 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
737 reg = <0x020fc000 0x4000>;
738 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
739 <0 100 IRQ_TYPE_LEVEL_HIGH>,
740 <0 101 IRQ_TYPE_LEVEL_HIGH>;
741 };
742 };
743
744 aips2: aips-bus@02100000 {
745 compatible = "fsl,aips-bus", "simple-bus";
746 #address-cells = <1>;
747 #size-cells = <1>;
748 reg = <0x02100000 0x100000>;
749 ranges;
750
751 usbotg1: usb@02184000 {
752 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
753 reg = <0x02184000 0x200>;
754 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&clks IMX6SL_CLK_USBOH3>;
756 fsl,usbphy = <&usbphy1>;
757 fsl,usbmisc = <&usbmisc 0>;
758 ahb-burst-config = <0x0>;
759 tx-burst-size-dword = <0x10>;
760 rx-burst-size-dword = <0x10>;
761 status = "disabled";
762 };
763
764 usbotg2: usb@02184200 {
765 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
766 reg = <0x02184200 0x200>;
767 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&clks IMX6SL_CLK_USBOH3>;
769 fsl,usbphy = <&usbphy2>;
770 fsl,usbmisc = <&usbmisc 1>;
771 ahb-burst-config = <0x0>;
772 tx-burst-size-dword = <0x10>;
773 rx-burst-size-dword = <0x10>;
774 status = "disabled";
775 };
776
777 usbh: usb@02184400 {
778 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
779 reg = <0x02184400 0x200>;
780 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&clks IMX6SL_CLK_USBOH3>;
782 fsl,usbmisc = <&usbmisc 2>;
783 dr_mode = "host";
784 ahb-burst-config = <0x0>;
785 tx-burst-size-dword = <0x10>;
786 rx-burst-size-dword = <0x10>;
787 status = "disabled";
788 };
789
790 usbmisc: usbmisc@02184800 {
791 #index-cells = <1>;
792 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
793 reg = <0x02184800 0x200>;
794 clocks = <&clks IMX6SL_CLK_USBOH3>;
795 };
796
797 fec: ethernet@02188000 {
798 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
799 reg = <0x02188000 0x4000>;
800 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&clks IMX6SL_CLK_ENET>,
802 <&clks IMX6SL_CLK_ENET_REF>;
803 clock-names = "ipg", "ahb";
804 status = "disabled";
805 };
806
807 usdhc1: usdhc@02190000 {
808 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
809 reg = <0x02190000 0x4000>;
810 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clks IMX6SL_CLK_USDHC1>,
812 <&clks IMX6SL_CLK_USDHC1>,
813 <&clks IMX6SL_CLK_USDHC1>;
814 clock-names = "ipg", "ahb", "per";
815 bus-width = <4>;
816 status = "disabled";
817 };
818
819 usdhc2: usdhc@02194000 {
820 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
821 reg = <0x02194000 0x4000>;
822 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&clks IMX6SL_CLK_USDHC2>,
824 <&clks IMX6SL_CLK_USDHC2>,
825 <&clks IMX6SL_CLK_USDHC2>;
826 clock-names = "ipg", "ahb", "per";
827 bus-width = <4>;
828 status = "disabled";
829 };
830
831 usdhc3: usdhc@02198000 {
832 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
833 reg = <0x02198000 0x4000>;
834 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clks IMX6SL_CLK_USDHC3>,
836 <&clks IMX6SL_CLK_USDHC3>,
837 <&clks IMX6SL_CLK_USDHC3>;
838 clock-names = "ipg", "ahb", "per";
839 bus-width = <4>;
840 status = "disabled";
841 };
842
843 usdhc4: usdhc@0219c000 {
844 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
845 reg = <0x0219c000 0x4000>;
846 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&clks IMX6SL_CLK_USDHC4>,
848 <&clks IMX6SL_CLK_USDHC4>,
849 <&clks IMX6SL_CLK_USDHC4>;
850 clock-names = "ipg", "ahb", "per";
851 bus-width = <4>;
852 status = "disabled";
853 };
854
855 i2c1: i2c@021a0000 {
856 #address-cells = <1>;
857 #size-cells = <0>;
858 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
859 reg = <0x021a0000 0x4000>;
860 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks IMX6SL_CLK_I2C1>;
862 status = "disabled";
863 };
864
865 i2c2: i2c@021a4000 {
866 #address-cells = <1>;
867 #size-cells = <0>;
868 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
869 reg = <0x021a4000 0x4000>;
870 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX6SL_CLK_I2C2>;
872 status = "disabled";
873 };
874
875 i2c3: i2c@021a8000 {
876 #address-cells = <1>;
877 #size-cells = <0>;
878 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
879 reg = <0x021a8000 0x4000>;
880 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&clks IMX6SL_CLK_I2C3>;
882 status = "disabled";
883 };
884
885 mmdc: mmdc@021b0000 {
886 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
887 reg = <0x021b0000 0x4000>;
888 };
889
890 rngb: rngb@021b4000 {
891 reg = <0x021b4000 0x4000>;
892 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
893 };
894
895 weim: weim@021b8000 {
896 reg = <0x021b8000 0x4000>;
897 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
898 };
899
900 ocotp: ocotp@021bc000 {
901 compatible = "fsl,imx6sl-ocotp", "syscon";
902 reg = <0x021bc000 0x4000>;
903 clocks = <&clks IMX6SL_CLK_OCOTP>;
904 };
905
906 audmux: audmux@021d8000 {
907 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
908 reg = <0x021d8000 0x4000>;
909 status = "disabled";
910 };
911 };
912 };
913 };
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