arch/arm/boot/dts/imx6ul-14x14-evk.dts

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/input/input.h>
  12 #include "imx6ul.dtsi"
  13
  14 / {
  15         model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
  16         compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
  17
  18         chosen {
  19                 stdout-path = &uart1;
  20         };
  21
  22         memory {
  23                 reg = <0x80000000 0x20000000>;
  24         };
  25
  26         regulators {
  27                 compatible = "simple-bus";
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 reg_sd1_vmmc: sd1_regulator {
  32                         compatible = "regulator-fixed";
  33                         regulator-name = "VSD_3V3";
  34                         regulator-min-microvolt = <3300000>;
  35                         regulator-max-microvolt = <3300000>;
  36                         gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  37                         enable-active-high;
  38                 };
  39         };
  40 };
  41
  42 &cpu0 {
  43         arm-supply = <&reg_arm>;
  44         soc-supply = <&reg_soc>;
  45 };
  46
  47 &fec1 {
  48         pinctrl-names = "default";
  49         pinctrl-0 = <&pinctrl_enet1>;
  50         phy-mode = "rmii";
  51         phy-handle = <&ethphy0>;
  52         status = "okay";
  53 };
  54
  55 &fec2 {
  56         pinctrl-names = "default";
  57         pinctrl-0 = <&pinctrl_enet2>;
  58         phy-mode = "rmii";
  59         phy-handle = <&ethphy1>;
  60         status = "okay";
  61
  62         mdio {
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65
  66                 ethphy0: ethernet-phy@2 {
  67                         reg = <2>;
  68                 };
  69
  70                 ethphy1: ethernet-phy@1 {
  71                         reg = <1>;
  72                 };
  73         };
  74 };
  75
  76 &qspi {
  77         pinctrl-names = "default";
  78         pinctrl-0 = <&pinctrl_qspi>;
  79         status = "okay";
  80
  81         flash0: n25q256a@0 {
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 compatible = "micron,n25q256a";
  85                 spi-max-frequency = <29000000>;
  86                 reg = <0>;
  87         };
  88 };
  89
  90 &snvs_poweroff {
  91         status = "okay";
  92 };
  93
  94 &uart1 {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_uart1>;
  97         status = "okay";
  98 };
  99
 100 &uart2 {
 101         pinctrl-names = "default";
 102         pinctrl-0 = <&pinctrl_uart2>;
 103         fsl,uart-has-rtscts;
 104         status = "okay";
 105 };
 106
 107 &usbotg1 {
 108         dr_mode = "peripheral";
 109         status = "okay";
 110 };
 111
 112 &usbotg2 {
 113         dr_mode = "host";
 114         disable-over-current;
 115         status = "okay";
 116 };
 117
 118 &usdhc1 {
 119         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 120         pinctrl-0 = <&pinctrl_usdhc1>;
 121         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 122         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 123         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 124         keep-power-in-suspend;
 125         enable-sdio-wakeup;
 126         vmmc-supply = <&reg_sd1_vmmc>;
 127         status = "okay";
 128 };
 129
 130 &usdhc2 {
 131         pinctrl-names = "default";
 132         pinctrl-0 = <&pinctrl_usdhc2>;
 133         no-1-8-v;
 134         keep-power-in-suspend;
 135         enable-sdio-wakeup;
 136         status = "okay";
 137 };
 138
 139 &iomuxc {
 140         pinctrl-names = "default";
 141
 142         pinctrl_csi1: csi1grp {
 143                 fsl,pins = <
 144                         MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
 145                         MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
 146                         MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
 147                         MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
 148                         MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
 149                         MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
 150                         MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
 151                         MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
 152                         MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
 153                         MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
 154                         MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
 155                         MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
 156                 >;
 157         };
 158
 159         pinctrl_enet1: enet1grp {
 160                 fsl,pins = <
 161                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 162                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 163                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 164                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 165                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 166                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 167                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 168                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 169                 >;
 170         };
 171
 172         pinctrl_enet2: enet2grp {
 173                 fsl,pins = <
 174                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 175                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 176                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 177                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 178                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 179                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 180                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 181                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 182                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 183                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 184                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x17059
 185                 >;
 186         };
 187
 188         pinctrl_flexcan1: flexcan1grp{
 189                 fsl,pins = <
 190                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 191                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 192                 >;
 193         };
 194
 195         pinctrl_flexcan2: flexcan2grp{
 196                 fsl,pins = <
 197                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 198                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 199                 >;
 200         };
 201
 202         pinctrl_i2c1: i2c1grp {
 203                 fsl,pins = <
 204                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 205                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 206                 >;
 207         };
 208
 209         pinctrl_i2c2: i2c2grp {
 210                 fsl,pins = <
 211                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 212                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 213                 >;
 214         };
 215
 216         pinctrl_lcdif_dat: lcdifdatgrp {
 217                 fsl,pins = <
 218                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 219                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 220                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 221                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 222                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 223                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 224                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 225                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 226                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 227                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 228                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 229                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 230                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 231                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 232                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 233                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 234                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 235                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 236                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
 237                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
 238                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
 239                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
 240                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
 241                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
 242                 >;
 243         };
 244
 245         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 246                 fsl,pins = <
 247                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 248                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 249                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 250                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 251                         /* used for lcd reset */
 252                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
 253                 >;
 254         };
 255
 256         pinctrl_qspi: qspigrp {
 257                 fsl,pins = <
 258                         MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
 259                         MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
 260                         MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
 261                         MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
 262                         MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
 263                         MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
 264                 >;
 265         };
 266
 267         pinctrl_pwm1: pwm1grp {
 268                 fsl,pins = <
 269                         MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
 270                 >;
 271         };
 272
 273         pinctrl_sim2: sim2grp {
 274                 fsl,pins = <
 275                         MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
 276                         MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
 277                         MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
 278                         MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
 279                         MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
 280                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
 281                 >;
 282         };
 283
 284         pinctrl_uart1: uart1grp {
 285                 fsl,pins = <
 286                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 287                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 288                 >;
 289         };
 290
 291         pinctrl_uart2: uart2grp {
 292                 fsl,pins = <
 293                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 294                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 295                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 296                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 297                 >;
 298         };
 299
 300         pinctrl_usdhc1: usdhc1grp {
 301                 fsl,pins = <
 302                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 303                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 304                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 305                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 306                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 307                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 308                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
 309                         MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
 310                         MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
 311                 >;
 312         };
 313
 314         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 315                 fsl,pins = <
 316                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 317                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 318                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 319                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 320                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 321                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 322
 323                 >;
 324         };
 325
 326         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 327                 fsl,pins = <
 328                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 329                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 330                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 331                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 332                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 333                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 334                 >;
 335         };
 336
 337         pinctrl_usdhc2: usdhc2grp {
 338                 fsl,pins = <
 339                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
 340                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
 341                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
 342                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
 343                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
 344                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 345                 >;
 346         };
 347 };