1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright (C) 2016 Amarula Solutions B.V.
4 * Copyright (C) 2016 Engicam S.r.l.
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
13 reg = <0x80000000 0x20000000>;
21 compatible = "pwm-backlight";
22 pwms = <&pwm8 0 100000>;
23 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
24 10 11 12 13 14 15 16 17 18 19
25 20 21 22 23 24 25 26 27 28 29
26 30 31 32 33 34 35 36 37 38 39
27 40 41 42 43 44 45 46 47 48 49
28 50 51 52 53 54 55 56 57 58 59
29 60 61 62 63 64 65 66 67 68 69
30 70 71 72 73 74 75 76 77 78 79
31 80 81 82 83 84 85 86 87 88 89
32 90 91 92 93 94 95 96 97 98 99
34 default-brightness-level = <100>;
37 reg_1p8v: regulator-1p8v {
38 compatible = "regulator-fixed";
39 regulator-name = "1P8V";
40 regulator-min-microvolt = <1800000>;
41 regulator-max-microvolt = <1800000>;
46 reg_3p3v: regulator-3p3v {
47 compatible = "regulator-fixed";
48 regulator-name = "3P3V";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
56 compatible = "simple-audio-card";
57 simple-audio-card,name = "imx6ul-isiot-sgtl5000";
58 simple-audio-card,format = "i2s";
59 simple-audio-card,bitclock-master = <&dailink_master>;
60 simple-audio-card,frame-master = <&dailink_master>;
61 simple-audio-card,widgets =
62 "Microphone", "Mic Jack",
65 "Headphone", "Headphone Jack";
66 simple-audio-card,routing =
68 "Mic Jack", "Mic Bias",
69 "Headphone Jack", "HP_OUT";
71 simple-audio-card,cpu {
75 dailink_master: simple-audio-card,codec {
76 sound-dai = <&sgtl5000>;
77 clocks = <&clks IMX6UL_CLK_SAI2>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_enet1>;
86 phy-handle = <ðphy0>;
93 ethphy0: ethernet-phy@0 {
94 compatible = "ethernet-phy-ieee802.3-c22";
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_gpmi_nand>;
108 clock-frequency = <100000>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_i2c1>;
114 compatible = "fsl,sgtl5000";
116 #sound-dai-cells = <0>;
117 clocks = <&clks IMX6UL_CLK_OSC>;
118 clock-names = "mclk";
119 VDDA-supply = <®_3p3v>;
120 VDDIO-supply = <®_3p3v>;
121 VDDD-supply = <®_1p8v>;
124 stmpe811: gpio-expander@44 {
125 compatible = "st,stmpe811";
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_stmpe>;
129 interrupt-parent = <&gpio1>;
130 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
135 compatible = "st,stmpe-ts";
136 st,sample-time = <4>;
141 st,touch-det-delay = <2>;
150 clock_frequency = <100000>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_i2c2>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_lcdif_dat
159 &pinctrl_lcdif_ctrl>;
160 display = <&display0>;
164 bits-per-pixel = <16>;
168 native-mode = <&timing0>;
170 clock-frequency = <28000000>;
182 pixelclk-active = <0>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_pwm8>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_sai2>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_uart1>;
207 pinctrl-names = "default", "state_100mhz", "state_200mhz";
208 pinctrl-0 = <&pinctrl_usdhc1>;
209 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
210 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
211 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_usdhc2>;
220 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
227 pinctrl_enet1: enet1grp {
229 MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
230 MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
231 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
232 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
233 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
234 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
235 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
236 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
237 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
238 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
242 pinctrl_gpmi_nand: gpminandgrp {
244 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
245 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
246 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
247 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
248 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
249 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
250 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
251 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
252 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
253 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
254 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
255 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
256 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
257 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
258 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
262 pinctrl_i2c1: i2c1grp {
264 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
265 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
269 pinctrl_i2c2: i2c2grp {
271 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
272 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
276 pinctrl_lcdif_ctrl: lcdifctrlgrp {
278 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
279 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
280 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
281 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
285 pinctrl_lcdif_dat: lcdifdatgrp {
287 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
288 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
289 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
290 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
291 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
292 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
293 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
294 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
295 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
296 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
297 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
298 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
299 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
300 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
301 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
302 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
303 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
304 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
308 pinctrl_pwm8: pwm8grp {
310 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
314 pinctrl_sai2: sai2grp {
316 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
317 MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
318 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
319 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
320 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
324 pinctrl_stmpe: stmpegrp {
326 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
330 pinctrl_uart1: uart1grp {
332 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
333 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
337 pinctrl_usdhc1: usdhc1grp {
339 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
340 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
341 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
342 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
343 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
344 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
348 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
350 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
351 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
352 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
353 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
354 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
355 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
359 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
361 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
362 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
363 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
364 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
365 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
366 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
370 pinctrl_usdhc2: usdhc2grp {
372 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
373 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
374 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
375 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
376 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
377 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
378 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
379 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
380 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
381 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
382 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070