arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
   4  * Author: Christian Hemp <c.hemp@phytec.de>
   5  */
   6
   7 / {
   8         model = "Phytec phyBOARD-Segin i.MX6 UltraLite";
   9         compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
  10
  11         aliases {
  12                 rtc0 = &i2c_rtc;
  13                 rtc1 = &snvs_rtc;
  14         };
  15
  16         reg_sound_1v8: regulator-1v8 {
  17                 compatible = "regulator-fixed";
  18                 regulator-name = "i2s-audio-1v8";
  19                 regulator-min-microvolt = <1800000>;
  20                 regulator-max-microvolt = <1800000>;
  21                 status = "disabled";
  22         };
  23
  24         reg_sound_3v3: regulator-3v3 {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "i2s-audio-3v3";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29                 status = "disabled";
  30         };
  31
  32         reg_can1_en: regulator-can1 {
  33                 compatible = "regulator-fixed";
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&princtrl_flexcan1_en>;
  36                 regulator-name = "Can";
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39                 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  40                 enable-active-high;
  41                 status = "disabled";
  42         };
  43
  44         reg_adc1_vref_3v3: regulator-vref-3v3 {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "vref-3v3";
  47                 regulator-min-microvolt = <3300000>;
  48                 regulator-max-microvolt = <3300000>;
  49         };
  50
  51         sound: sound {
  52                 compatible = "simple-audio-card";
  53                 simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
  54                 simple-audio-card,format = "i2s";
  55                 simple-audio-card,bitclock-master = <&dailink_master>;
  56                 simple-audio-card,frame-master = <&dailink_master>;
  57                 simple-audio-card,widgets =
  58                         "Line", "Line In",
  59                         "Line", "Line Out",
  60                         "Speaker", "Speaker";
  61                 simple-audio-card,routing =
  62                         "Line Out", "LLOUT",
  63                         "Line Out", "RLOUT",
  64                         "Speaker", "SPOP",
  65                         "Speaker", "SPOM",
  66                         "LINE1L", "Line In",
  67                         "LINE1R", "Line In";
  68                 status = "disabled";
  69
  70                 simple-audio-card,cpu {
  71                         sound-dai = <&sai2>;
  72                 };
  73
  74                 dailink_master: simple-audio-card,codec {
  75                         sound-dai = <&tlv320>;
  76                         clocks = <&clks IMX6UL_CLK_SAI2>;
  77                 };
  78         };
  79
  80 };
  81
  82 &adc1 {
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_adc1>;
  85         vref-supply = <&reg_adc1_vref_3v3>;
  86         /*
  87          * driver can not separate a specific channel so we request 4 channels
  88          * here - we need only the fourth channel
  89          */
  90         num-channels = <4>;
  91         status = "disabled";
  92 };
  93
  94 &can1 {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_flexcan1>;
  97         xceiver-supply = <&reg_can1_en>;
  98         status = "disabled";
  99 };
 100
 101 &clks {
 102         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 103         assigned-clock-rates = <786432000>;
 104 };
 105
 106 &fec2 {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_enet2>;
 109         phy-mode = "rmii";
 110         phy-handle = <&ethphy1>;
 111         status = "disabled";
 112 };
 113
 114 &i2c1 {
 115         tlv320: codec@18 {
 116                 compatible = "ti,tlv320aic3007";
 117                 #sound-dai-cells = <0>;
 118                 reg = <0x18>;
 119                 AVDD-supply = <&reg_sound_3v3>;
 120                 IOVDD-supply = <&reg_sound_3v3>;
 121                 DRVDD-supply = <&reg_sound_3v3>;
 122                 DVDD-supply = <&reg_sound_1v8>;
 123                 status = "disabled";
 124         };
 125
 126         stmpe: touchscreen@44 {
 127                 compatible = "st,stmpe811";
 128                 reg = <0x44>;
 129                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 130                 interrupt-parent = <&gpio5>;
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&pinctrl_stmpe>;
 133                 status = "disabled";
 134
 135                 touchscreen {
 136                         compatible = "st,stmpe-ts";
 137                         st,sample-time = <4>;
 138                         st,mod-12b = <1>;
 139                         st,ref-sel = <0>;
 140                         st,adc-freq = <1>;
 141                         st,ave-ctrl = <1>;
 142                         st,touch-det-delay = <2>;
 143                         st,settling = <2>;
 144                         st,fraction-z = <7>;
 145                         st,i-drive = <1>;
 146                         touchscreen-inverted-x = <1>;
 147                         touchscreen-inverted-y = <1>;
 148                 };
 149         };
 150
 151         i2c_rtc: rtc@68 {
 152                 pinctrl-names = "default";
 153                 pinctrl-0 = <&pinctrl_rtc_int>;
 154                 compatible = "microcrystal,rv4162";
 155                 reg = <0x68>;
 156                 interrupt-parent = <&gpio5>;
 157                 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
 158                 status = "disabled";
 159         };
 160 };
 161
 162 &mdio {
 163         ethphy1: ethernet-phy@2 {
 164                 reg = <2>;
 165                 micrel,led-mode = <1>;
 166                 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
 167                 clock-names = "rmii-ref";
 168         };
 169 };
 170
 171 &pwm3 {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_pwm3>;
 174         status = "disabled";
 175 };
 176
 177 &sai2 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_sai2>;
 180         assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
 181                         <&clks IMX6UL_CLK_SAI2>;
 182         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 183         assigned-clock-rates = <0>, <19200000>;
 184         fsl,sai-mclk-direction-output;
 185         status = "disabled";
 186 };
 187
 188 &uart5 {
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_uart5>;
 191         uart-has-rtscts;
 192         status = "disabled";
 193 };
 194
 195 &usbotg1 {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 198         dr_mode = "otg";
 199         status = "disabled";
 200 };
 201
 202 &usbotg2 {
 203         dr_mode = "host";
 204         disable-over-current;
 205         status = "disabled";
 206 };
 207
 208 &usdhc1 {
 209         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 210         pinctrl-0 = <&pinctrl_usdhc1>;
 211         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 212         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 213         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 214         no-1-8-v;
 215         keep-power-in-suspend;
 216         wakeup-source;
 217         status = "disabled";
 218 };
 219
 220 &iomuxc {
 221         pinctrl_adc1: adc1grp {
 222                 fsl,pins = <
 223                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
 224                 >;
 225         };
 226
 227         pinctrl_enet2: enet2grp {
 228                 fsl,pins = <
 229                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 230                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 231                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 232                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 233                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 234                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 235                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 236                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 237                 >;
 238         };
 239
 240         pinctrl_flexcan1: flexcan1 {
 241                 fsl,pins = <
 242                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
 243                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x0b0b0
 244                 >;
 245         };
 246
 247         princtrl_flexcan1_en: flexcan1engrp {
 248                 fsl,pins = <
 249                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x17059
 250                 >;
 251         };
 252
 253         pinctrl_pwm3: pwm3grp {
 254                 fsl,pins = <
 255                         MX6UL_PAD_GPIO1_IO04__PWM3_OUT  0x0b0b0
 256                 >;
 257         };
 258
 259         pinctrl_rtc_int: rtcintgrp {
 260                 fsl,pins = <
 261                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x17059
 262                 >;
 263         };
 264
 265         pinctrl_sai2: sai2grp {
 266                 fsl,pins = <
 267                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 268                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 269                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
 270                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
 271                         MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
 272                 >;
 273         };
 274
 275         pinctrl_stmpe: stmpegrp {
 276                 fsl,pins = <
 277                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x17059
 278                 >;
 279         };
 280
 281         pinctrl_uart5: uart5grp {
 282                 fsl,pins = <
 283                         MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
 284                         MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
 285                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x1b0b1
 286                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x1b0b1
 287                 >;
 288         };
 289
 290         pinctrl_usb_otg1_id: usbotg1idgrp {
 291                 fsl,pins = <
 292                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
 293                 >;
 294         };
 295
 296         pinctrl_usdhc1: usdhc1grp {
 297                 fsl,pins = <
 298                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 299                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 300                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 301                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 302                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 303                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 304                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059
 305                 >;
 306         };
 307
 308         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 309                 fsl,pins = <
 310                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170b9
 311                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100b9
 312                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
 313                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
 314                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
 315                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
 316                 >;
 317         };
 318
 319         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 320                 fsl,pins = <
 321                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170f9
 322                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100f9
 323                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170f9
 324                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170f9
 325                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170f9
 326                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170f9
 327                 >;
 328         };
 329 };