arch/arm/boot/dts/imx7d-nitrogen7.dts

   1 // SPDX-License-Identifier: GPL-2.0 OR X11
   2 /*
   3  * Copyright 2016 Boundary Devices, Inc.
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx7d.dtsi"
   9
  10 / {
  11         model = "Boundary Devices i.MX7 Nitrogen7 Board";
  12         compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
  13
  14         memory@80000000 {
  15                 reg = <0x80000000 0x40000000>;
  16         };
  17
  18         backlight-j9 {
  19                 compatible = "gpio-backlight";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_backlight_j9>;
  22                 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  23                 default-on;
  24         };
  25
  26         backlight_lcd: backlight-j20 {
  27                 compatible = "pwm-backlight";
  28                 pwms = <&pwm1 0 5000000 0>;
  29                 brightness-levels = <0 4 8 16 32 64 128 255>;
  30                 default-brightness-level = <6>;
  31                 status = "okay";
  32         };
  33
  34         panel-lcd {
  35                 compatible = "okaya,rs800480t-7x0gp";
  36                 backlight = <&backlight_lcd>;
  37
  38                 port {
  39                         panel_in: endpoint {
  40                                 remote-endpoint = <&lcdif_out>;
  41                         };
  42                 };
  43         };
  44
  45         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "usb_otg1_vbus";
  48                 regulator-min-microvolt = <5000000>;
  49                 regulator-max-microvolt = <5000000>;
  50                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  51                 enable-active-high;
  52         };
  53
  54         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  55                 compatible = "regulator-fixed";
  56                 regulator-name = "usb_otg2_vbus";
  57                 regulator-min-microvolt = <5000000>;
  58                 regulator-max-microvolt = <5000000>;
  59                 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  60                 enable-active-high;
  61         };
  62
  63         reg_can2_3v3: regulator-can2-3v3 {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "can2-3v3";
  66                 regulator-min-microvolt = <3300000>;
  67                 regulator-max-microvolt = <3300000>;
  68                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
  69         };
  70
  71         reg_vref_1v8: regulator-vref-1v8 {
  72                 compatible = "regulator-fixed";
  73                 regulator-name = "vref-1v8";
  74                 regulator-min-microvolt = <1800000>;
  75                 regulator-max-microvolt = <1800000>;
  76         };
  77
  78         reg_vref_3v3: regulator-vref-3v3 {
  79                 compatible = "regulator-fixed";
  80                 regulator-name = "vref-3v3";
  81                 regulator-min-microvolt = <3300000>;
  82                 regulator-max-microvolt = <3300000>;
  83         };
  84
  85         reg_wlan: regulator-wlan {
  86                 compatible = "regulator-fixed";
  87                 regulator-min-microvolt = <3300000>;
  88                 regulator-max-microvolt = <3300000>;
  89                 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
  90                 clock-names = "slow";
  91                 regulator-name = "reg_wlan";
  92                 startup-delay-us = <70000>;
  93                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  94                 enable-active-high;
  95         };
  96 };
  97
  98 &adc1 {
  99         vref-supply = <&reg_vref_1v8>;
 100         status = "okay";
 101 };
 102
 103 &adc2 {
 104         vref-supply = <&reg_vref_1v8>;
 105         status = "okay";
 106 };
 107
 108 &clks {
 109         assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
 110                           <&clks IMX7D_CLKO2_ROOT_DIV>;
 111         assigned-clock-parents = <&clks IMX7D_CKIL>;
 112         assigned-clock-rates = <0>, <32768>;
 113 };
 114
 115 &cpu0 {
 116         cpu-supply = <&sw1a_reg>;
 117 };
 118
 119 &fec1 {
 120         pinctrl-names = "default";
 121         pinctrl-0 = <&pinctrl_enet1>;
 122         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 123                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 124         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 125         assigned-clock-rates = <0>, <100000000>;
 126         phy-mode = "rgmii";
 127         phy-handle = <&ethphy0>;
 128         fsl,magic-packet;
 129         status = "okay";
 130
 131         mdio {
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134
 135                 ethphy0: ethernet-phy@4 {
 136                         reg = <4>;
 137                 };
 138         };
 139 };
 140
 141 &flexcan2 {
 142         pinctrl-names = "default";
 143         pinctrl-0 = <&pinctrl_flexcan2>;
 144         xceiver-supply = <&reg_can2_3v3>;
 145         status = "okay";
 146 };
 147
 148 &i2c1 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_i2c1>;
 151         status = "okay";
 152
 153         pmic: pfuze3000@8 {
 154                 compatible = "fsl,pfuze3000";
 155                 reg = <0x08>;
 156
 157                 regulators {
 158                         sw1a_reg: sw1a {
 159                                 regulator-min-microvolt = <700000>;
 160                                 regulator-max-microvolt = <1475000>;
 161                                 regulator-boot-on;
 162                                 regulator-always-on;
 163                                 regulator-ramp-delay = <6250>;
 164                         };
 165
 166                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 167                         sw1c_reg: sw1b {
 168                                 regulator-min-microvolt = <700000>;
 169                                 regulator-max-microvolt = <1475000>;
 170                                 regulator-boot-on;
 171                                 regulator-always-on;
 172                                 regulator-ramp-delay = <6250>;
 173                         };
 174
 175                         sw2_reg: sw2 {
 176                                 regulator-min-microvolt = <1500000>;
 177                                 regulator-max-microvolt = <1850000>;
 178                                 regulator-boot-on;
 179                                 regulator-always-on;
 180                         };
 181
 182                         sw3a_reg: sw3 {
 183                                 regulator-min-microvolt = <900000>;
 184                                 regulator-max-microvolt = <1650000>;
 185                                 regulator-boot-on;
 186                                 regulator-always-on;
 187                         };
 188
 189                         swbst_reg: swbst {
 190                                 regulator-min-microvolt = <5000000>;
 191                                 regulator-max-microvolt = <5150000>;
 192                         };
 193
 194                         snvs_reg: vsnvs {
 195                                 regulator-min-microvolt = <1000000>;
 196                                 regulator-max-microvolt = <3000000>;
 197                                 regulator-boot-on;
 198                                 regulator-always-on;
 199                         };
 200
 201                         vref_reg: vrefddr {
 202                                 regulator-boot-on;
 203                                 regulator-always-on;
 204                         };
 205
 206                         vgen1_reg: vldo1 {
 207                                 regulator-min-microvolt = <1800000>;
 208                                 regulator-max-microvolt = <3300000>;
 209                                 regulator-always-on;
 210                         };
 211
 212                         vgen2_reg: vldo2 {
 213                                 regulator-min-microvolt = <800000>;
 214                                 regulator-max-microvolt = <1550000>;
 215                                 regulator-always-on;
 216                         };
 217
 218                         vgen3_reg: vccsd {
 219                                 regulator-min-microvolt = <2850000>;
 220                                 regulator-max-microvolt = <3300000>;
 221                                 regulator-always-on;
 222                         };
 223
 224                         vgen4_reg: v33 {
 225                                 regulator-min-microvolt = <2850000>;
 226                                 regulator-max-microvolt = <3300000>;
 227                                 regulator-always-on;
 228                         };
 229
 230                         vgen5_reg: vldo3 {
 231                                 regulator-min-microvolt = <1800000>;
 232                                 regulator-max-microvolt = <3300000>;
 233                                 regulator-always-on;
 234                         };
 235
 236                         vgen6_reg: vldo4 {
 237                                 regulator-min-microvolt = <1800000>;
 238                                 regulator-max-microvolt = <3300000>;
 239                                 regulator-always-on;
 240                         };
 241                 };
 242         };
 243 };
 244
 245 &i2c2 {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_i2c2>;
 248         status = "okay";
 249
 250         rtc@68 {
 251                 compatible = "microcrystal,rv4162";
 252                 pinctrl-names = "default";
 253                 pinctrl-0 = <&pinctrl_i2c2_rv4162>;
 254                 reg = <0x68>;
 255                 interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
 256         };
 257 };
 258
 259 &i2c3 {
 260         pinctrl-names = "default";
 261         pinctrl-0 = <&pinctrl_i2c3>;
 262         status = "okay";
 263
 264         touch@48 {
 265                 compatible = "ti,tsc2004";
 266                 reg = <0x48>;
 267                 pinctrl-names = "default";
 268                 pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
 269                 interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
 270                 wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
 271         };
 272 };
 273
 274 &i2c4 {
 275         pinctrl-names = "default";
 276         pinctrl-0 = <&pinctrl_i2c4>;
 277         status = "okay";
 278
 279         codec: wm8960@1a {
 280                 compatible = "wlf,wm8960";
 281                 reg = <0x1a>;
 282                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 283                 clock-names = "mclk";
 284                 wlf,shared-lrclk;
 285         };
 286 };
 287
 288 &lcdif {
 289         status = "okay";
 290
 291         port {
 292                 lcdif_out: endpoint {
 293                         remote-endpoint = <&panel_in>;
 294                 };
 295         };
 296 };
 297
 298 &pwm1 {
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&pinctrl_pwm1>;
 301         status = "okay";
 302 };
 303
 304 &pwm2 {
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&pinctrl_pwm2>;
 307         status = "okay";
 308 };
 309
 310 &uart1 {
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&pinctrl_uart1>;
 313         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 314         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 315         status = "okay";
 316 };
 317
 318 &uart2 {
 319         pinctrl-names = "default";
 320         pinctrl-0 = <&pinctrl_uart2>;
 321         assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
 322         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 323         status = "okay";
 324 };
 325
 326 &uart3 {
 327         pinctrl-names = "default";
 328         pinctrl-0 = <&pinctrl_uart3>;
 329         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 330         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 331         status = "okay";
 332 };
 333
 334 &uart6 {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_uart6>;
 337         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 338         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 339         uart-has-rtscts;
 340         status = "okay";
 341 };
 342
 343 &usbotg1 {
 344         vbus-supply = <&reg_usb_otg1_vbus>;
 345         pinctrl-names = "default";
 346         pinctrl-0 = <&pinctrl_usbotg1>;
 347         status = "okay";
 348 };
 349
 350 &usbotg2 {
 351         vbus-supply = <&reg_usb_otg2_vbus>;
 352         pinctrl-names = "default";
 353         pinctrl-0 = <&pinctrl_usbotg2>;
 354         dr_mode = "host";
 355         status = "okay";
 356 };
 357
 358 &usdhc1 {
 359         pinctrl-names = "default";
 360         pinctrl-0 = <&pinctrl_usdhc1>;
 361         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 362         vmmc-supply = <&vgen3_reg>;
 363         bus-width = <4>;
 364         fsl,tuning-step = <2>;
 365         wakeup-source;
 366         keep-power-in-suspend;
 367         status = "okay";
 368 };
 369
 370 &usdhc2 {
 371         #address-cells = <1>;
 372         #size-cells = <0>;
 373         pinctrl-names = "default";
 374         pinctrl-0 = <&pinctrl_usdhc2>;
 375         bus-width = <4>;
 376         non-removable;
 377         vmmc-supply = <&reg_wlan>;
 378         cap-power-off-card;
 379         keep-power-in-suspend;
 380         status = "okay";
 381
 382         wlcore: wlcore@2 {
 383                 compatible = "ti,wl1271";
 384                 reg = <2>;
 385                 interrupt-parent = <&gpio4>;
 386                 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 387                 ref-clock-frequency = <38400000>;
 388         };
 389 };
 390
 391 &usdhc3 {
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_usdhc3>;
 394         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 395         assigned-clock-rates = <400000000>;
 396         bus-width = <8>;
 397         fsl,tuning-step = <2>;
 398         non-removable;
 399         status = "okay";
 400 };
 401
 402 &wdog1 {
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&pinctrl_wdog1>;
 405         status = "okay";
 406 };
 407
 408 &iomuxc {
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
 411
 412         pinctrl_hog_1: hoggrp-1 {
 413                 fsl,pins = <
 414                         MX7D_PAD_SD3_RESET_B__GPIO6_IO11        0x5d
 415                         MX7D_PAD_GPIO1_IO13__GPIO1_IO13         0x7d
 416                         MX7D_PAD_ECSPI2_MISO__GPIO4_IO22        0x7d
 417                 >;
 418         };
 419
 420         pinctrl_enet1: enet1grp {
 421                 fsl,pins = <
 422                         MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 423                         MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 424                         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1          0x3
 425                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x71
 426                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x71
 427                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x71
 428                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x71
 429                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x71
 430                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
 431                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x71
 432                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x11
 433                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x11
 434                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x11
 435                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x71
 436                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
 437                         MX7D_PAD_SD3_STROBE__GPIO6_IO10                 0x75
 438                 >;
 439         };
 440
 441         pinctrl_flexcan2: flexcan2grp {
 442                 fsl,pins = <
 443                         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x7d
 444                         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x7d
 445                         MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x7d
 446                 >;
 447         };
 448
 449         pinctrl_i2c1: i2c1grp {
 450                 fsl,pins = <
 451                         MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 452                         MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 453                 >;
 454         };
 455
 456         pinctrl_i2c2: i2c2grp {
 457                 fsl,pins = <
 458                         MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 459                         MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 460                 >;
 461         };
 462
 463         pinctrl_i2c2_rv4162: i2c2-rv4162grp {
 464                 fsl,pins = <
 465                         MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x7d
 466                 >;
 467         };
 468
 469         pinctrl_i2c3: i2c3grp {
 470                 fsl,pins = <
 471                         MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 472                         MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 473                 >;
 474         };
 475
 476         pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
 477                 fsl,pins = <
 478                         MX7D_PAD_LCD_RESET__GPIO3_IO4           0x79
 479                         MX7D_PAD_SD2_WP__GPIO5_IO10             0x7d
 480                 >;
 481         };
 482
 483         pinctrl_i2c4: i2c4grp {
 484                 fsl,pins = <
 485                         MX7D_PAD_I2C4_SDA__I2C4_SDA             0x4000007f
 486                         MX7D_PAD_I2C4_SCL__I2C4_SCL             0x4000007f
 487                 >;
 488         };
 489
 490         pinctrl_j2: j2grp {
 491                 fsl,pins = <
 492                         MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15       0x7d
 493                         MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x7d
 494                         MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12       0x7d
 495                         MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x7d
 496                         MX7D_PAD_SD1_WP__GPIO5_IO1              0x7d
 497                         MX7D_PAD_EPDC_SDSHR__GPIO2_IO19         0x7d
 498                         MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x7d
 499                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x7d
 500                         MX7D_PAD_EPDC_DATA07__GPIO2_IO7         0x7d
 501                         MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x7d
 502                         MX7D_PAD_EPDC_DATA09__GPIO2_IO9         0x7d
 503                         MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x7d
 504                         MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x7d
 505                         MX7D_PAD_EPDC_DATA12__GPIO2_IO12        0x7d
 506                         MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14       0x7d
 507                         MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x7d
 508                         MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13       0x7d
 509                         MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x7d
 510                         MX7D_PAD_EPDC_GDCLK__GPIO2_IO24         0x7d
 511                         MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21       0x7d
 512                         MX7D_PAD_EPDC_GDOE__GPIO2_IO25          0x7d
 513                         MX7D_PAD_EPDC_GDRL__GPIO2_IO26          0x7d
 514                         MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22       0x7d
 515                         MX7D_PAD_EPDC_SDCE0__GPIO2_IO20         0x7d
 516                         MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20       0x7d
 517                         MX7D_PAD_EPDC_SDCE1__GPIO2_IO21         0x7d
 518                         MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19       0x7d
 519                         MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x7d
 520                         MX7D_PAD_EPDC_SDCE3__GPIO2_IO23         0x7d
 521                         MX7D_PAD_EPDC_GDSP__GPIO2_IO27          0x7d
 522                         MX7D_PAD_EPDC_SDCLK__GPIO2_IO16         0x7d
 523                         MX7D_PAD_EPDC_SDLE__GPIO2_IO17          0x7d
 524                         MX7D_PAD_EPDC_SDOE__GPIO2_IO18          0x7d
 525                         MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x7d
 526                         MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x7d
 527                 >;
 528         };
 529
 530         pinctrl_lcdif_dat: lcdifdatgrp {
 531                 fsl,pins = <
 532                         MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 533                         MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 534                         MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 535                         MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 536                         MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 537                         MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 538                         MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 539                         MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 540                         MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 541                         MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 542                         MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 543                         MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 544                         MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 545                         MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 546                         MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 547                         MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 548                         MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 549                         MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 550                         MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 551                         MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 552                         MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 553                         MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 554                         MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 555                         MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 556                 >;
 557         };
 558
 559         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 560                 fsl,pins = <
 561                         MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 562                         MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 563                         MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 564                         MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 565                 >;
 566         };
 567
 568         pinctrl_pwm2: pwm2grp {
 569                 fsl,pins = <
 570                         MX7D_PAD_GPIO1_IO09__PWM2_OUT           0x7d
 571                 >;
 572         };
 573
 574         pinctrl_uart1: uart1grp {
 575                 fsl,pins = <
 576                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 577                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 578                 >;
 579         };
 580
 581         pinctrl_uart2: uart2grp {
 582                 fsl,pins = <
 583                         MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX    0x79
 584                         MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX    0x79
 585                 >;
 586         };
 587
 588         pinctrl_uart3: uart3grp {
 589                 fsl,pins = <
 590                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
 591                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
 592                         MX7D_PAD_EPDC_DATA04__GPIO2_IO4         0x7d
 593                 >;
 594         };
 595
 596         pinctrl_uart6: uart6grp {
 597                 fsl,pins = <
 598                         MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 599                         MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 600                         MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 601                         MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 602                 >;
 603         };
 604
 605         pinctrl_usbotg2: usbotg2grp {
 606                 fsl,pins = <
 607                         MX7D_PAD_UART3_RTS_B__USB_OTG2_OC       0x7d
 608                         MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 609                 >;
 610         };
 611
 612         pinctrl_usdhc1: usdhc1grp {
 613                 fsl,pins = <
 614                         MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 615                         MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 616                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 617                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 618                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 619                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 620                         MX7D_PAD_GPIO1_IO08__SD1_VSELECT        0x75
 621                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x75
 622                 >;
 623         };
 624
 625         pinctrl_usdhc2: usdhc2grp {
 626                 fsl,pins = <
 627                         MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 628                         MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 629                         MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 630                         MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 631                         MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 632                         MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 633                         MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20        0x59
 634                         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x59
 635                 >;
 636         };
 637
 638         pinctrl_usdhc3: usdhc3grp {
 639                 fsl,pins = <
 640                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 641                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 642                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 643                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 644                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 645                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 646                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 647                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 648                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 649                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 650                 >;
 651         };
 652 };
 653
 654 &iomuxc_lpsr {
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&pinctrl_hog_2>;
 657
 658         pinctrl_hog_2: hoggrp-2 {
 659                 fsl,pins = <
 660                         MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2     0x7d
 661                         MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2     0x7d
 662                 >;
 663         };
 664
 665         pinctrl_backlight_j9: backlightj9grp {
 666                 fsl,pins = <
 667                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7     0x7d
 668                 >;
 669         };
 670
 671         pinctrl_pwm1: pwm1grp {
 672                 fsl,pins = <
 673                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT      0x7d
 674                 >;
 675         };
 676
 677         pinctrl_usbotg1: usbotg1grp {
 678                 fsl,pins = <
 679                         MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC   0x7d
 680                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x14
 681                 >;
 682         };
 683
 684         pinctrl_wdog1: wdog1grp {
 685                 fsl,pins = <
 686                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x75
 687                 >;
 688         };
 689 };