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ARM: dts: imx7d.dtsi: add ADC support
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / imx7d.dtsi
1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/clock/imx7d-clock.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include "imx7d-pinfunc.h"
47 #include "skeleton.dtsi"
48
49 / {
50 aliases {
51 gpio0 = &gpio1;
52 gpio1 = &gpio2;
53 gpio2 = &gpio3;
54 gpio3 = &gpio4;
55 gpio4 = &gpio5;
56 gpio5 = &gpio6;
57 gpio6 = &gpio7;
58 i2c0 = &i2c1;
59 i2c1 = &i2c2;
60 i2c2 = &i2c3;
61 i2c3 = &i2c4;
62 mmc0 = &usdhc1;
63 mmc1 = &usdhc2;
64 mmc2 = &usdhc3;
65 serial0 = &uart1;
66 serial1 = &uart2;
67 serial2 = &uart3;
68 serial3 = &uart4;
69 serial4 = &uart5;
70 serial5 = &uart6;
71 serial6 = &uart7;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: cpu@0 {
79 compatible = "arm,cortex-a7";
80 device_type = "cpu";
81 reg = <0>;
82 operating-points = <
83 /* KHz uV */
84 996000 1075000
85 792000 975000
86 >;
87 clock-latency = <61036>; /* two CLK32 periods */
88 clocks = <&clks IMX7D_CLK_ARM>;
89 };
90
91 cpu1: cpu@1 {
92 compatible = "arm,cortex-a7";
93 device_type = "cpu";
94 reg = <1>;
95 };
96 };
97
98 intc: interrupt-controller@31001000 {
99 compatible = "arm,cortex-a7-gic";
100 #interrupt-cells = <3>;
101 interrupt-controller;
102 reg = <0x31001000 0x1000>,
103 <0x31002000 0x1000>,
104 <0x31004000 0x2000>,
105 <0x31006000 0x2000>;
106 };
107
108 ckil: clock-cki {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 clock-frequency = <32768>;
112 clock-output-names = "ckil";
113 };
114
115 osc: clock-osc {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <24000000>;
119 clock-output-names = "osc";
120 };
121
122 etr@30086000 {
123 compatible = "arm,coresight-tmc", "arm,primecell";
124 reg = <0x30086000 0x1000>;
125 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
126 clock-names = "apb_pclk";
127
128 port {
129 etr_in_port: endpoint {
130 slave-mode;
131 remote-endpoint = <&replicator_out_port1>;
132 };
133 };
134 };
135
136 tpiu@30087000 {
137 compatible = "arm,coresight-tpiu", "arm,primecell";
138 reg = <0x30087000 0x1000>;
139 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
140 clock-names = "apb_pclk";
141
142 port {
143 tpiu_in_port: endpoint {
144 slave-mode;
145 remote-endpoint = <&replicator_out_port1>;
146 };
147 };
148 };
149
150 replicator {
151 /*
152 * non-configurable replicators don't show up on the
153 * AMBA bus. As such no need to add "arm,primecell"
154 */
155 compatible = "arm,coresight-replicator";
156
157 ports {
158 #address-cells = <1>;
159 #size-cells = <0>;
160
161 /* replicator output ports */
162 port@0 {
163 reg = <0>;
164 replicator_out_port0: endpoint {
165 remote-endpoint = <&tpiu_in_port>;
166 };
167 };
168
169 port@1 {
170 reg = <1>;
171 replicator_out_port1: endpoint {
172 remote-endpoint = <&etr_in_port>;
173 };
174 };
175
176 /* replicator input port */
177 port@2 {
178 reg = <0>;
179 replicator_in_port0: endpoint {
180 slave-mode;
181 remote-endpoint = <&etf_out_port>;
182 };
183 };
184 };
185 };
186
187 etf@30084000 {
188 compatible = "arm,coresight-tmc", "arm,primecell";
189 reg = <0x30084000 0x1000>;
190 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
191 clock-names = "apb_pclk";
192
193 ports {
194 #address-cells = <1>;
195 #size-cells = <0>;
196
197 port@0 {
198 reg = <0>;
199 etf_in_port: endpoint {
200 slave-mode;
201 remote-endpoint = <&hugo_funnel_out_port0>;
202 };
203 };
204
205 port@1 {
206 reg = <0>;
207 etf_out_port: endpoint {
208 remote-endpoint = <&replicator_in_port0>;
209 };
210 };
211 };
212 };
213
214 funnel@30083000 {
215 compatible = "arm,coresight-funnel", "arm,primecell";
216 reg = <0x30083000 0x1000>;
217 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
218 clock-names = "apb_pclk";
219
220 ports {
221 #address-cells = <1>;
222 #size-cells = <0>;
223
224 /* funnel input ports */
225 port@0 {
226 reg = <0>;
227 hugo_funnel_in_port0: endpoint {
228 slave-mode;
229 remote-endpoint = <&ca_funnel_out_port0>;
230 };
231 };
232
233 port@1 {
234 reg = <1>;
235 hugo_funnel_in_port1: endpoint {
236 slave-mode; /* M4 input */
237 };
238 };
239
240 port@2 {
241 reg = <0>;
242 hugo_funnel_out_port0: endpoint {
243 remote-endpoint = <&etf_in_port>;
244 };
245 };
246
247 /* the other input ports are not connect to anything */
248 };
249 };
250
251 funnel@30041000 {
252 compatible = "arm,coresight-funnel", "arm,primecell";
253 reg = <0x30041000 0x1000>;
254 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
255 clock-names = "apb_pclk";
256
257 ports {
258 #address-cells = <1>;
259 #size-cells = <0>;
260
261 /* funnel input ports */
262 port@0 {
263 reg = <0>;
264 ca_funnel_in_port0: endpoint {
265 slave-mode;
266 remote-endpoint = <&etm0_out_port>;
267 };
268 };
269
270 port@1 {
271 reg = <1>;
272 ca_funnel_in_port1: endpoint {
273 slave-mode;
274 remote-endpoint = <&etm1_out_port>;
275 };
276 };
277
278 /* funnel output port */
279 port@2 {
280 reg = <0>;
281 ca_funnel_out_port0: endpoint {
282 remote-endpoint = <&hugo_funnel_in_port0>;
283 };
284 };
285
286 /* the other input ports are not connect to anything */
287 };
288 };
289
290 etm@3007c000 {
291 compatible = "arm,coresight-etm3x", "arm,primecell";
292 reg = <0x3007c000 0x1000>;
293 cpu = <&cpu0>;
294 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
295 clock-names = "apb_pclk";
296
297 port {
298 etm0_out_port: endpoint {
299 remote-endpoint = <&ca_funnel_in_port0>;
300 };
301 };
302 };
303
304 etm@3007d000 {
305 compatible = "arm,coresight-etm3x", "arm,primecell";
306 reg = <0x3007d000 0x1000>;
307
308 /*
309 * System will hang if added nosmp in kernel command line
310 * without arm,primecell-periphid because amba bus try to
311 * read id and core1 power off at this time.
312 */
313 arm,primecell-periphid = <0xbb956>;
314 cpu = <&cpu1>;
315 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
316 clock-names = "apb_pclk";
317
318 port {
319 etm1_out_port: endpoint {
320 remote-endpoint = <&ca_funnel_in_port1>;
321 };
322 };
323 };
324
325 soc {
326 #address-cells = <1>;
327 #size-cells = <1>;
328 compatible = "simple-bus";
329 interrupt-parent = <&intc>;
330 ranges;
331
332 aips1: aips-bus@30000000 {
333 compatible = "fsl,aips-bus", "simple-bus";
334 #address-cells = <1>;
335 #size-cells = <1>;
336 reg = <0x30000000 0x400000>;
337 ranges;
338
339 gpio1: gpio@30200000 {
340 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
341 reg = <0x30200000 0x10000>;
342 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
343 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 };
349
350 gpio2: gpio@30210000 {
351 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
352 reg = <0x30210000 0x10000>;
353 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
355 gpio-controller;
356 #gpio-cells = <2>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
359 };
360
361 gpio3: gpio@30220000 {
362 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
363 reg = <0x30220000 0x10000>;
364 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
366 gpio-controller;
367 #gpio-cells = <2>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
370 };
371
372 gpio4: gpio@30230000 {
373 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
374 reg = <0x30230000 0x10000>;
375 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 gpio-controller;
378 #gpio-cells = <2>;
379 interrupt-controller;
380 #interrupt-cells = <2>;
381 };
382
383 gpio5: gpio@30240000 {
384 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
385 reg = <0x30240000 0x10000>;
386 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
388 gpio-controller;
389 #gpio-cells = <2>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
392 };
393
394 gpio6: gpio@30250000 {
395 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
396 reg = <0x30250000 0x10000>;
397 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
399 gpio-controller;
400 #gpio-cells = <2>;
401 interrupt-controller;
402 #interrupt-cells = <2>;
403 };
404
405 gpio7: gpio@30260000 {
406 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
407 reg = <0x30260000 0x10000>;
408 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
410 gpio-controller;
411 #gpio-cells = <2>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
414 };
415
416 wdog1: wdog@30280000 {
417 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
418 reg = <0x30280000 0x10000>;
419 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
421 };
422
423 wdog2: wdog@30290000 {
424 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
425 reg = <0x30290000 0x10000>;
426 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
428 status = "disabled";
429 };
430
431 wdog3: wdog@302a0000 {
432 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
433 reg = <0x302a0000 0x10000>;
434 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
436 status = "disabled";
437 };
438
439 wdog4: wdog@302b0000 {
440 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
441 reg = <0x302b0000 0x10000>;
442 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
444 status = "disabled";
445 };
446
447 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
448 compatible = "fsl,imx7d-iomuxc-lpsr";
449 reg = <0x302c0000 0x10000>;
450 fsl,input-sel = <&iomuxc>;
451 };
452
453 gpt1: gpt@302d0000 {
454 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
455 reg = <0x302d0000 0x10000>;
456 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clks IMX7D_CLK_DUMMY>,
458 <&clks IMX7D_GPT1_ROOT_CLK>;
459 clock-names = "ipg", "per";
460 };
461
462 gpt2: gpt@302e0000 {
463 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
464 reg = <0x302e0000 0x10000>;
465 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clks IMX7D_CLK_DUMMY>,
467 <&clks IMX7D_GPT2_ROOT_CLK>;
468 clock-names = "ipg", "per";
469 status = "disabled";
470 };
471
472 gpt3: gpt@302f0000 {
473 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
474 reg = <0x302f0000 0x10000>;
475 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clks IMX7D_CLK_DUMMY>,
477 <&clks IMX7D_GPT3_ROOT_CLK>;
478 clock-names = "ipg", "per";
479 status = "disabled";
480 };
481
482 gpt4: gpt@30300000 {
483 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
484 reg = <0x30300000 0x10000>;
485 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clks IMX7D_CLK_DUMMY>,
487 <&clks IMX7D_GPT4_ROOT_CLK>;
488 clock-names = "ipg", "per";
489 status = "disabled";
490 };
491
492 iomuxc: iomuxc@30330000 {
493 compatible = "fsl,imx7d-iomuxc";
494 reg = <0x30330000 0x10000>;
495 };
496
497 gpr: iomuxc-gpr@30340000 {
498 compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
499 reg = <0x30340000 0x10000>;
500 };
501
502 ocotp: ocotp-ctrl@30350000 {
503 compatible = "syscon";
504 reg = <0x30350000 0x10000>;
505 clocks = <&clks IMX7D_CLK_DUMMY>;
506 status = "disabled";
507 };
508
509 anatop: anatop@30360000 {
510 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
511 "syscon", "simple-bus";
512 reg = <0x30360000 0x10000>;
513 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
515
516 reg_1p0d: regulator-vdd1p0d@210 {
517 compatible = "fsl,anatop-regulator";
518 regulator-name = "vdd1p0d";
519 regulator-min-microvolt = <800000>;
520 regulator-max-microvolt = <1200000>;
521 anatop-reg-offset = <0x210>;
522 anatop-vol-bit-shift = <8>;
523 anatop-vol-bit-width = <5>;
524 anatop-min-bit-val = <8>;
525 anatop-min-voltage = <800000>;
526 anatop-max-voltage = <1200000>;
527 anatop-enable-bit = <31>;
528 };
529 };
530
531 snvs: snvs@30370000 {
532 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
533 reg = <0x30370000 0x10000>;
534
535 snvs_rtc: snvs-rtc-lp {
536 compatible = "fsl,sec-v4.0-mon-rtc-lp";
537 regmap = <&snvs>;
538 offset = <0x34>;
539 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
541 };
542
543 snvs_poweroff: snvs-poweroff {
544 compatible = "syscon-poweroff";
545 regmap = <&snvs>;
546 offset = <0x38>;
547 mask = <0x60>;
548 };
549
550 snvs_pwrkey: snvs-powerkey {
551 compatible = "fsl,sec-v4.0-pwrkey";
552 regmap = <&snvs>;
553 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
554 linux,keycode = <KEY_POWER>;
555 wakeup-source;
556 };
557 };
558
559 clks: ccm@30380000 {
560 compatible = "fsl,imx7d-ccm";
561 reg = <0x30380000 0x10000>;
562 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
564 #clock-cells = <1>;
565 clocks = <&ckil>, <&osc>;
566 clock-names = "ckil", "osc";
567 };
568
569 src: src@30390000 {
570 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
571 reg = <0x30390000 0x10000>;
572 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
573 #reset-cells = <1>;
574 };
575 };
576
577 aips2: aips-bus@30400000 {
578 compatible = "fsl,aips-bus", "simple-bus";
579 #address-cells = <1>;
580 #size-cells = <1>;
581 reg = <0x30400000 0x400000>;
582 ranges;
583
584 adc1: adc@30610000 {
585 compatible = "fsl,imx7d-adc";
586 reg = <0x30610000 0x10000>;
587 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
589 clock-names = "adc";
590 status = "disabled";
591 };
592
593 adc2: adc@30620000 {
594 compatible = "fsl,imx7d-adc";
595 reg = <0x30620000 0x10000>;
596 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
598 clock-names = "adc";
599 status = "disabled";
600 };
601
602 pwm1: pwm@30660000 {
603 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
604 reg = <0x30660000 0x10000>;
605 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
607 <&clks IMX7D_PWM1_ROOT_CLK>;
608 clock-names = "ipg", "per";
609 #pwm-cells = <2>;
610 status = "disabled";
611 };
612
613 pwm2: pwm@30670000 {
614 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
615 reg = <0x30670000 0x10000>;
616 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
618 <&clks IMX7D_PWM2_ROOT_CLK>;
619 clock-names = "ipg", "per";
620 #pwm-cells = <2>;
621 status = "disabled";
622 };
623
624 pwm3: pwm@30680000 {
625 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
626 reg = <0x30680000 0x10000>;
627 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
629 <&clks IMX7D_PWM3_ROOT_CLK>;
630 clock-names = "ipg", "per";
631 #pwm-cells = <2>;
632 status = "disabled";
633 };
634
635 pwm4: pwm@30690000 {
636 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
637 reg = <0x30690000 0x10000>;
638 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
640 <&clks IMX7D_PWM4_ROOT_CLK>;
641 clock-names = "ipg", "per";
642 #pwm-cells = <2>;
643 status = "disabled";
644 };
645 };
646
647 aips3: aips-bus@30800000 {
648 compatible = "fsl,aips-bus", "simple-bus";
649 #address-cells = <1>;
650 #size-cells = <1>;
651 reg = <0x30800000 0x400000>;
652 ranges;
653
654 uart1: serial@30860000 {
655 compatible = "fsl,imx7d-uart",
656 "fsl,imx6q-uart";
657 reg = <0x30860000 0x10000>;
658 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
660 <&clks IMX7D_UART1_ROOT_CLK>;
661 clock-names = "ipg", "per";
662 status = "disabled";
663 };
664
665 uart2: serial@30890000 {
666 compatible = "fsl,imx7d-uart",
667 "fsl,imx6q-uart";
668 reg = <0x30890000 0x10000>;
669 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
671 <&clks IMX7D_UART2_ROOT_CLK>;
672 clock-names = "ipg", "per";
673 status = "disabled";
674 };
675
676 uart3: serial@30880000 {
677 compatible = "fsl,imx7d-uart",
678 "fsl,imx6q-uart";
679 reg = <0x30880000 0x10000>;
680 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
682 <&clks IMX7D_UART3_ROOT_CLK>;
683 clock-names = "ipg", "per";
684 status = "disabled";
685 };
686
687 i2c1: i2c@30a20000 {
688 #address-cells = <1>;
689 #size-cells = <0>;
690 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
691 reg = <0x30a20000 0x10000>;
692 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
694 status = "disabled";
695 };
696
697 i2c2: i2c@30a30000 {
698 #address-cells = <1>;
699 #size-cells = <0>;
700 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
701 reg = <0x30a30000 0x10000>;
702 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
704 status = "disabled";
705 };
706
707 i2c3: i2c@30a40000 {
708 #address-cells = <1>;
709 #size-cells = <0>;
710 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
711 reg = <0x30a40000 0x10000>;
712 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
714 status = "disabled";
715 };
716
717 i2c4: i2c@30a50000 {
718 #address-cells = <1>;
719 #size-cells = <0>;
720 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
721 reg = <0x30a50000 0x10000>;
722 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
724 status = "disabled";
725 };
726
727 uart4: serial@30a60000 {
728 compatible = "fsl,imx7d-uart",
729 "fsl,imx6q-uart";
730 reg = <0x30a60000 0x10000>;
731 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
733 <&clks IMX7D_UART4_ROOT_CLK>;
734 clock-names = "ipg", "per";
735 status = "disabled";
736 };
737
738 uart5: serial@30a70000 {
739 compatible = "fsl,imx7d-uart",
740 "fsl,imx6q-uart";
741 reg = <0x30a70000 0x10000>;
742 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
744 <&clks IMX7D_UART5_ROOT_CLK>;
745 clock-names = "ipg", "per";
746 status = "disabled";
747 };
748
749 uart6: serial@30a80000 {
750 compatible = "fsl,imx7d-uart",
751 "fsl,imx6q-uart";
752 reg = <0x30a80000 0x10000>;
753 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
755 <&clks IMX7D_UART6_ROOT_CLK>;
756 clock-names = "ipg", "per";
757 status = "disabled";
758 };
759
760 uart7: serial@30a90000 {
761 compatible = "fsl,imx7d-uart",
762 "fsl,imx6q-uart";
763 reg = <0x30a90000 0x10000>;
764 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
766 <&clks IMX7D_UART7_ROOT_CLK>;
767 clock-names = "ipg", "per";
768 status = "disabled";
769 };
770
771 usbotg1: usb@30b10000 {
772 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
773 reg = <0x30b10000 0x200>;
774 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clks IMX7D_USB_CTRL_CLK>;
776 fsl,usbphy = <&usbphynop1>;
777 fsl,usbmisc = <&usbmisc1 0>;
778 phy-clkgate-delay-us = <400>;
779 status = "disabled";
780 };
781
782 usbotg2: usb@30b20000 {
783 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
784 reg = <0x30b20000 0x200>;
785 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clks IMX7D_USB_CTRL_CLK>;
787 fsl,usbphy = <&usbphynop2>;
788 fsl,usbmisc = <&usbmisc2 0>;
789 phy-clkgate-delay-us = <400>;
790 status = "disabled";
791 };
792
793 usbh: usb@30b30000 {
794 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
795 reg = <0x30b30000 0x200>;
796 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&clks IMX7D_USB_CTRL_CLK>;
798 fsl,usbphy = <&usbphynop3>;
799 fsl,usbmisc = <&usbmisc3 0>;
800 phy_type = "hsic";
801 dr_mode = "host";
802 phy-clkgate-delay-us = <400>;
803 status = "disabled";
804 };
805
806 usbmisc1: usbmisc@30b10200 {
807 #index-cells = <1>;
808 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
809 reg = <0x30b10200 0x200>;
810 };
811
812 usbmisc2: usbmisc@30b20200 {
813 #index-cells = <1>;
814 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
815 reg = <0x30b20200 0x200>;
816 };
817
818 usbmisc3: usbmisc@30b30200 {
819 #index-cells = <1>;
820 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
821 reg = <0x30b30200 0x200>;
822 };
823
824 usbphynop1: usbphynop1 {
825 compatible = "usb-nop-xceiv";
826 clocks = <&clks IMX7D_USB_PHY1_CLK>;
827 clock-names = "main_clk";
828 };
829
830 usbphynop2: usbphynop2 {
831 compatible = "usb-nop-xceiv";
832 clocks = <&clks IMX7D_USB_PHY2_CLK>;
833 clock-names = "main_clk";
834 };
835
836 usbphynop3: usbphynop3 {
837 compatible = "usb-nop-xceiv";
838 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
839 clock-names = "main_clk";
840 };
841
842 usdhc1: usdhc@30b40000 {
843 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
844 reg = <0x30b40000 0x10000>;
845 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&clks IMX7D_CLK_DUMMY>,
847 <&clks IMX7D_CLK_DUMMY>,
848 <&clks IMX7D_USDHC1_ROOT_CLK>;
849 clock-names = "ipg", "ahb", "per";
850 bus-width = <4>;
851 status = "disabled";
852 };
853
854 usdhc2: usdhc@30b50000 {
855 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
856 reg = <0x30b50000 0x10000>;
857 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&clks IMX7D_CLK_DUMMY>,
859 <&clks IMX7D_CLK_DUMMY>,
860 <&clks IMX7D_USDHC2_ROOT_CLK>;
861 clock-names = "ipg", "ahb", "per";
862 bus-width = <4>;
863 status = "disabled";
864 };
865
866 usdhc3: usdhc@30b60000 {
867 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
868 reg = <0x30b60000 0x10000>;
869 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&clks IMX7D_CLK_DUMMY>,
871 <&clks IMX7D_CLK_DUMMY>,
872 <&clks IMX7D_USDHC3_ROOT_CLK>;
873 clock-names = "ipg", "ahb", "per";
874 bus-width = <4>;
875 status = "disabled";
876 };
877
878 fec1: ethernet@30be0000 {
879 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
880 reg = <0x30be0000 0x10000>;
881 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
885 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
886 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
887 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
888 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
889 clock-names = "ipg", "ahb", "ptp",
890 "enet_clk_ref", "enet_out";
891 fsl,num-tx-queues=<3>;
892 fsl,num-rx-queues=<3>;
893 status = "disabled";
894 };
895
896 fec2: ethernet@30bf0000 {
897 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
898 reg = <0x30bf0000 0x10000>;
899 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
903 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
904 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
905 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
906 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
907 clock-names = "ipg", "ahb", "ptp",
908 "enet_clk_ref", "enet_out";
909 fsl,num-tx-queues=<3>;
910 fsl,num-rx-queues=<3>;
911 status = "disabled";
912 };
913 };
914 };
915 };
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