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regulator: arizona: Add regulator specific device tree binding document
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / imx7d.dtsi
1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/clock/imx7d-clock.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include "imx7d-pinfunc.h"
47 #include "skeleton.dtsi"
48
49 / {
50 aliases {
51 gpio0 = &gpio1;
52 gpio1 = &gpio2;
53 gpio2 = &gpio3;
54 gpio3 = &gpio4;
55 gpio4 = &gpio5;
56 gpio5 = &gpio6;
57 gpio6 = &gpio7;
58 i2c0 = &i2c1;
59 i2c1 = &i2c2;
60 i2c2 = &i2c3;
61 i2c3 = &i2c4;
62 mmc0 = &usdhc1;
63 mmc1 = &usdhc2;
64 mmc2 = &usdhc3;
65 serial0 = &uart1;
66 serial1 = &uart2;
67 serial2 = &uart3;
68 serial3 = &uart4;
69 serial4 = &uart5;
70 serial5 = &uart6;
71 serial6 = &uart7;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: cpu@0 {
79 compatible = "arm,cortex-a7";
80 device_type = "cpu";
81 reg = <0>;
82 operating-points = <
83 /* KHz uV */
84 996000 1075000
85 792000 975000
86 >;
87 clock-latency = <61036>; /* two CLK32 periods */
88 clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
89 <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
90 clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main";
91 };
92
93 cpu1: cpu@1 {
94 compatible = "arm,cortex-a7";
95 device_type = "cpu";
96 reg = <1>;
97 };
98 };
99
100 intc: interrupt-controller@31001000 {
101 compatible = "arm,cortex-a7-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 reg = <0x31001000 0x1000>,
105 <0x31002000 0x1000>,
106 <0x31004000 0x2000>,
107 <0x31006000 0x2000>;
108 };
109
110 ckil: clock-cki {
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <32768>;
114 clock-output-names = "ckil";
115 };
116
117 osc: clock-osc {
118 compatible = "fixed-clock";
119 #clock-cells = <0>;
120 clock-frequency = <24000000>;
121 clock-output-names = "osc";
122 };
123
124 etr@30086000 {
125 compatible = "arm,coresight-tmc", "arm,primecell";
126 reg = <0x30086000 0x1000>;
127 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
128 clock-names = "apb_pclk";
129
130 port {
131 etr_in_port: endpoint {
132 slave-mode;
133 remote-endpoint = <&replicator_out_port1>;
134 };
135 };
136 };
137
138 tpiu@30087000 {
139 compatible = "arm,coresight-tpiu", "arm,primecell";
140 reg = <0x30087000 0x1000>;
141 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
142 clock-names = "apb_pclk";
143
144 port {
145 tpiu_in_port: endpoint {
146 slave-mode;
147 remote-endpoint = <&replicator_out_port1>;
148 };
149 };
150 };
151
152 replicator {
153 /*
154 * non-configurable replicators don't show up on the
155 * AMBA bus. As such no need to add "arm,primecell"
156 */
157 compatible = "arm,coresight-replicator";
158
159 ports {
160 #address-cells = <1>;
161 #size-cells = <0>;
162
163 /* replicator output ports */
164 port@0 {
165 reg = <0>;
166 replicator_out_port0: endpoint {
167 remote-endpoint = <&tpiu_in_port>;
168 };
169 };
170
171 port@1 {
172 reg = <1>;
173 replicator_out_port1: endpoint {
174 remote-endpoint = <&etr_in_port>;
175 };
176 };
177
178 /* replicator input port */
179 port@2 {
180 reg = <0>;
181 replicator_in_port0: endpoint {
182 slave-mode;
183 remote-endpoint = <&etf_out_port>;
184 };
185 };
186 };
187 };
188
189 etf@30084000 {
190 compatible = "arm,coresight-tmc", "arm,primecell";
191 reg = <0x30084000 0x1000>;
192 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
193 clock-names = "apb_pclk";
194
195 ports {
196 #address-cells = <1>;
197 #size-cells = <0>;
198
199 port@0 {
200 reg = <0>;
201 etf_in_port: endpoint {
202 slave-mode;
203 remote-endpoint = <&hugo_funnel_out_port0>;
204 };
205 };
206
207 port@1 {
208 reg = <0>;
209 etf_out_port: endpoint {
210 remote-endpoint = <&replicator_in_port0>;
211 };
212 };
213 };
214 };
215
216 funnel@30083000 {
217 compatible = "arm,coresight-funnel", "arm,primecell";
218 reg = <0x30083000 0x1000>;
219 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
220 clock-names = "apb_pclk";
221
222 ports {
223 #address-cells = <1>;
224 #size-cells = <0>;
225
226 /* funnel input ports */
227 port@0 {
228 reg = <0>;
229 hugo_funnel_in_port0: endpoint {
230 slave-mode;
231 remote-endpoint = <&ca_funnel_out_port0>;
232 };
233 };
234
235 port@1 {
236 reg = <1>;
237 hugo_funnel_in_port1: endpoint {
238 slave-mode; /* M4 input */
239 };
240 };
241
242 port@2 {
243 reg = <0>;
244 hugo_funnel_out_port0: endpoint {
245 remote-endpoint = <&etf_in_port>;
246 };
247 };
248
249 /* the other input ports are not connect to anything */
250 };
251 };
252
253 funnel@30041000 {
254 compatible = "arm,coresight-funnel", "arm,primecell";
255 reg = <0x30041000 0x1000>;
256 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
257 clock-names = "apb_pclk";
258
259 ports {
260 #address-cells = <1>;
261 #size-cells = <0>;
262
263 /* funnel input ports */
264 port@0 {
265 reg = <0>;
266 ca_funnel_in_port0: endpoint {
267 slave-mode;
268 remote-endpoint = <&etm0_out_port>;
269 };
270 };
271
272 port@1 {
273 reg = <1>;
274 ca_funnel_in_port1: endpoint {
275 slave-mode;
276 remote-endpoint = <&etm1_out_port>;
277 };
278 };
279
280 /* funnel output port */
281 port@2 {
282 reg = <0>;
283 ca_funnel_out_port0: endpoint {
284 remote-endpoint = <&hugo_funnel_in_port0>;
285 };
286 };
287
288 /* the other input ports are not connect to anything */
289 };
290 };
291
292 etm@3007c000 {
293 compatible = "arm,coresight-etm3x", "arm,primecell";
294 reg = <0x3007c000 0x1000>;
295 cpu = <&cpu0>;
296 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
297 clock-names = "apb_pclk";
298
299 port {
300 etm0_out_port: endpoint {
301 remote-endpoint = <&ca_funnel_in_port0>;
302 };
303 };
304 };
305
306 etm@3007d000 {
307 compatible = "arm,coresight-etm3x", "arm,primecell";
308 reg = <0x3007d000 0x1000>;
309
310 /*
311 * System will hang if added nosmp in kernel command line
312 * without arm,primecell-periphid because amba bus try to
313 * read id and core1 power off at this time.
314 */
315 arm,primecell-periphid = <0xbb956>;
316 cpu = <&cpu1>;
317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
318 clock-names = "apb_pclk";
319
320 port {
321 etm1_out_port: endpoint {
322 remote-endpoint = <&ca_funnel_in_port1>;
323 };
324 };
325 };
326
327 soc {
328 #address-cells = <1>;
329 #size-cells = <1>;
330 compatible = "simple-bus";
331 interrupt-parent = <&intc>;
332 ranges;
333
334 aips1: aips-bus@30000000 {
335 compatible = "fsl,aips-bus", "simple-bus";
336 #address-cells = <1>;
337 #size-cells = <1>;
338 reg = <0x30000000 0x400000>;
339 ranges;
340
341 gpio1: gpio@30200000 {
342 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
343 reg = <0x30200000 0x10000>;
344 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
345 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 };
351
352 gpio2: gpio@30210000 {
353 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
354 reg = <0x30210000 0x10000>;
355 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
357 gpio-controller;
358 #gpio-cells = <2>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
361 };
362
363 gpio3: gpio@30220000 {
364 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
365 reg = <0x30220000 0x10000>;
366 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 };
373
374 gpio4: gpio@30230000 {
375 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
376 reg = <0x30230000 0x10000>;
377 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
379 gpio-controller;
380 #gpio-cells = <2>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
383 };
384
385 gpio5: gpio@30240000 {
386 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
387 reg = <0x30240000 0x10000>;
388 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 };
395
396 gpio6: gpio@30250000 {
397 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
398 reg = <0x30250000 0x10000>;
399 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 };
406
407 gpio7: gpio@30260000 {
408 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
409 reg = <0x30260000 0x10000>;
410 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
412 gpio-controller;
413 #gpio-cells = <2>;
414 interrupt-controller;
415 #interrupt-cells = <2>;
416 };
417
418 wdog1: wdog@30280000 {
419 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
420 reg = <0x30280000 0x10000>;
421 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
423 };
424
425 wdog2: wdog@30290000 {
426 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
427 reg = <0x30290000 0x10000>;
428 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
430 status = "disabled";
431 };
432
433 wdog3: wdog@302a0000 {
434 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
435 reg = <0x302a0000 0x10000>;
436 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
438 status = "disabled";
439 };
440
441 wdog4: wdog@302b0000 {
442 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
443 reg = <0x302b0000 0x10000>;
444 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
446 status = "disabled";
447 };
448
449 gpt1: gpt@302d0000 {
450 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
451 reg = <0x302d0000 0x10000>;
452 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clks IMX7D_CLK_DUMMY>,
454 <&clks IMX7D_GPT1_ROOT_CLK>;
455 clock-names = "ipg", "per";
456 };
457
458 gpt2: gpt@302e0000 {
459 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
460 reg = <0x302e0000 0x10000>;
461 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX7D_CLK_DUMMY>,
463 <&clks IMX7D_GPT2_ROOT_CLK>;
464 clock-names = "ipg", "per";
465 status = "disabled";
466 };
467
468 gpt3: gpt@302f0000 {
469 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
470 reg = <0x302f0000 0x10000>;
471 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&clks IMX7D_CLK_DUMMY>,
473 <&clks IMX7D_GPT3_ROOT_CLK>;
474 clock-names = "ipg", "per";
475 status = "disabled";
476 };
477
478 gpt4: gpt@30300000 {
479 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
480 reg = <0x30300000 0x10000>;
481 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clks IMX7D_CLK_DUMMY>,
483 <&clks IMX7D_GPT4_ROOT_CLK>;
484 clock-names = "ipg", "per";
485 status = "disabled";
486 };
487
488 iomuxc: iomuxc@30330000 {
489 compatible = "fsl,imx7d-iomuxc";
490 reg = <0x30330000 0x10000>;
491 };
492
493 gpr: iomuxc-gpr@30340000 {
494 compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
495 reg = <0x30340000 0x10000>;
496 };
497
498 ocotp: ocotp-ctrl@30350000 {
499 compatible = "syscon";
500 reg = <0x30350000 0x10000>;
501 clocks = <&clks IMX7D_CLK_DUMMY>;
502 status = "disabled";
503 };
504
505 anatop: anatop@30360000 {
506 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
507 "syscon", "simple-bus";
508 reg = <0x30360000 0x10000>;
509 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
511
512 reg_1p0d: regulator-vdd1p0d@210 {
513 compatible = "fsl,anatop-regulator";
514 regulator-name = "vdd1p0d";
515 regulator-min-microvolt = <800000>;
516 regulator-max-microvolt = <1200000>;
517 anatop-reg-offset = <0x210>;
518 anatop-vol-bit-shift = <8>;
519 anatop-vol-bit-width = <5>;
520 anatop-min-bit-val = <8>;
521 anatop-min-voltage = <800000>;
522 anatop-max-voltage = <1200000>;
523 anatop-enable-bit = <31>;
524 };
525 };
526
527 snvs: snvs@30370000 {
528 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
529 reg = <0x30370000 0x10000>;
530
531 snvs_rtc: snvs-rtc-lp {
532 compatible = "fsl,sec-v4.0-mon-rtc-lp";
533 regmap = <&snvs>;
534 offset = <0x34>;
535 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
537 };
538
539 snvs_poweroff: snvs-poweroff {
540 compatible = "syscon-poweroff";
541 regmap = <&snvs>;
542 offset = <0x38>;
543 mask = <0x60>;
544 };
545
546 snvs_pwrkey: snvs-powerkey {
547 compatible = "fsl,sec-v4.0-pwrkey";
548 regmap = <&snvs>;
549 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
550 linux,keycode = <KEY_POWER>;
551 wakeup-source;
552 };
553 };
554
555 clks: ccm@30380000 {
556 compatible = "fsl,imx7d-ccm";
557 reg = <0x30380000 0x10000>;
558 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
560 #clock-cells = <1>;
561 clocks = <&ckil>, <&osc>;
562 clock-names = "ckil", "osc";
563 };
564
565 src: src@30390000 {
566 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
567 reg = <0x30390000 0x10000>;
568 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
569 #reset-cells = <1>;
570 };
571 };
572
573 aips3: aips-bus@30800000 {
574 compatible = "fsl,aips-bus", "simple-bus";
575 #address-cells = <1>;
576 #size-cells = <1>;
577 reg = <0x30800000 0x400000>;
578 ranges;
579
580 uart1: serial@30860000 {
581 compatible = "fsl,imx7d-uart",
582 "fsl,imx6q-uart";
583 reg = <0x30860000 0x10000>;
584 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
586 <&clks IMX7D_UART1_ROOT_CLK>;
587 clock-names = "ipg", "per";
588 status = "disabled";
589 };
590
591 uart2: serial@30870000 {
592 compatible = "fsl,imx7d-uart",
593 "fsl,imx6q-uart";
594 reg = <0x30870000 0x10000>;
595 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
597 <&clks IMX7D_UART2_ROOT_CLK>;
598 clock-names = "ipg", "per";
599 status = "disabled";
600 };
601
602 uart3: serial@30880000 {
603 compatible = "fsl,imx7d-uart",
604 "fsl,imx6q-uart";
605 reg = <0x30880000 0x10000>;
606 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
608 <&clks IMX7D_UART3_ROOT_CLK>;
609 clock-names = "ipg", "per";
610 status = "disabled";
611 };
612
613 i2c1: i2c@30a20000 {
614 #address-cells = <1>;
615 #size-cells = <0>;
616 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
617 reg = <0x30a20000 0x10000>;
618 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
620 status = "disabled";
621 };
622
623 i2c2: i2c@30a30000 {
624 #address-cells = <1>;
625 #size-cells = <0>;
626 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
627 reg = <0x30a30000 0x10000>;
628 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
630 status = "disabled";
631 };
632
633 i2c3: i2c@30a40000 {
634 #address-cells = <1>;
635 #size-cells = <0>;
636 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
637 reg = <0x30a40000 0x10000>;
638 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
640 status = "disabled";
641 };
642
643 i2c4: i2c@30a50000 {
644 #address-cells = <1>;
645 #size-cells = <0>;
646 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
647 reg = <0x30a50000 0x10000>;
648 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
650 status = "disabled";
651 };
652
653 uart4: serial@30a60000 {
654 compatible = "fsl,imx7d-uart",
655 "fsl,imx6q-uart";
656 reg = <0x30a60000 0x10000>;
657 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
659 <&clks IMX7D_UART4_ROOT_CLK>;
660 clock-names = "ipg", "per";
661 status = "disabled";
662 };
663
664 uart5: serial@30a70000 {
665 compatible = "fsl,imx7d-uart",
666 "fsl,imx6q-uart";
667 reg = <0x30a70000 0x10000>;
668 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
670 <&clks IMX7D_UART5_ROOT_CLK>;
671 clock-names = "ipg", "per";
672 status = "disabled";
673 };
674
675 uart6: serial@30a80000 {
676 compatible = "fsl,imx7d-uart",
677 "fsl,imx6q-uart";
678 reg = <0x30a80000 0x10000>;
679 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
681 <&clks IMX7D_UART6_ROOT_CLK>;
682 clock-names = "ipg", "per";
683 status = "disabled";
684 };
685
686 uart7: serial@30a90000 {
687 compatible = "fsl,imx7d-uart",
688 "fsl,imx6q-uart";
689 reg = <0x30a90000 0x10000>;
690 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
692 <&clks IMX7D_UART7_ROOT_CLK>;
693 clock-names = "ipg", "per";
694 status = "disabled";
695 };
696
697 usdhc1: usdhc@30b40000 {
698 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
699 reg = <0x30b40000 0x10000>;
700 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&clks IMX7D_CLK_DUMMY>,
702 <&clks IMX7D_CLK_DUMMY>,
703 <&clks IMX7D_USDHC1_ROOT_CLK>;
704 clock-names = "ipg", "ahb", "per";
705 bus-width = <4>;
706 status = "disabled";
707 };
708
709 usdhc2: usdhc@30b50000 {
710 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
711 reg = <0x30b50000 0x10000>;
712 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clks IMX7D_CLK_DUMMY>,
714 <&clks IMX7D_CLK_DUMMY>,
715 <&clks IMX7D_USDHC2_ROOT_CLK>;
716 clock-names = "ipg", "ahb", "per";
717 bus-width = <4>;
718 status = "disabled";
719 };
720
721 usdhc3: usdhc@30b60000 {
722 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
723 reg = <0x30b60000 0x10000>;
724 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clks IMX7D_CLK_DUMMY>,
726 <&clks IMX7D_CLK_DUMMY>,
727 <&clks IMX7D_USDHC3_ROOT_CLK>;
728 clock-names = "ipg", "ahb", "per";
729 bus-width = <4>;
730 status = "disabled";
731 };
732 };
733 };
734 };
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