2 * Copyright 2013 Texas Instruments, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/gpio/gpio.h>
12 #include "skeleton.dtsi"
15 compatible = "ti,keystone";
16 model = "Texas Instruments Keystone 2 SoC";
19 interrupt-parent = <&gic>;
29 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
32 gic: interrupt-controller {
33 compatible = "arm,cortex-a15-gic";
34 #interrupt-cells = <3>;
36 reg = <0x0 0x02561000 0x0 0x1000>,
37 <0x0 0x02562000 0x0 0x2000>,
38 <0x0 0x02564000 0x0 0x1000>,
39 <0x0 0x02566000 0x0 0x2000>;
40 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
41 IRQ_TYPE_LEVEL_HIGH)>;
45 compatible = "arm,armv7-timer";
48 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
52 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
54 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
58 compatible = "arm,cortex-a15-pmu";
59 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
60 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
61 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
62 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
66 compatible = "arm,psci";
68 cpu_suspend = <0x84000001>;
69 cpu_off = <0x84000002>;
70 cpu_on = <0x84000003>;
74 compatible = "arm,psci";
76 cpu_suspend = <0x84000001>;
77 cpu_off = <0x84000002>;
78 cpu_on = <0x84000003>;
84 compatible = "ti,keystone","simple-bus";
85 interrupt-parent = <&gic>;
86 ranges = <0x0 0x0 0x0 0xc0000000>;
87 dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
89 pllctrl: pll-controller@02310000 {
90 compatible = "ti,keystone-pllctrl", "syscon";
91 reg = <0x02310000 0x200>;
94 devctrl: device-state-control@02620000 {
95 compatible = "ti,keystone-devctrl", "syscon";
96 reg = <0x02620000 0x1000>;
99 rstctrl: reset-controller {
100 compatible = "ti,keystone-reset";
101 ti,syscon-pll = <&pllctrl 0xe4>;
102 ti,syscon-dev = <&devctrl 0x328>;
106 /include/ "keystone-clocks.dtsi"
108 uart0: serial@02530c00 {
109 compatible = "ns16550a";
110 current-speed = <115200>;
113 reg = <0x02530c00 0x100>;
114 clocks = <&clkuart0>;
115 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
118 uart1: serial@02531000 {
119 compatible = "ns16550a";
120 current-speed = <115200>;
123 reg = <0x02531000 0x100>;
124 clocks = <&clkuart1>;
125 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
129 compatible = "ti,davinci-i2c";
130 reg = <0x02530000 0x400>;
131 clock-frequency = <100000>;
133 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
134 #address-cells = <1>;
139 compatible = "ti,davinci-i2c";
140 reg = <0x02530400 0x400>;
141 clock-frequency = <100000>;
143 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
144 #address-cells = <1>;
149 compatible = "ti,davinci-i2c";
150 reg = <0x02530800 0x400>;
151 clock-frequency = <100000>;
153 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
154 #address-cells = <1>;
159 compatible = "ti,keystone-spi", "ti,dm6441-spi";
160 reg = <0x21000400 0x200>;
162 ti,davinci-spi-intr-line = <0>;
163 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
165 #address-cells = <1>;
170 compatible = "ti,keystone-spi", "ti,dm6441-spi";
171 reg = <0x21000600 0x200>;
173 ti,davinci-spi-intr-line = <0>;
174 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
176 #address-cells = <1>;
181 compatible = "ti,keystone-spi", "ti,dm6441-spi";
182 reg = <0x21000800 0x200>;
184 ti,davinci-spi-intr-line = <0>;
185 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
187 #address-cells = <1>;
191 usb_phy: usb_phy@2620738 {
192 compatible = "ti,keystone-usbphy";
193 #address-cells = <1>;
195 reg = <0x2620738 24>;
200 compatible = "ti,keystone-dwc3";
201 #address-cells = <1>;
203 reg = <0x2680000 0x10000>;
206 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
213 compatible = "synopsys,dwc3";
214 reg = <0x2690000 0x70000>;
215 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
216 usb-phy = <&usb_phy>, <&usb_phy>;
221 compatible = "ti,keystone-wdt","ti,davinci-wdt";
222 reg = <0x022f0080 0x80>;
223 clocks = <&clkwdtimer0>;
226 clock_event: timer@22f0000 {
227 compatible = "ti,keystone-timer";
228 reg = <0x022f0000 0x80>;
229 interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
230 clocks = <&clktimer15>;
233 gpio0: gpio@260bf00 {
234 compatible = "ti,keystone-gpio";
235 reg = <0x0260bf00 0x100>;
238 /* HW Interrupts mapped to GPIO pins */
239 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
240 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
241 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
242 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
243 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
244 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
245 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
246 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
247 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
248 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
249 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
250 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
251 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
252 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
254 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
255 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
256 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
257 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
258 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
259 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
260 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
261 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
262 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
263 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
264 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
265 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
266 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
267 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
268 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
269 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
270 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
272 clock-names = "gpio";
274 ti,davinci-gpio-unbanked = <32>;
277 aemif: aemif@21000A00 {
278 compatible = "ti,keystone-aemif", "ti,davinci-aemif";
279 #address-cells = <2>;
281 clocks = <&clkaemif>;
282 clock-names = "aemif";
285 reg = <0x21000A00 0x00000100>;
286 ranges = <0 0 0x30000000 0x10000000
287 1 0 0x21000A00 0x00000100>;
290 kirq0: keystone_irq@26202a0 {
291 compatible = "ti,keystone-irq";
292 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
293 interrupt-controller;
294 #interrupt-cells = <1>;
295 ti,syscon-dev = <&devctrl 0x2a0>;
298 pcie0: pcie@21800000 {
299 compatible = "ti,keystone-pcie", "snps,dw-pcie";
301 clock-names = "pcie";
302 #address-cells = <3>;
304 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
305 ranges = <0x82000000 0 0x50000000 0x50000000
311 bus-range = <0x00 0xff>;
313 /* error interrupt */
314 interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
315 #interrupt-cells = <1>;
316 interrupt-map-mask = <0 0 0 7>;
317 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
318 <0 0 0 2 &pcie_intc0 1>, /* INT B */
319 <0 0 0 3 &pcie_intc0 2>, /* INT C */
320 <0 0 0 4 &pcie_intc0 3>; /* INT D */
322 pcie_msi_intc0: msi-interrupt-controller {
323 interrupt-controller;
324 #interrupt-cells = <1>;
325 interrupt-parent = <&gic>;
326 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
327 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
328 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
329 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
330 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
331 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
332 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
333 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
336 pcie_intc0: legacy-interrupt-controller {
337 interrupt-controller;
338 #interrupt-cells = <1>;
339 interrupt-parent = <&gic>;
340 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
341 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
342 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
343 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;