arch/arm/boot/dts/marco.dtsi

   1 /*
   2  * DTS file for CSR SiRFmarco SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,marco";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&gic>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a9";
  23                         reg = <0>;
  24                 };
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <1>;
  29                 };
  30         };
  31
  32         axi {
  33                 compatible = "simple-bus";
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 ranges = <0x40000000 0x40000000 0xa0000000>;
  37
  38                 l2-cache-controller@c0030000 {
  39                         compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
  40                         reg = <0xc0030000 0x1000>;
  41                         interrupts = <0 59 0>;
  42                         arm,tag-latency = <1 1 1>;
  43                         arm,data-latency = <1 1 1>;
  44                         arm,filter-ranges = <0x40000000 0x80000000>;
  45                 };
  46
  47                 gic: interrupt-controller@c0011000 {
  48                         compatible = "arm,cortex-a9-gic";
  49                         interrupt-controller;
  50                         #interrupt-cells = <3>;
  51                         reg = <0xc0011000 0x1000>,
  52                               <0xc0010100 0x0100>;
  53                 };
  54
  55                 rstc-iobg {
  56                         compatible = "simple-bus";
  57                         #address-cells = <1>;
  58                         #size-cells = <1>;
  59                         ranges = <0xc2000000 0xc2000000 0x1000000>;
  60
  61                         reset-controller@c2000000 {
  62                                 compatible = "sirf,marco-rstc";
  63                                 reg = <0xc2000000 0x10000>;
  64                         };
  65                 };
  66
  67                 sys-iobg {
  68                         compatible = "simple-bus";
  69                         #address-cells = <1>;
  70                         #size-cells = <1>;
  71                         ranges = <0xc3000000 0xc3000000 0x1000000>;
  72
  73                         clock-controller@c3000000 {
  74                                 compatible = "sirf,marco-clkc";
  75                                 reg = <0xc3000000 0x1000>;
  76                                 interrupts = <0 3 0>;
  77                         };
  78
  79                         rsc-controller@c3010000 {
  80                                 compatible = "sirf,marco-rsc";
  81                                 reg = <0xc3010000 0x1000>;
  82                         };
  83                 };
  84
  85                 mem-iobg {
  86                         compatible = "simple-bus";
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         ranges = <0xc4000000 0xc4000000 0x1000000>;
  90
  91                         memory-controller@c4000000 {
  92                                 compatible = "sirf,marco-memc";
  93                                 reg = <0xc4000000 0x10000>;
  94                                 interrupts = <0 27 0>;
  95                         };
  96                 };
  97
  98                 disp-iobg0 {
  99                         compatible = "simple-bus";
 100                         #address-cells = <1>;
 101                         #size-cells = <1>;
 102                         ranges = <0xc5000000 0xc5000000 0x1000000>;
 103
 104                         display0@c5000000 {
 105                                 compatible = "sirf,marco-lcd";
 106                                 reg = <0xc5000000 0x10000>;
 107                                 interrupts = <0 30 0>;
 108                         };
 109
 110                         vpp0@c5010000 {
 111                                 compatible = "sirf,marco-vpp";
 112                                 reg = <0xc5010000 0x10000>;
 113                                 interrupts = <0 31 0>;
 114                         };
 115                 };
 116
 117                 disp-iobg1 {
 118                         compatible = "simple-bus";
 119                         #address-cells = <1>;
 120                         #size-cells = <1>;
 121                         ranges = <0xc6000000 0xc6000000 0x1000000>;
 122
 123                         display1@c6000000 {
 124                                 compatible = "sirf,marco-lcd";
 125                                 reg = <0xc6000000 0x10000>;
 126                                 interrupts = <0 62 0>;
 127                         };
 128
 129                         vpp1@c6010000 {
 130                                 compatible = "sirf,marco-vpp";
 131                                 reg = <0xc6010000 0x10000>;
 132                                 interrupts = <0 63 0>;
 133                         };
 134                 };
 135
 136                 graphics-iobg {
 137                         compatible = "simple-bus";
 138                         #address-cells = <1>;
 139                         #size-cells = <1>;
 140                         ranges = <0xc8000000 0xc8000000 0x1000000>;
 141
 142                         graphics@c8000000 {
 143                                 compatible = "powervr,sgx540";
 144                                 reg = <0xc8000000 0x1000000>;
 145                                 interrupts = <0 6 0>;
 146                         };
 147                 };
 148
 149                 multimedia-iobg {
 150                         compatible = "simple-bus";
 151                         #address-cells = <1>;
 152                         #size-cells = <1>;
 153                         ranges = <0xc9000000 0xc9000000 0x1000000>;
 154
 155                         multimedia@a0000000 {
 156                                 compatible = "sirf,marco-video-codec";
 157                                 reg = <0xc9000000 0x1000000>;
 158                                 interrupts = <0 5 0>;
 159                         };
 160                 };
 161
 162                 dsp-iobg {
 163                         compatible = "simple-bus";
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         ranges = <0xca000000 0xca000000 0x2000000>;
 167
 168                         dspif@ca000000 {
 169                                 compatible = "sirf,marco-dspif";
 170                                 reg = <0xca000000 0x10000>;
 171                                 interrupts = <0 9 0>;
 172                         };
 173
 174                         gps@ca010000 {
 175                                 compatible = "sirf,marco-gps";
 176                                 reg = <0xca010000 0x10000>;
 177                                 interrupts = <0 7 0>;
 178                         };
 179
 180                         dsp@cb000000 {
 181                                 compatible = "sirf,marco-dsp";
 182                                 reg = <0xcb000000 0x1000000>;
 183                                 interrupts = <0 8 0>;
 184                         };
 185                 };
 186
 187                 peri-iobg {
 188                         compatible = "simple-bus";
 189                         #address-cells = <1>;
 190                         #size-cells = <1>;
 191                         ranges = <0xcc000000 0xcc000000 0x2000000>;
 192
 193                         timer@cc020000 {
 194                                 compatible = "sirf,marco-tick";
 195                                 reg = <0xcc020000 0x1000>;
 196                                 interrupts = <0 0 0>,
 197                                            <0 1 0>,
 198                                            <0 2 0>,
 199                                            <0 49 0>,
 200                                            <0 50 0>,
 201                                            <0 51 0>;
 202                         };
 203
 204                         nand@cc030000 {
 205                                 compatible = "sirf,marco-nand";
 206                                 reg = <0xcc030000 0x10000>;
 207                                 interrupts = <0 41 0>;
 208                         };
 209
 210                         audio@cc040000 {
 211                                 compatible = "sirf,marco-audio";
 212                                 reg = <0xcc040000 0x10000>;
 213                                 interrupts = <0 35 0>;
 214                         };
 215
 216                         uart0: uart@cc050000 {
 217                                 cell-index = <0>;
 218                                 compatible = "sirf,marco-uart";
 219                                 reg = <0xcc050000 0x1000>;
 220                                 interrupts = <0 17 0>;
 221                                 fifosize = <128>;
 222                                 status = "disabled";
 223                         };
 224
 225                         uart1: uart@cc060000 {
 226                                 cell-index = <1>;
 227                                 compatible = "sirf,marco-uart";
 228                                 reg = <0xcc060000 0x1000>;
 229                                 interrupts = <0 18 0>;
 230                                 fifosize = <32>;
 231                                 status = "disabled";
 232                         };
 233
 234                         uart2: uart@cc070000 {
 235                                 cell-index = <2>;
 236                                 compatible = "sirf,marco-uart";
 237                                 reg = <0xcc070000 0x1000>;
 238                                 interrupts = <0 19 0>;
 239                                 fifosize = <128>;
 240                                 status = "disabled";
 241                         };
 242
 243                         uart3: uart@cc190000 {
 244                                 cell-index = <3>;
 245                                 compatible = "sirf,marco-uart";
 246                                 reg = <0xcc190000 0x1000>;
 247                                 interrupts = <0 66 0>;
 248                                 fifosize = <128>;
 249                                 status = "disabled";
 250                         };
 251
 252                         uart4: uart@cc1a0000 {
 253                                 cell-index = <4>;
 254                                 compatible = "sirf,marco-uart";
 255                                 reg = <0xcc1a0000 0x1000>;
 256                                 interrupts = <0 69 0>;
 257                                 fifosize = <128>;
 258                                 status = "disabled";
 259                         };
 260
 261                         usp0: usp@cc080000 {
 262                                 cell-index = <0>;
 263                                 compatible = "sirf,marco-usp";
 264                                 reg = <0xcc080000 0x10000>;
 265                                 interrupts = <0 20 0>;
 266                                 status = "disabled";
 267                         };
 268
 269                         usp1: usp@cc090000 {
 270                                 cell-index = <1>;
 271                                 compatible = "sirf,marco-usp";
 272                                 reg = <0xcc090000 0x10000>;
 273                                 interrupts = <0 21 0>;
 274                                 status = "disabled";
 275                         };
 276
 277                         usp2: usp@cc0a0000 {
 278                                 cell-index = <2>;
 279                                 compatible = "sirf,marco-usp";
 280                                 reg = <0xcc0a0000 0x10000>;
 281                                 interrupts = <0 22 0>;
 282                                 status = "disabled";
 283                         };
 284
 285                         dmac0: dma-controller@cc0b0000 {
 286                                 cell-index = <0>;
 287                                 compatible = "sirf,marco-dmac";
 288                                 reg = <0xcc0b0000 0x10000>;
 289                                 interrupts = <0 12 0>;
 290                         };
 291
 292                         dmac1: dma-controller@cc160000 {
 293                                 cell-index = <1>;
 294                                 compatible = "sirf,marco-dmac";
 295                                 reg = <0xcc160000 0x10000>;
 296                                 interrupts = <0 13 0>;
 297                         };
 298
 299                         vip@cc0c0000 {
 300                                 compatible = "sirf,marco-vip";
 301                                 reg = <0xcc0c0000 0x10000>;
 302                         };
 303
 304                         spi0: spi@cc0d0000 {
 305                                 cell-index = <0>;
 306                                 compatible = "sirf,marco-spi";
 307                                 reg = <0xcc0d0000 0x10000>;
 308                                 interrupts = <0 15 0>;
 309                                 sirf,spi-num-chipselects = <1>;
 310                                 cs-gpios = <&gpio 0 0>;
 311                                 sirf,spi-dma-rx-channel = <25>;
 312                                 sirf,spi-dma-tx-channel = <20>;
 313                                 #address-cells = <1>;
 314                                 #size-cells = <0>;
 315                                 status = "disabled";
 316                         };
 317
 318                         spi1: spi@cc170000 {
 319                                 cell-index = <1>;
 320                                 compatible = "sirf,marco-spi";
 321                                 reg = <0xcc170000 0x10000>;
 322                                 interrupts = <0 16 0>;
 323                                 sirf,spi-num-chipselects = <1>;
 324                                 cs-gpios = <&gpio 0 0>;
 325                                 sirf,spi-dma-rx-channel = <12>;
 326                                 sirf,spi-dma-tx-channel = <13>;
 327                                 #address-cells = <1>;
 328                                 #size-cells = <0>;
 329                                 status = "disabled";
 330                         };
 331
 332                         i2c0: i2c@cc0e0000 {
 333                                 cell-index = <0>;
 334                                 compatible = "sirf,marco-i2c";
 335                                 reg = <0xcc0e0000 0x10000>;
 336                                 interrupts = <0 24 0>;
 337                                 #address-cells = <1>;
 338                                 #size-cells = <0>;
 339                                 status = "disabled";
 340                         };
 341
 342                         i2c1: i2c@cc0f0000 {
 343                                 cell-index = <1>;
 344                                 compatible = "sirf,marco-i2c";
 345                                 reg = <0xcc0f0000 0x10000>;
 346                                 interrupts = <0 25 0>;
 347                                 #address-cells = <1>;
 348                                 #size-cells = <0>;
 349                                 status = "disabled";
 350                         };
 351
 352                         tsc@cc110000 {
 353                                 compatible = "sirf,marco-tsc";
 354                                 reg = <0xcc110000 0x10000>;
 355                                 interrupts = <0 33 0>;
 356                         };
 357
 358                         gpio: pinctrl@cc120000 {
 359                                 #gpio-cells = <2>;
 360                                 #interrupt-cells = <2>;
 361                                 compatible = "sirf,marco-pinctrl";
 362                                 reg = <0xcc120000 0x10000>;
 363                                 interrupts = <0 43 0>,
 364                                            <0 44 0>,
 365                                            <0 45 0>,
 366                                            <0 46 0>,
 367                                            <0 47 0>;
 368                                 gpio-controller;
 369                                 interrupt-controller;
 370
 371                                 lcd_16pins_a: lcd0_0 {
 372                                         lcd {
 373                                                 sirf,pins = "lcd_16bitsgrp";
 374                                                 sirf,function = "lcd_16bits";
 375                                         };
 376                                 };
 377                                 lcd_18pins_a: lcd0_1 {
 378                                         lcd {
 379                                                 sirf,pins = "lcd_18bitsgrp";
 380                                                 sirf,function = "lcd_18bits";
 381                                         };
 382                                 };
 383                                 lcd_24pins_a: lcd0_2 {
 384                                         lcd {
 385                                                 sirf,pins = "lcd_24bitsgrp";
 386                                                 sirf,function = "lcd_24bits";
 387                                         };
 388                                 };
 389                                 lcdrom_pins_a: lcdrom0_0 {
 390                                         lcd {
 391                                                 sirf,pins = "lcdromgrp";
 392                                                 sirf,function = "lcdrom";
 393                                         };
 394                                 };
 395                                 uart0_pins_a: uart0_0 {
 396                                         uart {
 397                                                 sirf,pins = "uart0grp";
 398                                                 sirf,function = "uart0";
 399                                         };
 400                                 };
 401                                 uart1_pins_a: uart1_0 {
 402                                         uart {
 403                                                 sirf,pins = "uart1grp";
 404                                                 sirf,function = "uart1";
 405                                         };
 406                                 };
 407                                 uart2_pins_a: uart2_0 {
 408                                         uart {
 409                                                 sirf,pins = "uart2grp";
 410                                                 sirf,function = "uart2";
 411                                         };
 412                                 };
 413                                 uart2_noflow_pins_a: uart2_1 {
 414                                         uart {
 415                                                 sirf,pins = "uart2_nostreamctrlgrp";
 416                                                 sirf,function = "uart2_nostreamctrl";
 417                                         };
 418                                 };
 419                                 spi0_pins_a: spi0_0 {
 420                                         spi {
 421                                                 sirf,pins = "spi0grp";
 422                                                 sirf,function = "spi0";
 423                                         };
 424                                 };
 425                                 spi1_pins_a: spi1_0 {
 426                                         spi {
 427                                                 sirf,pins = "spi1grp";
 428                                                 sirf,function = "spi1";
 429                                         };
 430                                 };
 431                                 i2c0_pins_a: i2c0_0 {
 432                                         i2c {
 433                                                 sirf,pins = "i2c0grp";
 434                                                 sirf,function = "i2c0";
 435                                         };
 436                                 };
 437                                 i2c1_pins_a: i2c1_0 {
 438                                         i2c {
 439                                                 sirf,pins = "i2c1grp";
 440                                                 sirf,function = "i2c1";
 441                                         };
 442                                 };
 443                                 pwm0_pins_a: pwm0_0 {
 444                                         pwm {
 445                                                 sirf,pins = "pwm0grp";
 446                                                 sirf,function = "pwm0";
 447                                         };
 448                                 };
 449                                 pwm1_pins_a: pwm1_0 {
 450                                         pwm {
 451                                                 sirf,pins = "pwm1grp";
 452                                                 sirf,function = "pwm1";
 453                                         };
 454                                 };
 455                                 pwm2_pins_a: pwm2_0 {
 456                                         pwm {
 457                                                 sirf,pins = "pwm2grp";
 458                                                 sirf,function = "pwm2";
 459                                         };
 460                                 };
 461                                 pwm3_pins_a: pwm3_0 {
 462                                         pwm {
 463                                                 sirf,pins = "pwm3grp";
 464                                                 sirf,function = "pwm3";
 465                                         };
 466                                 };
 467                                 gps_pins_a: gps_0 {
 468                                         gps {
 469                                                 sirf,pins = "gpsgrp";
 470                                                 sirf,function = "gps";
 471                                         };
 472                                 };
 473                                 vip_pins_a: vip_0 {
 474                                         vip {
 475                                                 sirf,pins = "vipgrp";
 476                                                 sirf,function = "vip";
 477                                         };
 478                                 };
 479                                 sdmmc0_pins_a: sdmmc0_0 {
 480                                         sdmmc0 {
 481                                                 sirf,pins = "sdmmc0grp";
 482                                                 sirf,function = "sdmmc0";
 483                                         };
 484                                 };
 485                                 sdmmc1_pins_a: sdmmc1_0 {
 486                                         sdmmc1 {
 487                                                 sirf,pins = "sdmmc1grp";
 488                                                 sirf,function = "sdmmc1";
 489                                         };
 490                                 };
 491                                 sdmmc2_pins_a: sdmmc2_0 {
 492                                         sdmmc2 {
 493                                                 sirf,pins = "sdmmc2grp";
 494                                                 sirf,function = "sdmmc2";
 495                                         };
 496                                 };
 497                                 sdmmc3_pins_a: sdmmc3_0 {
 498                                         sdmmc3 {
 499                                                 sirf,pins = "sdmmc3grp";
 500                                                 sirf,function = "sdmmc3";
 501                                         };
 502                                 };
 503                                 sdmmc4_pins_a: sdmmc4_0 {
 504                                         sdmmc4 {
 505                                                 sirf,pins = "sdmmc4grp";
 506                                                 sirf,function = "sdmmc4";
 507                                         };
 508                                 };
 509                                 sdmmc5_pins_a: sdmmc5_0 {
 510                                         sdmmc5 {
 511                                                 sirf,pins = "sdmmc5grp";
 512                                                 sirf,function = "sdmmc5";
 513                                         };
 514                                 };
 515                                 i2s_pins_a: i2s_0 {
 516                                         i2s {
 517                                                 sirf,pins = "i2sgrp";
 518                                                 sirf,function = "i2s";
 519                                         };
 520                                 };
 521                                 ac97_pins_a: ac97_0 {
 522                                         ac97 {
 523                                                 sirf,pins = "ac97grp";
 524                                                 sirf,function = "ac97";
 525                                         };
 526                                 };
 527                                 nand_pins_a: nand_0 {
 528                                         nand {
 529                                                 sirf,pins = "nandgrp";
 530                                                 sirf,function = "nand";
 531                                         };
 532                                 };
 533                                 usp0_pins_a: usp0_0 {
 534                                         usp0 {
 535                                                 sirf,pins = "usp0grp";
 536                                                 sirf,function = "usp0";
 537                                         };
 538                                 };
 539                                 usp1_pins_a: usp1_0 {
 540                                         usp1 {
 541                                                 sirf,pins = "usp1grp";
 542                                                 sirf,function = "usp1";
 543                                         };
 544                                 };
 545                                 usp2_pins_a: usp2_0 {
 546                                         usp2 {
 547                                                 sirf,pins = "usp2grp";
 548                                                 sirf,function = "usp2";
 549                                         };
 550                                 };
 551                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
 552                                         usb0_utmi_drvbus {
 553                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 554                                                 sirf,function = "usb0_utmi_drvbus";
 555                                         };
 556                                 };
 557                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
 558                                         usb1_utmi_drvbus {
 559                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 560                                                 sirf,function = "usb1_utmi_drvbus";
 561                                         };
 562                                 };
 563                                 warm_rst_pins_a: warm_rst_0 {
 564                                         warm_rst {
 565                                                 sirf,pins = "warm_rstgrp";
 566                                                 sirf,function = "warm_rst";
 567                                         };
 568                                 };
 569                                 pulse_count_pins_a: pulse_count_0 {
 570                                         pulse_count {
 571                                                 sirf,pins = "pulse_countgrp";
 572                                                 sirf,function = "pulse_count";
 573                                         };
 574                                 };
 575                                 cko0_rst_pins_a: cko0_rst_0 {
 576                                         cko0_rst {
 577                                                 sirf,pins = "cko0_rstgrp";
 578                                                 sirf,function = "cko0_rst";
 579                                         };
 580                                 };
 581                                 cko1_rst_pins_a: cko1_rst_0 {
 582                                         cko1_rst {
 583                                                 sirf,pins = "cko1_rstgrp";
 584                                                 sirf,function = "cko1_rst";
 585                                         };
 586                                 };
 587                         };
 588
 589                         pwm@cc130000 {
 590                                 compatible = "sirf,marco-pwm";
 591                                 reg = <0xcc130000 0x10000>;
 592                         };
 593
 594                         efusesys@cc140000 {
 595                                 compatible = "sirf,marco-efuse";
 596                                 reg = <0xcc140000 0x10000>;
 597                         };
 598
 599                         pulsec@cc150000 {
 600                                 compatible = "sirf,marco-pulsec";
 601                                 reg = <0xcc150000 0x10000>;
 602                                 interrupts = <0 48 0>;
 603                         };
 604
 605                         pci-iobg {
 606                                 compatible = "sirf,marco-pciiobg", "simple-bus";
 607                                 #address-cells = <1>;
 608                                 #size-cells = <1>;
 609                                 ranges = <0xcd000000 0xcd000000 0x1000000>;
 610
 611                                 sd0: sdhci@cd000000 {
 612                                         cell-index = <0>;
 613                                         compatible = "sirf,marco-sdhc";
 614                                         reg = <0xcd000000 0x100000>;
 615                                         interrupts = <0 38 0>;
 616                                         status = "disabled";
 617                                 };
 618
 619                                 sd1: sdhci@cd100000 {
 620                                         cell-index = <1>;
 621                                         compatible = "sirf,marco-sdhc";
 622                                         reg = <0xcd100000 0x100000>;
 623                                         interrupts = <0 38 0>;
 624                                         status = "disabled";
 625                                 };
 626
 627                                 sd2: sdhci@cd200000 {
 628                                         cell-index = <2>;
 629                                         compatible = "sirf,marco-sdhc";
 630                                         reg = <0xcd200000 0x100000>;
 631                                         interrupts = <0 23 0>;
 632                                         status = "disabled";
 633                                 };
 634
 635                                 sd3: sdhci@cd300000 {
 636                                         cell-index = <3>;
 637                                         compatible = "sirf,marco-sdhc";
 638                                         reg = <0xcd300000 0x100000>;
 639                                         interrupts = <0 23 0>;
 640                                         status = "disabled";
 641                                 };
 642
 643                                 sd4: sdhci@cd400000 {
 644                                         cell-index = <4>;
 645                                         compatible = "sirf,marco-sdhc";
 646                                         reg = <0xcd400000 0x100000>;
 647                                         interrupts = <0 39 0>;
 648                                         status = "disabled";
 649                                 };
 650
 651                                 sd5: sdhci@cd500000 {
 652                                         cell-index = <5>;
 653                                         compatible = "sirf,marco-sdhc";
 654                                         reg = <0xcd500000 0x100000>;
 655                                         interrupts = <0 39 0>;
 656                                         status = "disabled";
 657                                 };
 658
 659                                 pci-copy@cd900000 {
 660                                         compatible = "sirf,marco-pcicp";
 661                                         reg = <0xcd900000 0x100000>;
 662                                         interrupts = <0 40 0>;
 663                                 };
 664
 665                                 rom-interface@cda00000 {
 666                                         compatible = "sirf,marco-romif";
 667                                         reg = <0xcda00000 0x100000>;
 668                                 };
 669                         };
 670                 };
 671
 672                 rtc-iobg {
 673                         compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
 674                         #address-cells = <1>;
 675                         #size-cells = <1>;
 676                         reg = <0xc1000000 0x10000>;
 677
 678                         gpsrtc@1000 {
 679                                 compatible = "sirf,marco-gpsrtc";
 680                                 reg = <0x1000 0x1000>;
 681                                 interrupts = <0 55 0>,
 682                                            <0 56 0>,
 683                                            <0 57 0>;
 684                         };
 685
 686                         sysrtc@2000 {
 687                                 compatible = "sirf,marco-sysrtc";
 688                                 reg = <0x2000 0x1000>;
 689                                 interrupts = <0 52 0>,
 690                                            <0 53 0>,
 691                                            <0 54 0>;
 692                         };
 693
 694                         pwrc@3000 {
 695                                 compatible = "sirf,marco-pwrc";
 696                                 reg = <0x3000 0x1000>;
 697                                 interrupts = <0 32 0>;
 698                         };
 699                 };
 700
 701                 uus-iobg {
 702                         compatible = "simple-bus";
 703                         #address-cells = <1>;
 704                         #size-cells = <1>;
 705                         ranges = <0xce000000 0xce000000 0x1000000>;
 706
 707                         usb0: usb@ce000000 {
 708                                 compatible = "chipidea,ci13611a-marco";
 709                                 reg = <0xce000000 0x10000>;
 710                                 interrupts = <0 10 0>;
 711                         };
 712
 713                         usb1: usb@ce010000 {
 714                                 compatible = "chipidea,ci13611a-marco";
 715                                 reg = <0xce010000 0x10000>;
 716                                 interrupts = <0 11 0>;
 717                         };
 718
 719                         security@ce020000 {
 720                                 compatible = "sirf,marco-security";
 721                                 reg = <0xce020000 0x10000>;
 722                                 interrupts = <0 42 0>;
 723                         };
 724                 };
 725
 726                 can-iobg {
 727                         compatible = "simple-bus";
 728                         #address-cells = <1>;
 729                         #size-cells = <1>;
 730                         ranges = <0xd0000000 0xd0000000 0x1000000>;
 731
 732                         can0: can@d0000000 {
 733                                 compatible = "sirf,marco-can";
 734                                 reg = <0xd0000000 0x10000>;
 735                         };
 736
 737                         can1: can@d0010000 {
 738                                 compatible = "sirf,marco-can";
 739                                 reg = <0xd0010000 0x10000>;
 740                         };
 741                 };
 742
 743                 lvds-iobg {
 744                         compatible = "simple-bus";
 745                         #address-cells = <1>;
 746                         #size-cells = <1>;
 747                         ranges = <0xd1000000 0xd1000000 0x1000000>;
 748
 749                         lvds@d1000000 {
 750                                 compatible = "sirf,marco-lvds";
 751                                 reg = <0xd1000000 0x10000>;
 752                                 interrupts = <0 64 0>;
 753                         };
 754                 };
 755         };
 756 };