arch/arm/boot/dts/meson8b.dtsi

   1 /*
   2  * Copyright 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  *     You should have received a copy of the GNU General Public License
  21  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/clock/meson8b-clkc.h>
  48 #include <dt-bindings/gpio/meson8b-gpio.h>
  49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  51 #include "meson.dtsi"
  52
  53 / {
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@200 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a5";
  61                         next-level-cache = <&L2>;
  62                         reg = <0x200>;
  63                         enable-method = "amlogic,meson8b-smp";
  64                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  65                         operating-points-v2 = <&cpu_opp_table>;
  66                         clocks = <&clkc CLKID_CPUCLK>;
  67                 };
  68
  69                 cpu1: cpu@201 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a5";
  72                         next-level-cache = <&L2>;
  73                         reg = <0x201>;
  74                         enable-method = "amlogic,meson8b-smp";
  75                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  76                         operating-points-v2 = <&cpu_opp_table>;
  77                         clocks = <&clkc CLKID_CPUCLK>;
  78                 };
  79
  80                 cpu2: cpu@202 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a5";
  83                         next-level-cache = <&L2>;
  84                         reg = <0x202>;
  85                         enable-method = "amlogic,meson8b-smp";
  86                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  87                         operating-points-v2 = <&cpu_opp_table>;
  88                         clocks = <&clkc CLKID_CPUCLK>;
  89                 };
  90
  91                 cpu3: cpu@203 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a5";
  94                         next-level-cache = <&L2>;
  95                         reg = <0x203>;
  96                         enable-method = "amlogic,meson8b-smp";
  97                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  98                         operating-points-v2 = <&cpu_opp_table>;
  99                         clocks = <&clkc CLKID_CPUCLK>;
 100                 };
 101         };
 102
 103         cpu_opp_table: opp-table {
 104                 compatible = "operating-points-v2";
 105                 opp-shared;
 106
 107                 opp-96000000 {
 108                         opp-hz = /bits/ 64 <96000000>;
 109                         opp-microvolt = <860000>;
 110                 };
 111                 opp-192000000 {
 112                         opp-hz = /bits/ 64 <192000000>;
 113                         opp-microvolt = <860000>;
 114                 };
 115                 opp-312000000 {
 116                         opp-hz = /bits/ 64 <312000000>;
 117                         opp-microvolt = <860000>;
 118                 };
 119                 opp-408000000 {
 120                         opp-hz = /bits/ 64 <408000000>;
 121                         opp-microvolt = <860000>;
 122                 };
 123                 opp-504000000 {
 124                         opp-hz = /bits/ 64 <504000000>;
 125                         opp-microvolt = <860000>;
 126                 };
 127                 opp-600000000 {
 128                         opp-hz = /bits/ 64 <600000000>;
 129                         opp-microvolt = <860000>;
 130                 };
 131                 opp-720000000 {
 132                         opp-hz = /bits/ 64 <720000000>;
 133                         opp-microvolt = <860000>;
 134                 };
 135                 opp-816000000 {
 136                         opp-hz = /bits/ 64 <816000000>;
 137                         opp-microvolt = <900000>;
 138                 };
 139                 opp-1008000000 {
 140                         opp-hz = /bits/ 64 <1008000000>;
 141                         opp-microvolt = <1140000>;
 142                 };
 143                 opp-1200000000 {
 144                         opp-hz = /bits/ 64 <1200000000>;
 145                         opp-microvolt = <1140000>;
 146                 };
 147                 opp-1320000000 {
 148                         opp-hz = /bits/ 64 <1320000000>;
 149                         opp-microvolt = <1140000>;
 150                 };
 151                 opp-1488000000 {
 152                         opp-hz = /bits/ 64 <1488000000>;
 153                         opp-microvolt = <1140000>;
 154                 };
 155                 opp-1536000000 {
 156                         opp-hz = /bits/ 64 <1536000000>;
 157                         opp-microvolt = <1140000>;
 158                 };
 159         };
 160
 161         gpu_opp_table: gpu-opp-table {
 162                 compatible = "operating-points-v2";
 163
 164                 opp-255000000 {
 165                         opp-hz = /bits/ 64 <255000000>;
 166                         opp-microvolt = <1100000>;
 167                 };
 168                 opp-364300000 {
 169                         opp-hz = /bits/ 64 <364300000>;
 170                         opp-microvolt = <1100000>;
 171                 };
 172                 opp-425000000 {
 173                         opp-hz = /bits/ 64 <425000000>;
 174                         opp-microvolt = <1100000>;
 175                 };
 176                 opp-510000000 {
 177                         opp-hz = /bits/ 64 <510000000>;
 178                         opp-microvolt = <1100000>;
 179                 };
 180                 opp-637500000 {
 181                         opp-hz = /bits/ 64 <637500000>;
 182                         opp-microvolt = <1100000>;
 183                         turbo-mode;
 184                 };
 185         };
 186
 187         pmu {
 188                 compatible = "arm,cortex-a5-pmu";
 189                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 193                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 194         };
 195
 196         reserved-memory {
 197                 #address-cells = <1>;
 198                 #size-cells = <1>;
 199                 ranges;
 200
 201                 /* 2 MiB reserved for Hardware ROM Firmware? */
 202                 hwrom@0 {
 203                         reg = <0x0 0x200000>;
 204                         no-map;
 205                 };
 206         };
 207
 208         apb: bus@d0000000 {
 209                 compatible = "simple-bus";
 210                 reg = <0xd0000000 0x200000>;
 211                 #address-cells = <1>;
 212                 #size-cells = <1>;
 213                 ranges = <0x0 0xd0000000 0x200000>;
 214
 215                 mali: gpu@c0000 {
 216                         compatible = "amlogic,meson8b-mali", "arm,mali-450";
 217                         reg = <0xc0000 0x40000>;
 218                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 226                         interrupt-names = "gp", "gpmmu", "pp", "pmu",
 227                                           "pp0", "ppmmu0", "pp1", "ppmmu1";
 228                         resets = <&reset RESET_MALI>;
 229                         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 230                         clock-names = "bus", "core";
 231                         operating-points-v2 = <&gpu_opp_table>;
 232                 };
 233         };
 234 }; /* end of / */
 235
 236 &aobus {
 237         pmu: pmu@e0 {
 238                 compatible = "amlogic,meson8b-pmu", "syscon";
 239                 reg = <0xe0 0x18>;
 240         };
 241
 242         pinctrl_aobus: pinctrl@84 {
 243                 compatible = "amlogic,meson8b-aobus-pinctrl";
 244                 reg = <0x84 0xc>;
 245                 #address-cells = <1>;
 246                 #size-cells = <1>;
 247                 ranges;
 248
 249                 gpio_ao: ao-bank@14 {
 250                         reg = <0x14 0x4>,
 251                                 <0x2c 0x4>,
 252                                 <0x24 0x8>;
 253                         reg-names = "mux", "pull", "gpio";
 254                         gpio-controller;
 255                         #gpio-cells = <2>;
 256                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 257                 };
 258
 259                 uart_ao_a_pins: uart_ao_a {
 260                         mux {
 261                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 262                                 function = "uart_ao";
 263                                 bias-disable;
 264                         };
 265                 };
 266
 267                 ir_recv_pins: remote {
 268                         mux {
 269                                 groups = "remote_input";
 270                                 function = "remote";
 271                                 bias-disable;
 272                         };
 273                 };
 274         };
 275 };
 276
 277 &cbus {
 278         reset: reset-controller@4404 {
 279                 compatible = "amlogic,meson8b-reset";
 280                 reg = <0x4404 0x9c>;
 281                 #reset-cells = <1>;
 282         };
 283
 284         analog_top: analog-top@81a8 {
 285                 compatible = "amlogic,meson8b-analog-top", "syscon";
 286                 reg = <0x81a8 0x14>;
 287         };
 288
 289         pwm_ef: pwm@86c0 {
 290                 compatible = "amlogic,meson8b-pwm";
 291                 reg = <0x86c0 0x10>;
 292                 #pwm-cells = <3>;
 293                 status = "disabled";
 294         };
 295
 296         clock-measure@8758 {
 297                 compatible = "amlogic,meson8b-clk-measure";
 298                 reg = <0x8758 0x1c>;
 299         };
 300
 301         pinctrl_cbus: pinctrl@9880 {
 302                 compatible = "amlogic,meson8b-cbus-pinctrl";
 303                 reg = <0x9880 0x10>;
 304                 #address-cells = <1>;
 305                 #size-cells = <1>;
 306                 ranges;
 307
 308                 gpio: banks@80b0 {
 309                         reg = <0x80b0 0x28>,
 310                                 <0x80e8 0x18>,
 311                                 <0x8120 0x18>,
 312                                 <0x8030 0x38>;
 313                         reg-names = "mux", "pull", "pull-enable", "gpio";
 314                         gpio-controller;
 315                         #gpio-cells = <2>;
 316                         gpio-ranges = <&pinctrl_cbus 0 0 83>;
 317                 };
 318
 319                 eth_rgmii_pins: eth-rgmii {
 320                         mux {
 321                                 groups = "eth_tx_clk",
 322                                          "eth_tx_en",
 323                                          "eth_txd1_0",
 324                                          "eth_txd0_0",
 325                                          "eth_rx_clk",
 326                                          "eth_rx_dv",
 327                                          "eth_rxd1",
 328                                          "eth_rxd0",
 329                                          "eth_mdio_en",
 330                                          "eth_mdc",
 331                                          "eth_ref_clk",
 332                                          "eth_txd2",
 333                                          "eth_txd3",
 334                                          "eth_rxd3",
 335                                          "eth_rxd2";
 336                                 function = "ethernet";
 337                                 bias-disable;
 338                         };
 339                 };
 340
 341                 eth_rmii_pins: eth-rmii {
 342                         mux {
 343                                 groups = "eth_tx_en",
 344                                          "eth_txd1_0",
 345                                          "eth_txd0_0",
 346                                          "eth_rx_clk",
 347                                          "eth_rx_dv",
 348                                          "eth_rxd1",
 349                                          "eth_rxd0",
 350                                          "eth_mdio_en",
 351                                          "eth_mdc";
 352                                 function = "ethernet";
 353                                 bias-disable;
 354                         };
 355                 };
 356
 357                 i2c_a_pins: i2c-a {
 358                         mux {
 359                                 groups = "i2c_sda_a", "i2c_sck_a";
 360                                 function = "i2c_a";
 361                                 bias-disable;
 362                         };
 363                 };
 364
 365                 sd_b_pins: sd-b {
 366                         mux {
 367                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 368                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 369                                 function = "sd_b";
 370                                 bias-disable;
 371                         };
 372                 };
 373
 374                 pwm_c1_pins: pwm-c1 {
 375                         mux {
 376                                 groups = "pwm_c1";
 377                                 function = "pwm_c";
 378                                 bias-disable;
 379                         };
 380                 };
 381
 382                 uart_b0_pins: uart-b0 {
 383                         mux {
 384                                 groups = "uart_tx_b0",
 385                                        "uart_rx_b0";
 386                                 function = "uart_b";
 387                                 bias-disable;
 388                         };
 389                 };
 390
 391                 uart_b0_cts_rts_pins: uart-b0-cts-rts {
 392                         mux {
 393                                 groups = "uart_cts_b0",
 394                                        "uart_rts_b0";
 395                                 function = "uart_b";
 396                                 bias-disable;
 397                         };
 398                 };
 399         };
 400 };
 401
 402 &ahb_sram {
 403         smp-sram@1ff80 {
 404                 compatible = "amlogic,meson8b-smp-sram";
 405                 reg = <0x1ff80 0x8>;
 406         };
 407 };
 408
 409
 410 &efuse {
 411         compatible = "amlogic,meson8b-efuse";
 412         clocks = <&clkc CLKID_EFUSE>;
 413         clock-names = "core";
 414
 415         temperature_calib: calib@1f4 {
 416                 /* only the upper two bytes are relevant */
 417                 reg = <0x1f4 0x4>;
 418         };
 419 };
 420
 421 &ethmac {
 422         compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
 423
 424         reg = <0xc9410000 0x10000
 425                0xc1108140 0x4>;
 426
 427         clocks = <&clkc CLKID_ETH>,
 428                  <&clkc CLKID_MPLL2>,
 429                  <&clkc CLKID_MPLL2>;
 430         clock-names = "stmmaceth", "clkin0", "clkin1";
 431
 432         resets = <&reset RESET_ETHERNET>;
 433         reset-names = "stmmaceth";
 434 };
 435
 436 &gpio_intc {
 437         compatible = "amlogic,meson-gpio-intc",
 438                      "amlogic,meson8b-gpio-intc";
 439         status = "okay";
 440 };
 441
 442 &hhi {
 443         clkc: clock-controller {
 444                 compatible = "amlogic,meson8-clkc";
 445                 #clock-cells = <1>;
 446                 #reset-cells = <1>;
 447         };
 448 };
 449
 450 &hwrng {
 451         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
 452         clocks = <&clkc CLKID_RNG0>;
 453         clock-names = "core";
 454 };
 455
 456 &i2c_AO {
 457         clocks = <&clkc CLKID_CLK81>;
 458 };
 459
 460 &i2c_A {
 461         clocks = <&clkc CLKID_I2C>;
 462 };
 463
 464 &i2c_B {
 465         clocks = <&clkc CLKID_I2C>;
 466 };
 467
 468 &L2 {
 469         arm,data-latency = <3 3 3>;
 470         arm,tag-latency = <2 2 2>;
 471         arm,filter-ranges = <0x100000 0xc0000000>;
 472         prefetch-data = <1>;
 473         prefetch-instr = <1>;
 474         arm,shared-override;
 475 };
 476
 477 &periph {
 478         scu@0 {
 479                 compatible = "arm,cortex-a5-scu";
 480                 reg = <0x0 0x100>;
 481         };
 482
 483         timer@200 {
 484                 compatible = "arm,cortex-a5-global-timer";
 485                 reg = <0x200 0x20>;
 486                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 487                 clocks = <&clkc CLKID_PERIPH>;
 488
 489                 /*
 490                  * the arm_global_timer driver currently does not handle clock
 491                  * rate changes. Keep it disabled for now.
 492                  */
 493                 status = "disabled";
 494         };
 495
 496         timer@600 {
 497                 compatible = "arm,cortex-a5-twd-timer";
 498                 reg = <0x600 0x20>;
 499                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 500                 clocks = <&clkc CLKID_PERIPH>;
 501         };
 502 };
 503
 504 &pwm_ab {
 505         compatible = "amlogic,meson8b-pwm";
 506 };
 507
 508 &pwm_cd {
 509         compatible = "amlogic,meson8b-pwm";
 510 };
 511
 512 &rtc {
 513         compatible = "amlogic,meson8b-rtc";
 514         resets = <&reset RESET_RTC>;
 515 };
 516
 517 &saradc {
 518         compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
 519         clocks = <&clkc CLKID_XTAL>,
 520                 <&clkc CLKID_SAR_ADC>;
 521         clock-names = "clkin", "core";
 522         amlogic,hhi-sysctrl = <&hhi>;
 523         nvmem-cells = <&temperature_calib>;
 524         nvmem-cell-names = "temperature_calib";
 525 };
 526
 527 &sdio {
 528         compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
 529         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 530         clock-names = "core", "clkin";
 531 };
 532
 533 &timer_abcde {
 534         clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 535         clock-names = "xtal", "pclk";
 536 };
 537
 538 &uart_AO {
 539         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 540         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 541         clock-names = "baud", "xtal", "pclk";
 542 };
 543
 544 &uart_A {
 545         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 546         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
 547         clock-names = "baud", "xtal", "pclk";
 548 };
 549
 550 &uart_B {
 551         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 552         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
 553         clock-names = "baud", "xtal", "pclk";
 554 };
 555
 556 &uart_C {
 557         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 558         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
 559         clock-names = "baud", "xtal", "pclk";
 560 };
 561
 562 &usb0 {
 563         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 564         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 565         clock-names = "otg";
 566 };
 567
 568 &usb1 {
 569         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 570         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 571         clock-names = "otg";
 572 };
 573
 574 &usb0_phy {
 575         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 576         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 577         clock-names = "usb_general", "usb";
 578         resets = <&reset RESET_USB_OTG>;
 579 };
 580
 581 &usb1_phy {
 582         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 583         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 584         clock-names = "usb_general", "usb";
 585         resets = <&reset RESET_USB_OTG>;
 586 };
 587
 588 &wdt {
 589         compatible = "amlogic,meson8b-wdt";
 590 };