arch/arm/boot/dts/mt7623.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: John Crispin <john@phrozen.org>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/clock/mt2701-clk.h>
  19 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  20 #include <dt-bindings/power/mt2701-power.h>
  21 #include <dt-bindings/gpio/gpio.h>
  22 #include <dt-bindings/phy/phy.h>
  23 #include <dt-bindings/reset/mt2701-resets.h>
  24 #include <dt-bindings/thermal/thermal.h>
  25
  26 / {
  27         compatible = "mediatek,mt7623";
  28         interrupt-parent = <&sysirq>;
  29         #address-cells = <2>;
  30         #size-cells = <2>;
  31
  32         cpu_opp_table: opp_table {
  33                 compatible = "operating-points-v2";
  34                 opp-shared;
  35
  36                 opp-98000000 {
  37                         opp-hz = /bits/ 64 <98000000>;
  38                         opp-microvolt = <1050000>;
  39                 };
  40
  41                 opp-198000000 {
  42                         opp-hz = /bits/ 64 <198000000>;
  43                         opp-microvolt = <1050000>;
  44                 };
  45
  46                 opp-398000000 {
  47                         opp-hz = /bits/ 64 <398000000>;
  48                         opp-microvolt = <1050000>;
  49                 };
  50
  51                 opp-598000000 {
  52                         opp-hz = /bits/ 64 <598000000>;
  53                         opp-microvolt = <1050000>;
  54                 };
  55
  56                 opp-747500000 {
  57                         opp-hz = /bits/ 64 <747500000>;
  58                         opp-microvolt = <1050000>;
  59                 };
  60
  61                 opp-1040000000 {
  62                         opp-hz = /bits/ 64 <1040000000>;
  63                         opp-microvolt = <1150000>;
  64                 };
  65
  66                 opp-1196000000 {
  67                         opp-hz = /bits/ 64 <1196000000>;
  68                         opp-microvolt = <1200000>;
  69                 };
  70
  71                 opp-1300000000 {
  72                         opp-hz = /bits/ 64 <1300000000>;
  73                         opp-microvolt = <1300000>;
  74                 };
  75         };
  76
  77         cpus {
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80                 enable-method = "mediatek,mt6589-smp";
  81
  82                 cpu0: cpu@0 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a7";
  85                         reg = <0x0>;
  86                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  87                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  88                         clock-names = "cpu", "intermediate";
  89                         operating-points-v2 = <&cpu_opp_table>;
  90                         #cooling-cells = <2>;
  91                         cooling-min-level = <0>;
  92                         cooling-max-level = <7>;
  93                         clock-frequency = <1300000000>;
  94                 };
  95
  96                 cpu1: cpu@1 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a7";
  99                         reg = <0x1>;
 100                         operating-points-v2 = <&cpu_opp_table>;
 101                         #cooling-cells = <2>;
 102                         clock-frequency = <1300000000>;
 103                 };
 104
 105                 cpu2: cpu@2 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a7";
 108                         reg = <0x2>;
 109                         operating-points-v2 = <&cpu_opp_table>;
 110                         #cooling-cells = <2>;
 111                         clock-frequency = <1300000000>;
 112                 };
 113
 114                 cpu3: cpu@3 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a7";
 117                         reg = <0x3>;
 118                         operating-points-v2 = <&cpu_opp_table>;
 119                         #cooling-cells = <2>;
 120                         clock-frequency = <1300000000>;
 121                 };
 122         };
 123
 124         system_clk: dummy13m {
 125                 compatible = "fixed-clock";
 126                 clock-frequency = <13000000>;
 127                 #clock-cells = <0>;
 128         };
 129
 130         rtc32k: oscillator@1 {
 131                 compatible = "fixed-clock";
 132                 #clock-cells = <0>;
 133                 clock-frequency = <32000>;
 134                 clock-output-names = "rtc32k";
 135         };
 136
 137         clk26m: oscillator@0 {
 138                 compatible = "fixed-clock";
 139                 #clock-cells = <0>;
 140                 clock-frequency = <26000000>;
 141                 clock-output-names = "clk26m";
 142         };
 143
 144         thermal-zones {
 145                         cpu_thermal: cpu_thermal {
 146                                 polling-delay-passive = <1000>;
 147                                 polling-delay = <1000>;
 148
 149                                 thermal-sensors = <&thermal 0>;
 150
 151                                 trips {
 152                                         cpu_passive: cpu_passive {
 153                                                 temperature = <47000>;
 154                                                 hysteresis = <2000>;
 155                                                 type = "passive";
 156                                         };
 157
 158                                         cpu_active: cpu_active {
 159                                                 temperature = <67000>;
 160                                                 hysteresis = <2000>;
 161                                                 type = "active";
 162                                         };
 163
 164                                         cpu_hot: cpu_hot {
 165                                                 temperature = <87000>;
 166                                                 hysteresis = <2000>;
 167                                                 type = "hot";
 168                                         };
 169
 170                                         cpu_crit {
 171                                                 temperature = <107000>;
 172                                                 hysteresis = <2000>;
 173                                                 type = "critical";
 174                                         };
 175                                 };
 176
 177                         cooling-maps {
 178                                 map0 {
 179                                         trip = <&cpu_passive>;
 180                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 181                                 };
 182
 183                                 map1 {
 184                                         trip = <&cpu_active>;
 185                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 186                                 };
 187
 188                                 map2 {
 189                                         trip = <&cpu_hot>;
 190                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 191                                 };
 192                         };
 193                 };
 194         };
 195
 196         timer {
 197                 compatible = "arm,armv7-timer";
 198                 interrupt-parent = <&gic>;
 199                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 200                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 201                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 202                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 203                 clock-frequency = <13000000>;
 204                 arm,cpu-registers-not-fw-configured;
 205         };
 206
 207         topckgen: syscon@10000000 {
 208                 compatible = "mediatek,mt7623-topckgen",
 209                              "mediatek,mt2701-topckgen",
 210                              "syscon";
 211                 reg = <0 0x10000000 0 0x1000>;
 212                 #clock-cells = <1>;
 213         };
 214
 215         infracfg: syscon@10001000 {
 216                 compatible = "mediatek,mt7623-infracfg",
 217                              "mediatek,mt2701-infracfg",
 218                              "syscon";
 219                 reg = <0 0x10001000 0 0x1000>;
 220                 #clock-cells = <1>;
 221                 #reset-cells = <1>;
 222         };
 223
 224         pericfg: syscon@10003000 {
 225                 compatible =  "mediatek,mt7623-pericfg",
 226                               "mediatek,mt2701-pericfg",
 227                               "syscon";
 228                 reg = <0 0x10003000 0 0x1000>;
 229                 #clock-cells = <1>;
 230                 #reset-cells = <1>;
 231         };
 232
 233         pio: pinctrl@10005000 {
 234                 compatible = "mediatek,mt7623-pinctrl";
 235                 reg = <0 0x1000b000 0 0x1000>;
 236                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 237                 pins-are-numbered;
 238                 gpio-controller;
 239                 #gpio-cells = <2>;
 240                 interrupt-controller;
 241                 interrupt-parent = <&gic>;
 242                 #interrupt-cells = <2>;
 243                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 245         };
 246
 247         syscfg_pctl_a: syscfg@10005000 {
 248                 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 249                 reg = <0 0x10005000 0 0x1000>;
 250         };
 251
 252         scpsys: scpsys@10006000 {
 253                 compatible = "mediatek,mt7623-scpsys",
 254                              "mediatek,mt2701-scpsys",
 255                              "syscon";
 256                 #power-domain-cells = <1>;
 257                 reg = <0 0x10006000 0 0x1000>;
 258                 infracfg = <&infracfg>;
 259                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 260                          <&topckgen CLK_TOP_MFG_SEL>,
 261                          <&topckgen CLK_TOP_ETHIF_SEL>;
 262                 clock-names = "mm", "mfg", "ethif";
 263         };
 264
 265         watchdog: watchdog@10007000 {
 266                 compatible = "mediatek,mt7623-wdt",
 267                              "mediatek,mt6589-wdt";
 268                 reg = <0 0x10007000 0 0x100>;
 269         };
 270
 271         timer: timer@10008000 {
 272                 compatible = "mediatek,mt7623-timer",
 273                              "mediatek,mt6577-timer";
 274                 reg = <0 0x10008000 0 0x80>;
 275                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 276                 clocks = <&system_clk>, <&rtc32k>;
 277                 clock-names = "system-clk", "rtc-clk";
 278         };
 279
 280         pwrap: pwrap@1000d000 {
 281                 compatible = "mediatek,mt7623-pwrap",
 282                              "mediatek,mt2701-pwrap";
 283                 reg = <0 0x1000d000 0 0x1000>;
 284                 reg-names = "pwrap";
 285                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 286                 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 287                 reset-names = "pwrap";
 288                 clocks = <&infracfg CLK_INFRA_PMICSPI>,
 289                          <&infracfg CLK_INFRA_PMICWRAP>;
 290                 clock-names = "spi", "wrap";
 291         };
 292
 293         cir: cir@10013000 {
 294                 compatible = "mediatek,mt7623-cir";
 295                 reg = <0 0x10013000 0 0x1000>;
 296                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 297                 clocks = <&infracfg CLK_INFRA_IRRX>;
 298                 clock-names = "clk";
 299                 status = "disabled";
 300         };
 301
 302         sysirq: interrupt-controller@10200100 {
 303                 compatible = "mediatek,mt7623-sysirq",
 304                              "mediatek,mt6577-sysirq";
 305                 interrupt-controller;
 306                 #interrupt-cells = <3>;
 307                 interrupt-parent = <&gic>;
 308                 reg = <0 0x10200100 0 0x1c>;
 309         };
 310
 311         efuse: efuse@10206000 {
 312                 compatible = "mediatek,mt7623-efuse",
 313                              "mediatek,mt8173-efuse";
 314                 reg = <0 0x10206000 0 0x1000>;
 315                 #address-cells = <1>;
 316                 #size-cells = <1>;
 317                 thermal_calibration_data: calib@424 {
 318                         reg = <0x424 0xc>;
 319                 };
 320         };
 321
 322         apmixedsys: syscon@10209000 {
 323                 compatible = "mediatek,mt7623-apmixedsys",
 324                              "mediatek,mt2701-apmixedsys",
 325                              "syscon";
 326                 reg = <0 0x10209000 0 0x1000>;
 327                 #clock-cells = <1>;
 328         };
 329
 330         rng: rng@1020f000 {
 331                 compatible = "mediatek,mt7623-rng";
 332                 reg = <0 0x1020f000 0 0x1000>;
 333                 clocks = <&infracfg CLK_INFRA_TRNG>;
 334                 clock-names = "rng";
 335         };
 336
 337         gic: interrupt-controller@10211000 {
 338                 compatible = "arm,cortex-a7-gic";
 339                 interrupt-controller;
 340                 #interrupt-cells = <3>;
 341                 interrupt-parent = <&gic>;
 342                 reg = <0 0x10211000 0 0x1000>,
 343                       <0 0x10212000 0 0x2000>,
 344                       <0 0x10214000 0 0x2000>,
 345                       <0 0x10216000 0 0x2000>;
 346         };
 347
 348         auxadc: adc@11001000 {
 349                 compatible = "mediatek,mt7623-auxadc",
 350                              "mediatek,mt2701-auxadc";
 351                 reg = <0 0x11001000 0 0x1000>;
 352                 clocks = <&pericfg CLK_PERI_AUXADC>;
 353                 clock-names = "main";
 354                 #io-channel-cells = <1>;
 355         };
 356
 357         uart0: serial@11002000 {
 358                 compatible = "mediatek,mt7623-uart",
 359                              "mediatek,mt6577-uart";
 360                 reg = <0 0x11002000 0 0x400>;
 361                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 362                 clocks = <&pericfg CLK_PERI_UART0_SEL>,
 363                          <&pericfg CLK_PERI_UART0>;
 364                 clock-names = "baud", "bus";
 365                 status = "disabled";
 366         };
 367
 368         uart1: serial@11003000 {
 369                 compatible = "mediatek,mt7623-uart",
 370                              "mediatek,mt6577-uart";
 371                 reg = <0 0x11003000 0 0x400>;
 372                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 373                 clocks = <&pericfg CLK_PERI_UART1_SEL>,
 374                          <&pericfg CLK_PERI_UART1>;
 375                 clock-names = "baud", "bus";
 376                 status = "disabled";
 377         };
 378
 379         uart2: serial@11004000 {
 380                 compatible = "mediatek,mt7623-uart",
 381                              "mediatek,mt6577-uart";
 382                 reg = <0 0x11004000 0 0x400>;
 383                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 384                 clocks = <&pericfg CLK_PERI_UART2_SEL>,
 385                          <&pericfg CLK_PERI_UART2>;
 386                 clock-names = "baud", "bus";
 387                 status = "disabled";
 388         };
 389
 390         uart3: serial@11005000 {
 391                 compatible = "mediatek,mt7623-uart",
 392                              "mediatek,mt6577-uart";
 393                 reg = <0 0x11005000 0 0x400>;
 394                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 395                 clocks = <&pericfg CLK_PERI_UART3_SEL>,
 396                          <&pericfg CLK_PERI_UART3>;
 397                 clock-names = "baud", "bus";
 398                 status = "disabled";
 399         };
 400
 401         pwm: pwm@11006000 {
 402                 compatible = "mediatek,mt7623-pwm";
 403                 reg = <0 0x11006000 0 0x1000>;
 404                 #pwm-cells = <2>;
 405                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 406                          <&pericfg CLK_PERI_PWM>,
 407                          <&pericfg CLK_PERI_PWM1>,
 408                          <&pericfg CLK_PERI_PWM2>,
 409                          <&pericfg CLK_PERI_PWM3>,
 410                          <&pericfg CLK_PERI_PWM4>,
 411                          <&pericfg CLK_PERI_PWM5>;
 412                 clock-names = "top", "main", "pwm1", "pwm2",
 413                               "pwm3", "pwm4", "pwm5";
 414                 status = "disabled";
 415         };
 416
 417         i2c0: i2c@11007000 {
 418                 compatible = "mediatek,mt7623-i2c",
 419                              "mediatek,mt6577-i2c";
 420                 reg = <0 0x11007000 0 0x70>,
 421                       <0 0x11000200 0 0x80>;
 422                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 423                 clock-div = <16>;
 424                 clocks = <&pericfg CLK_PERI_I2C0>,
 425                          <&pericfg CLK_PERI_AP_DMA>;
 426                 clock-names = "main", "dma";
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 status = "disabled";
 430         };
 431
 432         i2c1: i2c@11008000 {
 433                 compatible = "mediatek,mt7623-i2c",
 434                              "mediatek,mt6577-i2c";
 435                 reg = <0 0x11008000 0 0x70>,
 436                       <0 0x11000280 0 0x80>;
 437                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 438                 clock-div = <16>;
 439                 clocks = <&pericfg CLK_PERI_I2C1>,
 440                          <&pericfg CLK_PERI_AP_DMA>;
 441                 clock-names = "main", "dma";
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 status = "disabled";
 445         };
 446
 447         i2c2: i2c@11009000 {
 448                 compatible = "mediatek,mt7623-i2c",
 449                              "mediatek,mt6577-i2c";
 450                 reg = <0 0x11009000 0 0x70>,
 451                       <0 0x11000300 0 0x80>;
 452                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 453                 clock-div = <16>;
 454                 clocks = <&pericfg CLK_PERI_I2C2>,
 455                          <&pericfg CLK_PERI_AP_DMA>;
 456                 clock-names = "main", "dma";
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 status = "disabled";
 460         };
 461
 462         spi0: spi@1100a000 {
 463                 compatible = "mediatek,mt7623-spi",
 464                              "mediatek,mt2701-spi";
 465                 #address-cells = <1>;
 466                 #size-cells = <0>;
 467                 reg = <0 0x1100a000 0 0x100>;
 468                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 469                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 470                          <&topckgen CLK_TOP_SPI0_SEL>,
 471                          <&pericfg CLK_PERI_SPI0>;
 472                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 473                 status = "disabled";
 474         };
 475
 476         thermal: thermal@1100b000 {
 477                 #thermal-sensor-cells = <1>;
 478                 compatible = "mediatek,mt7623-thermal",
 479                              "mediatek,mt2701-thermal";
 480                 reg = <0 0x1100b000 0 0x1000>;
 481                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 482                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 483                 clock-names = "therm", "auxadc";
 484                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 485                 reset-names = "therm";
 486                 mediatek,auxadc = <&auxadc>;
 487                 mediatek,apmixedsys = <&apmixedsys>;
 488                 nvmem-cells = <&thermal_calibration_data>;
 489                 nvmem-cell-names = "calibration-data";
 490         };
 491
 492         nandc: nfi@1100d000 {
 493                 compatible = "mediatek,mt7623-nfc",
 494                              "mediatek,mt2701-nfc";
 495                 reg = <0 0x1100d000 0 0x1000>;
 496                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 497                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 498                 clocks = <&pericfg CLK_PERI_NFI>,
 499                          <&pericfg CLK_PERI_NFI_PAD>;
 500                 clock-names = "nfi_clk", "pad_clk";
 501                 status = "disabled";
 502                 ecc-engine = <&bch>;
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505         };
 506
 507         bch: ecc@1100e000 {
 508                 compatible = "mediatek,mt7623-ecc",
 509                              "mediatek,mt2701-ecc";
 510                 reg = <0 0x1100e000 0 0x1000>;
 511                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 512                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 513                 clock-names = "nfiecc_clk";
 514                 status = "disabled";
 515         };
 516
 517         spi1: spi@11016000 {
 518                 compatible = "mediatek,mt7623-spi",
 519                              "mediatek,mt2701-spi";
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 reg = <0 0x11016000 0 0x100>;
 523                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 524                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 525                          <&topckgen CLK_TOP_SPI1_SEL>,
 526                          <&pericfg CLK_PERI_SPI1>;
 527                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 528                 status = "disabled";
 529         };
 530
 531         spi2: spi@11017000 {
 532                 compatible = "mediatek,mt7623-spi",
 533                              "mediatek,mt2701-spi";
 534                 #address-cells = <1>;
 535                 #size-cells = <0>;
 536                 reg = <0 0x11017000 0 0x1000>;
 537                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 538                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 539                          <&topckgen CLK_TOP_SPI2_SEL>,
 540                          <&pericfg CLK_PERI_SPI2>;
 541                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 542                 status = "disabled";
 543         };
 544
 545         afe: audio-controller@11220000 {
 546                 compatible = "mediatek,mt7623-audio",
 547                              "mediatek,mt2701-audio";
 548                 reg = <0 0x11220000 0 0x2000>,
 549                       <0 0x112a0000 0 0x20000>;
 550                 interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 551                               <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 552                 interrupt-names = "afe", "asys";
 553                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 554
 555                 clocks = <&infracfg CLK_INFRA_AUDIO>,
 556                          <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 557                          <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 558                          <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 559                          <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 560                          <&topckgen CLK_TOP_AUD_48K_TIMING>,
 561                          <&topckgen CLK_TOP_AUD_44K_TIMING>,
 562                          <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 563                          <&topckgen CLK_TOP_APLL_SEL>,
 564                          <&topckgen CLK_TOP_AUD1PLL_98M>,
 565                          <&topckgen CLK_TOP_AUD2PLL_90M>,
 566                          <&topckgen CLK_TOP_HADDS2PLL_98M>,
 567                          <&topckgen CLK_TOP_HADDS2PLL_294M>,
 568                          <&topckgen CLK_TOP_AUDPLL>,
 569                          <&topckgen CLK_TOP_AUDPLL_D4>,
 570                          <&topckgen CLK_TOP_AUDPLL_D8>,
 571                          <&topckgen CLK_TOP_AUDPLL_D16>,
 572                          <&topckgen CLK_TOP_AUDPLL_D24>,
 573                          <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 574                          <&clk26m>,
 575                          <&topckgen CLK_TOP_SYSPLL1_D4>,
 576                          <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 577                          <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 578                          <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 579                          <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 580                          <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 581                          <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 582                          <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 583                          <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 584                          <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 585                          <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 586                          <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 587                          <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 588                          <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 589                          <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 590                          <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 591                          <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 592                          <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 593                          <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 594                          <&topckgen CLK_TOP_ASM_M_SEL>,
 595                          <&topckgen CLK_TOP_ASM_H_SEL>,
 596                          <&topckgen CLK_TOP_UNIVPLL2_D4>,
 597                          <&topckgen CLK_TOP_UNIVPLL2_D2>,
 598                          <&topckgen CLK_TOP_SYSPLL_D5>;
 599
 600                 clock-names = "infra_sys_audio_clk",
 601                          "top_audio_mux1_sel",
 602                          "top_audio_mux2_sel",
 603                          "top_audio_mux1_div",
 604                          "top_audio_mux2_div",
 605                          "top_audio_48k_timing",
 606                          "top_audio_44k_timing",
 607                          "top_audpll_mux_sel",
 608                          "top_apll_sel",
 609                          "top_aud1_pll_98M",
 610                          "top_aud2_pll_90M",
 611                          "top_hadds2_pll_98M",
 612                          "top_hadds2_pll_294M",
 613                          "top_audpll",
 614                          "top_audpll_d4",
 615                          "top_audpll_d8",
 616                          "top_audpll_d16",
 617                          "top_audpll_d24",
 618                          "top_audintbus_sel",
 619                          "clk_26m",
 620                          "top_syspll1_d4",
 621                          "top_aud_k1_src_sel",
 622                          "top_aud_k2_src_sel",
 623                          "top_aud_k3_src_sel",
 624                          "top_aud_k4_src_sel",
 625                          "top_aud_k5_src_sel",
 626                          "top_aud_k6_src_sel",
 627                          "top_aud_k1_src_div",
 628                          "top_aud_k2_src_div",
 629                          "top_aud_k3_src_div",
 630                          "top_aud_k4_src_div",
 631                          "top_aud_k5_src_div",
 632                          "top_aud_k6_src_div",
 633                          "top_aud_i2s1_mclk",
 634                          "top_aud_i2s2_mclk",
 635                          "top_aud_i2s3_mclk",
 636                          "top_aud_i2s4_mclk",
 637                          "top_aud_i2s5_mclk",
 638                          "top_aud_i2s6_mclk",
 639                          "top_asm_m_sel",
 640                          "top_asm_h_sel",
 641                          "top_univpll2_d4",
 642                          "top_univpll2_d2",
 643                          "top_syspll_d5";
 644         };
 645
 646         mmc0: mmc@11230000 {
 647                 compatible = "mediatek,mt7623-mmc",
 648                              "mediatek,mt8135-mmc";
 649                 reg = <0 0x11230000 0 0x1000>;
 650                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 651                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 652                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 653                 clock-names = "source", "hclk";
 654                 status = "disabled";
 655         };
 656
 657         mmc1: mmc@11240000 {
 658                 compatible = "mediatek,mt7623-mmc",
 659                              "mediatek,mt8135-mmc";
 660                 reg = <0 0x11240000 0 0x1000>;
 661                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 662                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 663                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 664                 clock-names = "source", "hclk";
 665                 status = "disabled";
 666         };
 667
 668         hifsys: syscon@1a000000 {
 669                 compatible = "mediatek,mt7623-hifsys",
 670                              "mediatek,mt2701-hifsys",
 671                              "syscon";
 672                 reg = <0 0x1a000000 0 0x1000>;
 673                 #clock-cells = <1>;
 674                 #reset-cells = <1>;
 675         };
 676
 677         usb1: usb@1a1c0000 {
 678                 compatible = "mediatek,mt7623-xhci",
 679                              "mediatek,mt8173-xhci";
 680                 reg = <0 0x1a1c0000 0 0x1000>,
 681                       <0 0x1a1c4700 0 0x0100>;
 682                 reg-names = "mac", "ippc";
 683                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 684                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 685                          <&topckgen CLK_TOP_ETHIF_SEL>;
 686                 clock-names = "sys_ck", "ref_ck";
 687                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 688                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 689                 status = "disabled";
 690         };
 691
 692         u3phy1: usb-phy@1a1c4000 {
 693                 compatible = "mediatek,mt7623-u3phy",
 694                              "mediatek,mt2701-u3phy";
 695                 reg = <0 0x1a1c4000 0 0x0700>;
 696                 #address-cells = <2>;
 697                 #size-cells = <2>;
 698                 ranges;
 699                 status = "disabled";
 700
 701                 u2port0: usb-phy@1a1c4800 {
 702                         reg = <0 0x1a1c4800 0 0x0100>;
 703                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 704                         clock-names = "ref";
 705                         #phy-cells = <1>;
 706                         status = "okay";
 707                 };
 708
 709                 u3port0: usb-phy@1a1c4900 {
 710                         reg = <0 0x1a1c4900 0 0x0700>;
 711                         clocks = <&clk26m>;
 712                         clock-names = "ref";
 713                         #phy-cells = <1>;
 714                         status = "okay";
 715                 };
 716         };
 717
 718         usb2: usb@1a240000 {
 719                 compatible = "mediatek,mt7623-xhci",
 720                              "mediatek,mt8173-xhci";
 721                 reg = <0 0x1a240000 0 0x1000>,
 722                       <0 0x1a244700 0 0x0100>;
 723                 reg-names = "mac", "ippc";
 724                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 725                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 726                          <&topckgen CLK_TOP_ETHIF_SEL>;
 727                 clock-names = "sys_ck", "ref_ck";
 728                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 729                 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 730                 status = "disabled";
 731         };
 732
 733         u3phy2: usb-phy@1a244000 {
 734                 compatible = "mediatek,mt7623-u3phy",
 735                              "mediatek,mt2701-u3phy";
 736                 reg = <0 0x1a244000 0 0x0700>;
 737                 #address-cells = <2>;
 738                 #size-cells = <2>;
 739                 ranges;
 740                 status = "disabled";
 741
 742                 u2port1: usb-phy@1a244800 {
 743                         reg = <0 0x1a244800 0 0x0100>;
 744                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 745                         clock-names = "ref";
 746                         #phy-cells = <1>;
 747                         status = "okay";
 748                 };
 749
 750                 u3port1: usb-phy@1a244900 {
 751                         reg = <0 0x1a244900 0 0x0700>;
 752                         clocks = <&clk26m>;
 753                         clock-names = "ref";
 754                         #phy-cells = <1>;
 755                         status = "okay";
 756                 };
 757         };
 758
 759         ethsys: syscon@1b000000 {
 760                 compatible = "mediatek,mt7623-ethsys",
 761                              "mediatek,mt2701-ethsys",
 762                              "syscon";
 763                 reg = <0 0x1b000000 0 0x1000>;
 764                 #clock-cells = <1>;
 765                 #reset-cells = <1>;
 766         };
 767
 768         eth: ethernet@1b100000 {
 769                 compatible = "mediatek,mt7623-eth",
 770                              "mediatek,mt2701-eth",
 771                              "syscon";
 772                 reg = <0 0x1b100000 0 0x20000>;
 773                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 774                              <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 775                              <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 776                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 777                          <&ethsys CLK_ETHSYS_ESW>,
 778                          <&ethsys CLK_ETHSYS_GP1>,
 779                          <&ethsys CLK_ETHSYS_GP2>,
 780                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 781                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 782                 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
 783                          <&ethsys MT2701_ETHSYS_GMAC_RST>,
 784                          <&ethsys MT2701_ETHSYS_PPE_RST>;
 785                 reset-names = "fe", "gmac", "ppe";
 786                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 787                 mediatek,ethsys = <&ethsys>;
 788                 mediatek,pctl = <&syscfg_pctl_a>;
 789                 #address-cells = <1>;
 790                 #size-cells = <0>;
 791                 status = "disabled";
 792         };
 793
 794         crypto: crypto@1b240000 {
 795                 compatible = "mediatek,eip97-crypto";
 796                 reg = <0 0x1b240000 0 0x20000>;
 797                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
 798                              <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
 799                              <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
 800                              <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
 801                              <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
 802                 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
 803                 clock-names = "cryp";
 804                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 805                 status = "disabled";
 806         };
 807 };