2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
15 #include "skeleton.dtsi"
18 compatible = "ti,omap3430", "ti,omap3";
19 interrupt-parent = <&intc>;
35 compatible = "arm,cortex-a8";
42 clock-latency = <300000>; /* From omap-cpufreq driver */
47 compatible = "arm,cortex-a8-pmu";
48 reg = <0x54000000 0x800000>;
50 ti,hwmods = "debugss";
54 * The soc node represents the soc top level view. It is used for IPs
55 * that are not memory mapped in the MPU view or for the MPU itself.
58 compatible = "ti,omap-infra";
60 compatible = "ti,omap3-mpu";
65 compatible = "ti,iva2.2";
69 compatible = "ti,omap3-c64";
75 * XXX: Use a flat representation of the OMAP3 interconnect.
76 * The real OMAP interconnect network is quite complex.
77 * Since it will not bring real advantage to represent that in DT for
78 * the moment, just use a fake OCP bus entry to represent the whole bus
82 compatible = "ti,omap3-l3-smx", "simple-bus";
83 reg = <0x68000000 0x10000>;
88 ti,hwmods = "l3_main";
90 l4_core: l4@48000000 {
91 compatible = "ti,omap3-l4-core", "simple-bus";
94 ranges = <0 0x48000000 0x1000000>;
97 compatible = "ti,omap3-scm", "simple-bus";
98 reg = <0x2000 0x2000>;
101 ranges = <0 0x2000 0x2000>;
103 omap3_pmx_core: pinmux@30 {
104 compatible = "ti,omap3-padconf",
107 #address-cells = <1>;
109 #interrupt-cells = <1>;
110 interrupt-controller;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0xff1f>;
115 scm_conf: scm_conf@270 {
116 compatible = "syscon";
118 #address-cells = <1>;
122 #address-cells = <1>;
127 scm_clockdomains: clockdomains {
130 omap3_pmx_wkup: pinmux@a00 {
131 compatible = "ti,omap3-padconf",
134 #address-cells = <1>;
136 #interrupt-cells = <1>;
137 interrupt-controller;
138 pinctrl-single,register-width = <16>;
139 pinctrl-single,function-mask = <0xff1f>;
145 compatible = "ti,omap3-aes";
147 reg = <0x480c5000 0x50>;
149 dmas = <&sdma 65 &sdma 66>;
150 dma-names = "tx", "rx";
154 compatible = "ti,omap3-prm";
155 reg = <0x48306000 0x4000>;
159 #address-cells = <1>;
163 prm_clockdomains: clockdomains {
168 compatible = "ti,omap3-cm";
169 reg = <0x48004000 0x4000>;
172 #address-cells = <1>;
176 cm_clockdomains: clockdomains {
180 counter32k: counter@48320000 {
181 compatible = "ti,omap-counter32k";
182 reg = <0x48320000 0x20>;
183 ti,hwmods = "counter_32k";
186 intc: interrupt-controller@48200000 {
187 compatible = "ti,omap3-intc";
188 interrupt-controller;
189 #interrupt-cells = <1>;
190 reg = <0x48200000 0x1000>;
193 sdma: dma-controller@48056000 {
194 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
195 reg = <0x48056000 0x1000>;
205 pbias_regulator: pbias_regulator {
206 compatible = "ti,pbias-omap";
208 syscon = <&scm_conf>;
209 pbias_mmc_reg: pbias_mmc_omap2430 {
210 regulator-name = "pbias_mmc_omap2430";
211 regulator-min-microvolt = <1800000>;
212 regulator-max-microvolt = <3000000>;
216 gpio1: gpio@48310000 {
217 compatible = "ti,omap3-gpio";
218 reg = <0x48310000 0x200>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
228 gpio2: gpio@49050000 {
229 compatible = "ti,omap3-gpio";
230 reg = <0x49050000 0x200>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
239 gpio3: gpio@49052000 {
240 compatible = "ti,omap3-gpio";
241 reg = <0x49052000 0x200>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
250 gpio4: gpio@49054000 {
251 compatible = "ti,omap3-gpio";
252 reg = <0x49054000 0x200>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
261 gpio5: gpio@49056000 {
262 compatible = "ti,omap3-gpio";
263 reg = <0x49056000 0x200>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
272 gpio6: gpio@49058000 {
273 compatible = "ti,omap3-gpio";
274 reg = <0x49058000 0x200>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
283 uart1: serial@4806a000 {
284 compatible = "ti,omap3-uart";
285 reg = <0x4806a000 0x2000>;
286 interrupts-extended = <&intc 72>;
287 dmas = <&sdma 49 &sdma 50>;
288 dma-names = "tx", "rx";
290 clock-frequency = <48000000>;
293 uart2: serial@4806c000 {
294 compatible = "ti,omap3-uart";
295 reg = <0x4806c000 0x400>;
296 interrupts-extended = <&intc 73>;
297 dmas = <&sdma 51 &sdma 52>;
298 dma-names = "tx", "rx";
300 clock-frequency = <48000000>;
303 uart3: serial@49020000 {
304 compatible = "ti,omap3-uart";
305 reg = <0x49020000 0x400>;
306 interrupts-extended = <&intc 74>;
307 dmas = <&sdma 53 &sdma 54>;
308 dma-names = "tx", "rx";
310 clock-frequency = <48000000>;
314 compatible = "ti,omap3-i2c";
315 reg = <0x48070000 0x80>;
317 dmas = <&sdma 27 &sdma 28>;
318 dma-names = "tx", "rx";
319 #address-cells = <1>;
325 compatible = "ti,omap3-i2c";
326 reg = <0x48072000 0x80>;
328 dmas = <&sdma 29 &sdma 30>;
329 dma-names = "tx", "rx";
330 #address-cells = <1>;
336 compatible = "ti,omap3-i2c";
337 reg = <0x48060000 0x80>;
339 dmas = <&sdma 25 &sdma 26>;
340 dma-names = "tx", "rx";
341 #address-cells = <1>;
346 mailbox: mailbox@48094000 {
347 compatible = "ti,omap3-mailbox";
348 ti,hwmods = "mailbox";
349 reg = <0x48094000 0x200>;
352 ti,mbox-num-users = <2>;
353 ti,mbox-num-fifos = <2>;
355 ti,mbox-tx = <0 0 0>;
356 ti,mbox-rx = <1 0 0>;
360 mcspi1: spi@48098000 {
361 compatible = "ti,omap2-mcspi";
362 reg = <0x48098000 0x100>;
364 #address-cells = <1>;
366 ti,hwmods = "mcspi1";
376 dma-names = "tx0", "rx0", "tx1", "rx1",
377 "tx2", "rx2", "tx3", "rx3";
380 mcspi2: spi@4809a000 {
381 compatible = "ti,omap2-mcspi";
382 reg = <0x4809a000 0x100>;
384 #address-cells = <1>;
386 ti,hwmods = "mcspi2";
392 dma-names = "tx0", "rx0", "tx1", "rx1";
395 mcspi3: spi@480b8000 {
396 compatible = "ti,omap2-mcspi";
397 reg = <0x480b8000 0x100>;
399 #address-cells = <1>;
401 ti,hwmods = "mcspi3";
407 dma-names = "tx0", "rx0", "tx1", "rx1";
410 mcspi4: spi@480ba000 {
411 compatible = "ti,omap2-mcspi";
412 reg = <0x480ba000 0x100>;
414 #address-cells = <1>;
416 ti,hwmods = "mcspi4";
418 dmas = <&sdma 70>, <&sdma 71>;
419 dma-names = "tx0", "rx0";
422 hdqw1w: 1w@480b2000 {
423 compatible = "ti,omap3-1w";
424 reg = <0x480b2000 0x1000>;
430 compatible = "ti,omap3-hsmmc";
431 reg = <0x4809c000 0x200>;
435 dmas = <&sdma 61>, <&sdma 62>;
436 dma-names = "tx", "rx";
437 pbias-supply = <&pbias_mmc_reg>;
441 compatible = "ti,omap3-hsmmc";
442 reg = <0x480b4000 0x200>;
445 dmas = <&sdma 47>, <&sdma 48>;
446 dma-names = "tx", "rx";
450 compatible = "ti,omap3-hsmmc";
451 reg = <0x480ad000 0x200>;
454 dmas = <&sdma 77>, <&sdma 78>;
455 dma-names = "tx", "rx";
458 mmu_isp: mmu@480bd400 {
459 compatible = "ti,omap2-iommu";
460 reg = <0x480bd400 0x80>;
462 ti,hwmods = "mmu_isp";
463 ti,#tlb-entries = <8>;
466 mmu_iva: mmu@5d000000 {
467 compatible = "ti,omap2-iommu";
468 reg = <0x5d000000 0x80>;
470 ti,hwmods = "mmu_iva";
475 compatible = "ti,omap3-wdt";
476 reg = <0x48314000 0x80>;
477 ti,hwmods = "wd_timer2";
480 mcbsp1: mcbsp@48074000 {
481 compatible = "ti,omap3-mcbsp";
482 reg = <0x48074000 0xff>;
484 interrupts = <16>, /* OCP compliant interrupt */
485 <59>, /* TX interrupt */
486 <60>; /* RX interrupt */
487 interrupt-names = "common", "tx", "rx";
488 ti,buffer-size = <128>;
489 ti,hwmods = "mcbsp1";
492 dma-names = "tx", "rx";
496 mcbsp2: mcbsp@49022000 {
497 compatible = "ti,omap3-mcbsp";
498 reg = <0x49022000 0xff>,
500 reg-names = "mpu", "sidetone";
501 interrupts = <17>, /* OCP compliant interrupt */
502 <62>, /* TX interrupt */
503 <63>, /* RX interrupt */
505 interrupt-names = "common", "tx", "rx", "sidetone";
506 ti,buffer-size = <1280>;
507 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
510 dma-names = "tx", "rx";
514 mcbsp3: mcbsp@49024000 {
515 compatible = "ti,omap3-mcbsp";
516 reg = <0x49024000 0xff>,
518 reg-names = "mpu", "sidetone";
519 interrupts = <22>, /* OCP compliant interrupt */
520 <89>, /* TX interrupt */
521 <90>, /* RX interrupt */
523 interrupt-names = "common", "tx", "rx", "sidetone";
524 ti,buffer-size = <128>;
525 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
528 dma-names = "tx", "rx";
532 mcbsp4: mcbsp@49026000 {
533 compatible = "ti,omap3-mcbsp";
534 reg = <0x49026000 0xff>;
536 interrupts = <23>, /* OCP compliant interrupt */
537 <54>, /* TX interrupt */
538 <55>; /* RX interrupt */
539 interrupt-names = "common", "tx", "rx";
540 ti,buffer-size = <128>;
541 ti,hwmods = "mcbsp4";
544 dma-names = "tx", "rx";
548 mcbsp5: mcbsp@48096000 {
549 compatible = "ti,omap3-mcbsp";
550 reg = <0x48096000 0xff>;
552 interrupts = <27>, /* OCP compliant interrupt */
553 <81>, /* TX interrupt */
554 <82>; /* RX interrupt */
555 interrupt-names = "common", "tx", "rx";
556 ti,buffer-size = <128>;
557 ti,hwmods = "mcbsp5";
560 dma-names = "tx", "rx";
564 sham: sham@480c3000 {
565 compatible = "ti,omap3-sham";
567 reg = <0x480c3000 0x64>;
573 smartreflex_core: smartreflex@480cb000 {
574 compatible = "ti,omap3-smartreflex-core";
575 ti,hwmods = "smartreflex_core";
576 reg = <0x480cb000 0x400>;
580 smartreflex_mpu_iva: smartreflex@480c9000 {
581 compatible = "ti,omap3-smartreflex-iva";
582 ti,hwmods = "smartreflex_mpu_iva";
583 reg = <0x480c9000 0x400>;
587 timer1: timer@48318000 {
588 compatible = "ti,omap3430-timer";
589 reg = <0x48318000 0x400>;
591 ti,hwmods = "timer1";
595 timer2: timer@49032000 {
596 compatible = "ti,omap3430-timer";
597 reg = <0x49032000 0x400>;
599 ti,hwmods = "timer2";
602 timer3: timer@49034000 {
603 compatible = "ti,omap3430-timer";
604 reg = <0x49034000 0x400>;
606 ti,hwmods = "timer3";
609 timer4: timer@49036000 {
610 compatible = "ti,omap3430-timer";
611 reg = <0x49036000 0x400>;
613 ti,hwmods = "timer4";
616 timer5: timer@49038000 {
617 compatible = "ti,omap3430-timer";
618 reg = <0x49038000 0x400>;
620 ti,hwmods = "timer5";
624 timer6: timer@4903a000 {
625 compatible = "ti,omap3430-timer";
626 reg = <0x4903a000 0x400>;
628 ti,hwmods = "timer6";
632 timer7: timer@4903c000 {
633 compatible = "ti,omap3430-timer";
634 reg = <0x4903c000 0x400>;
636 ti,hwmods = "timer7";
640 timer8: timer@4903e000 {
641 compatible = "ti,omap3430-timer";
642 reg = <0x4903e000 0x400>;
644 ti,hwmods = "timer8";
649 timer9: timer@49040000 {
650 compatible = "ti,omap3430-timer";
651 reg = <0x49040000 0x400>;
653 ti,hwmods = "timer9";
657 timer10: timer@48086000 {
658 compatible = "ti,omap3430-timer";
659 reg = <0x48086000 0x400>;
661 ti,hwmods = "timer10";
665 timer11: timer@48088000 {
666 compatible = "ti,omap3430-timer";
667 reg = <0x48088000 0x400>;
669 ti,hwmods = "timer11";
673 timer12: timer@48304000 {
674 compatible = "ti,omap3430-timer";
675 reg = <0x48304000 0x400>;
677 ti,hwmods = "timer12";
682 usbhstll: usbhstll@48062000 {
683 compatible = "ti,usbhs-tll";
684 reg = <0x48062000 0x1000>;
686 ti,hwmods = "usb_tll_hs";
689 usbhshost: usbhshost@48064000 {
690 compatible = "ti,usbhs-host";
691 reg = <0x48064000 0x400>;
692 ti,hwmods = "usb_host_hs";
693 #address-cells = <1>;
697 usbhsohci: ohci@48064400 {
698 compatible = "ti,ohci-omap3";
699 reg = <0x48064400 0x400>;
700 interrupt-parent = <&intc>;
704 usbhsehci: ehci@48064800 {
705 compatible = "ti,ehci-omap";
706 reg = <0x48064800 0x400>;
707 interrupt-parent = <&intc>;
712 gpmc: gpmc@6e000000 {
713 compatible = "ti,omap3430-gpmc";
715 reg = <0x6e000000 0x02d0>;
718 gpmc,num-waitpins = <4>;
719 #address-cells = <2>;
723 usb_otg_hs: usb_otg_hs@480ab000 {
724 compatible = "ti,omap3-musb";
725 reg = <0x480ab000 0x1000>;
726 interrupts = <92>, <93>;
727 interrupt-names = "mc", "dma";
728 ti,hwmods = "usb_otg_hs";
735 compatible = "ti,omap3-dss";
736 reg = <0x48050000 0x200>;
738 ti,hwmods = "dss_core";
739 clocks = <&dss1_alwon_fck>;
741 #address-cells = <1>;
746 compatible = "ti,omap3-dispc";
747 reg = <0x48050400 0x400>;
749 ti,hwmods = "dss_dispc";
750 clocks = <&dss1_alwon_fck>;
754 dsi: encoder@4804fc00 {
755 compatible = "ti,omap3-dsi";
756 reg = <0x4804fc00 0x200>,
759 reg-names = "proto", "phy", "pll";
762 ti,hwmods = "dss_dsi1";
763 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
764 clock-names = "fck", "sys_clk";
767 rfbi: encoder@48050800 {
768 compatible = "ti,omap3-rfbi";
769 reg = <0x48050800 0x100>;
771 ti,hwmods = "dss_rfbi";
772 clocks = <&dss1_alwon_fck>, <&dss_ick>;
773 clock-names = "fck", "ick";
776 venc: encoder@48050c00 {
777 compatible = "ti,omap3-venc";
778 reg = <0x48050c00 0x100>;
780 ti,hwmods = "dss_venc";
781 clocks = <&dss_tv_fck>;
786 ssi: ssi-controller@48058000 {
787 compatible = "ti,omap3-ssi";
792 reg = <0x48058000 0x1000>,
798 interrupt-names = "gdd_mpu";
800 #address-cells = <1>;
804 ssi_port1: ssi-port@4805a000 {
805 compatible = "ti,omap3-ssi-port";
807 reg = <0x4805a000 0x800>,
812 interrupt-parent = <&intc>;
817 ssi_port2: ssi-port@4805b000 {
818 compatible = "ti,omap3-ssi-port";
820 reg = <0x4805b000 0x800>,
825 interrupt-parent = <&intc>;
833 /include/ "omap3xxx-clocks.dtsi"