arch/arm/boot/dts/omap3430es1-clocks.dtsi

   1 /*
   2  * Device Tree Source for OMAP3430 ES1 clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &cm_clocks {
  11         gfx_l3_ck: gfx_l3_ck@b10 {
  12                 #clock-cells = <0>;
  13                 compatible = "ti,wait-gate-clock";
  14                 clocks = <&l3_ick>;
  15                 reg = <0x0b10>;
  16                 ti,bit-shift = <0>;
  17         };
  18
  19         gfx_l3_fck: gfx_l3_fck@b40 {
  20                 #clock-cells = <0>;
  21                 compatible = "ti,divider-clock";
  22                 clocks = <&l3_ick>;
  23                 ti,max-div = <7>;
  24                 reg = <0x0b40>;
  25                 ti,index-starts-at-one;
  26         };
  27
  28         gfx_l3_ick: gfx_l3_ick {
  29                 #clock-cells = <0>;
  30                 compatible = "fixed-factor-clock";
  31                 clocks = <&gfx_l3_ck>;
  32                 clock-mult = <1>;
  33                 clock-div = <1>;
  34         };
  35
  36         gfx_cg1_ck: gfx_cg1_ck@b00 {
  37                 #clock-cells = <0>;
  38                 compatible = "ti,wait-gate-clock";
  39                 clocks = <&gfx_l3_fck>;
  40                 reg = <0x0b00>;
  41                 ti,bit-shift = <1>;
  42         };
  43
  44         gfx_cg2_ck: gfx_cg2_ck@b00 {
  45                 #clock-cells = <0>;
  46                 compatible = "ti,wait-gate-clock";
  47                 clocks = <&gfx_l3_fck>;
  48                 reg = <0x0b00>;
  49                 ti,bit-shift = <2>;
  50         };
  51
  52         d2d_26m_fck: d2d_26m_fck@a00 {
  53                 #clock-cells = <0>;
  54                 compatible = "ti,wait-gate-clock";
  55                 clocks = <&sys_ck>;
  56                 reg = <0x0a00>;
  57                 ti,bit-shift = <3>;
  58         };
  59
  60         fshostusb_fck: fshostusb_fck@a00 {
  61                 #clock-cells = <0>;
  62                 compatible = "ti,wait-gate-clock";
  63                 clocks = <&core_48m_fck>;
  64                 reg = <0x0a00>;
  65                 ti,bit-shift = <5>;
  66         };
  67
  68         ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 {
  69                 #clock-cells = <0>;
  70                 compatible = "ti,composite-no-wait-gate-clock";
  71                 clocks = <&corex2_fck>;
  72                 ti,bit-shift = <0>;
  73                 reg = <0x0a00>;
  74         };
  75
  76         ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {
  77                 #clock-cells = <0>;
  78                 compatible = "ti,composite-divider-clock";
  79                 clocks = <&corex2_fck>;
  80                 ti,bit-shift = <8>;
  81                 reg = <0x0a40>;
  82                 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
  83         };
  84
  85         ssi_ssr_fck: ssi_ssr_fck_3430es1 {
  86                 #clock-cells = <0>;
  87                 compatible = "ti,composite-clock";
  88                 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
  89         };
  90
  91         ssi_sst_fck: ssi_sst_fck_3430es1 {
  92                 #clock-cells = <0>;
  93                 compatible = "fixed-factor-clock";
  94                 clocks = <&ssi_ssr_fck>;
  95                 clock-mult = <1>;
  96                 clock-div = <2>;
  97         };
  98
  99         hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 {
 100                 #clock-cells = <0>;
 101                 compatible = "ti,omap3-no-wait-interface-clock";
 102                 clocks = <&core_l3_ick>;
 103                 reg = <0x0a10>;
 104                 ti,bit-shift = <4>;
 105         };
 106
 107         fac_ick: fac_ick@a10 {
 108                 #clock-cells = <0>;
 109                 compatible = "ti,omap3-interface-clock";
 110                 clocks = <&core_l4_ick>;
 111                 reg = <0x0a10>;
 112                 ti,bit-shift = <8>;
 113         };
 114
 115         ssi_l4_ick: ssi_l4_ick {
 116                 #clock-cells = <0>;
 117                 compatible = "fixed-factor-clock";
 118                 clocks = <&l4_ick>;
 119                 clock-mult = <1>;
 120                 clock-div = <1>;
 121         };
 122
 123         ssi_ick: ssi_ick_3430es1@a10 {
 124                 #clock-cells = <0>;
 125                 compatible = "ti,omap3-no-wait-interface-clock";
 126                 clocks = <&ssi_l4_ick>;
 127                 reg = <0x0a10>;
 128                 ti,bit-shift = <0>;
 129         };
 130
 131         usb_l4_gate_ick: usb_l4_gate_ick@a10 {
 132                 #clock-cells = <0>;
 133                 compatible = "ti,composite-interface-clock";
 134                 clocks = <&l4_ick>;
 135                 ti,bit-shift = <5>;
 136                 reg = <0x0a10>;
 137         };
 138
 139         usb_l4_div_ick: usb_l4_div_ick@a40 {
 140                 #clock-cells = <0>;
 141                 compatible = "ti,composite-divider-clock";
 142                 clocks = <&l4_ick>;
 143                 ti,bit-shift = <4>;
 144                 ti,max-div = <1>;
 145                 reg = <0x0a40>;
 146                 ti,index-starts-at-one;
 147         };
 148
 149         usb_l4_ick: usb_l4_ick {
 150                 #clock-cells = <0>;
 151                 compatible = "ti,composite-clock";
 152                 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
 153         };
 154
 155         dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 {
 156                 #clock-cells = <0>;
 157                 compatible = "ti,gate-clock";
 158                 clocks = <&dpll4_m4x2_ck>;
 159                 ti,bit-shift = <0>;
 160                 reg = <0x0e00>;
 161                 ti,set-rate-parent;
 162         };
 163
 164         dss_ick: dss_ick_3430es1@e10 {
 165                 #clock-cells = <0>;
 166                 compatible = "ti,omap3-no-wait-interface-clock";
 167                 clocks = <&l4_ick>;
 168                 reg = <0x0e10>;
 169                 ti,bit-shift = <0>;
 170         };
 171 };
 172
 173 &cm_clockdomains {
 174         core_l3_clkdm: core_l3_clkdm {
 175                 compatible = "ti,clockdomain";
 176                 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
 177         };
 178
 179         gfx_3430es1_clkdm: gfx_3430es1_clkdm {
 180                 compatible = "ti,clockdomain";
 181                 clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
 182         };
 183
 184         dss_clkdm: dss_clkdm {
 185                 compatible = "ti,clockdomain";
 186                 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
 187                          <&dss1_alwon_fck>, <&dss_ick>;
 188         };
 189
 190         d2d_clkdm: d2d_clkdm {
 191                 compatible = "ti,clockdomain";
 192                 clocks = <&d2d_26m_fck>;
 193         };
 194
 195         core_l4_clkdm: core_l4_clkdm {
 196                 compatible = "ti,clockdomain";
 197                 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
 198                          <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
 199                          <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
 200                          <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
 201                          <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
 202                          <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
 203                          <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
 204                          <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
 205                          <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
 206                          <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
 207         };
 208 };