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ARM: dts: Add missing hwmods property for omap4 dma
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / omap4.dtsi
1 /*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12
13 / {
14 compatible = "ti,omap4430", "ti,omap4";
15 interrupt-parent = <&wakeupgen>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18 chosen { };
19
20 aliases {
21 i2c0 = &i2c1;
22 i2c1 = &i2c2;
23 i2c2 = &i2c3;
24 i2c3 = &i2c4;
25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
28 serial3 = &uart4;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 device_type = "cpu";
38 next-level-cache = <&L2>;
39 reg = <0x0>;
40
41 clocks = <&dpll_mpu_ck>;
42 clock-names = "cpu";
43
44 clock-latency = <300000>; /* From omap-cpufreq driver */
45 };
46 cpu@1 {
47 compatible = "arm,cortex-a9";
48 device_type = "cpu";
49 next-level-cache = <&L2>;
50 reg = <0x1>;
51 };
52 };
53
54 /*
55 * Note that 4430 needs cross trigger interface (CTI) supported
56 * before we can configure the interrupts. This means sampling
57 * events are not supported for pmu. Note that 4460 does not use
58 * CTI, see also 4460.dtsi.
59 */
60 pmu {
61 compatible = "arm,cortex-a9-pmu";
62 ti,hwmods = "debugss";
63 };
64
65 gic: interrupt-controller@48241000 {
66 compatible = "arm,cortex-a9-gic";
67 interrupt-controller;
68 #interrupt-cells = <3>;
69 reg = <0x48241000 0x1000>,
70 <0x48240100 0x0100>;
71 interrupt-parent = <&gic>;
72 };
73
74 L2: l2-cache-controller@48242000 {
75 compatible = "arm,pl310-cache";
76 reg = <0x48242000 0x1000>;
77 cache-unified;
78 cache-level = <2>;
79 };
80
81 local-timer@48240600 {
82 compatible = "arm,cortex-a9-twd-timer";
83 clocks = <&mpu_periphclk>;
84 reg = <0x48240600 0x20>;
85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
86 interrupt-parent = <&gic>;
87 };
88
89 wakeupgen: interrupt-controller@48281000 {
90 compatible = "ti,omap4-wugen-mpu";
91 interrupt-controller;
92 #interrupt-cells = <3>;
93 reg = <0x48281000 0x1000>;
94 interrupt-parent = <&gic>;
95 };
96
97 /*
98 * The soc node represents the soc top level view. It is used for IPs
99 * that are not memory mapped in the MPU view or for the MPU itself.
100 */
101 soc {
102 compatible = "ti,omap-infra";
103 mpu {
104 compatible = "ti,omap4-mpu";
105 ti,hwmods = "mpu";
106 sram = <&ocmcram>;
107 };
108
109 dsp {
110 compatible = "ti,omap3-c64";
111 ti,hwmods = "dsp";
112 };
113
114 iva {
115 compatible = "ti,ivahd";
116 ti,hwmods = "iva";
117 };
118 };
119
120 /*
121 * XXX: Use a flat representation of the OMAP4 interconnect.
122 * The real OMAP interconnect network is quite complex.
123 * Since it will not bring real advantage to represent that in DT for
124 * the moment, just use a fake OCP bus entry to represent the whole bus
125 * hierarchy.
126 */
127 ocp {
128 compatible = "ti,omap4-l3-noc", "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
131 ranges;
132 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
133 reg = <0x44000000 0x1000>,
134 <0x44800000 0x2000>,
135 <0x45000000 0x1000>;
136 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
138
139 l4_cfg: l4@4a000000 {
140 compatible = "ti,omap4-l4-cfg", "simple-bus";
141 #address-cells = <1>;
142 #size-cells = <1>;
143 ranges = <0 0x4a000000 0x1000000>;
144
145 cm1: cm1@4000 {
146 compatible = "ti,omap4-cm1";
147 reg = <0x4000 0x2000>;
148
149 cm1_clocks: clocks {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 };
153
154 cm1_clockdomains: clockdomains {
155 };
156 };
157
158 cm2: cm2@8000 {
159 compatible = "ti,omap4-cm2";
160 reg = <0x8000 0x3000>;
161
162 cm2_clocks: clocks {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 };
166
167 cm2_clockdomains: clockdomains {
168 };
169 };
170
171 omap4_scm_core: scm@2000 {
172 compatible = "ti,omap4-scm-core", "simple-bus";
173 reg = <0x2000 0x1000>;
174 #address-cells = <1>;
175 #size-cells = <1>;
176 ranges = <0 0x2000 0x1000>;
177 ti,hwmods = "ctrl_module_core";
178
179 scm_conf: scm_conf@0 {
180 compatible = "syscon";
181 reg = <0x0 0x800>;
182 #address-cells = <1>;
183 #size-cells = <1>;
184 };
185 };
186
187 omap4_padconf_core: scm@100000 {
188 compatible = "ti,omap4-scm-padconf-core",
189 "simple-bus";
190 reg = <0x100000 0x1000>;
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges = <0 0x100000 0x1000>;
194 ti,hwmods = "ctrl_module_pad_core";
195
196 omap4_pmx_core: pinmux@40 {
197 compatible = "ti,omap4-padconf",
198 "pinctrl-single";
199 reg = <0x40 0x0196>;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 #pinctrl-cells = <1>;
203 #interrupt-cells = <1>;
204 interrupt-controller;
205 pinctrl-single,register-width = <16>;
206 pinctrl-single,function-mask = <0x7fff>;
207 };
208
209 omap4_padconf_global: omap4_padconf_global@5a0 {
210 compatible = "syscon",
211 "simple-bus";
212 reg = <0x5a0 0x170>;
213 #address-cells = <1>;
214 #size-cells = <1>;
215 ranges = <0 0x5a0 0x170>;
216
217 pbias_regulator: pbias_regulator@60 {
218 compatible = "ti,pbias-omap4", "ti,pbias-omap";
219 reg = <0x60 0x4>;
220 syscon = <&omap4_padconf_global>;
221 pbias_mmc_reg: pbias_mmc_omap4 {
222 regulator-name = "pbias_mmc_omap4";
223 regulator-min-microvolt = <1800000>;
224 regulator-max-microvolt = <3000000>;
225 };
226 };
227 };
228 };
229
230 l4_wkup: l4@300000 {
231 compatible = "ti,omap4-l4-wkup", "simple-bus";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges = <0 0x300000 0x40000>;
235
236 counter32k: counter@4000 {
237 compatible = "ti,omap-counter32k";
238 reg = <0x4000 0x20>;
239 ti,hwmods = "counter_32k";
240 };
241
242 prm: prm@6000 {
243 compatible = "ti,omap4-prm";
244 reg = <0x6000 0x3000>;
245 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
246
247 prm_clocks: clocks {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 };
251
252 prm_clockdomains: clockdomains {
253 };
254 };
255
256 scrm: scrm@a000 {
257 compatible = "ti,omap4-scrm";
258 reg = <0xa000 0x2000>;
259
260 scrm_clocks: clocks {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 };
264
265 scrm_clockdomains: clockdomains {
266 };
267 };
268
269 omap4_scm_wkup: scm@c000 {
270 compatible = "ti,omap4-scm-wkup";
271 reg = <0xc000 0x1000>;
272 ti,hwmods = "ctrl_module_wkup";
273 };
274
275 omap4_padconf_wkup: padconf@1e000 {
276 compatible = "ti,omap4-scm-padconf-wkup",
277 "simple-bus";
278 reg = <0x1e000 0x1000>;
279 #address-cells = <1>;
280 #size-cells = <1>;
281 ranges = <0 0x1e000 0x1000>;
282 ti,hwmods = "ctrl_module_pad_wkup";
283
284 omap4_pmx_wkup: pinmux@40 {
285 compatible = "ti,omap4-padconf",
286 "pinctrl-single";
287 reg = <0x40 0x0038>;
288 #address-cells = <1>;
289 #size-cells = <0>;
290 #pinctrl-cells = <1>;
291 #interrupt-cells = <1>;
292 interrupt-controller;
293 pinctrl-single,register-width = <16>;
294 pinctrl-single,function-mask = <0x7fff>;
295 };
296 };
297 };
298 };
299
300 ocmcram: ocmcram@40304000 {
301 compatible = "mmio-sram";
302 reg = <0x40304000 0xa000>; /* 40k */
303 };
304
305 sdma: dma-controller@4a056000 {
306 compatible = "ti,omap4430-sdma";
307 reg = <0x4a056000 0x1000>;
308 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
312 #dma-cells = <1>;
313 dma-channels = <32>;
314 dma-requests = <127>;
315 ti,hwmods = "dma_system";
316 };
317
318 gpio1: gpio@4a310000 {
319 compatible = "ti,omap4-gpio";
320 reg = <0x4a310000 0x200>;
321 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
322 ti,hwmods = "gpio1";
323 ti,gpio-always-on;
324 gpio-controller;
325 #gpio-cells = <2>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
328 };
329
330 gpio2: gpio@48055000 {
331 compatible = "ti,omap4-gpio";
332 reg = <0x48055000 0x200>;
333 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
334 ti,hwmods = "gpio2";
335 gpio-controller;
336 #gpio-cells = <2>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
339 };
340
341 gpio3: gpio@48057000 {
342 compatible = "ti,omap4-gpio";
343 reg = <0x48057000 0x200>;
344 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
345 ti,hwmods = "gpio3";
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 };
351
352 gpio4: gpio@48059000 {
353 compatible = "ti,omap4-gpio";
354 reg = <0x48059000 0x200>;
355 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
356 ti,hwmods = "gpio4";
357 gpio-controller;
358 #gpio-cells = <2>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
361 };
362
363 gpio5: gpio@4805b000 {
364 compatible = "ti,omap4-gpio";
365 reg = <0x4805b000 0x200>;
366 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
367 ti,hwmods = "gpio5";
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 };
373
374 gpio6: gpio@4805d000 {
375 compatible = "ti,omap4-gpio";
376 reg = <0x4805d000 0x200>;
377 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
378 ti,hwmods = "gpio6";
379 gpio-controller;
380 #gpio-cells = <2>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
383 };
384
385 elm: elm@48078000 {
386 compatible = "ti,am3352-elm";
387 reg = <0x48078000 0x2000>;
388 interrupts = <4>;
389 ti,hwmods = "elm";
390 status = "disabled";
391 };
392
393 gpmc: gpmc@50000000 {
394 compatible = "ti,omap4430-gpmc";
395 reg = <0x50000000 0x1000>;
396 #address-cells = <2>;
397 #size-cells = <1>;
398 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
399 dmas = <&sdma 4>;
400 dma-names = "rxtx";
401 gpmc,num-cs = <8>;
402 gpmc,num-waitpins = <4>;
403 ti,hwmods = "gpmc";
404 ti,no-idle-on-init;
405 clocks = <&l3_div_ck>;
406 clock-names = "fck";
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 gpio-controller;
410 #gpio-cells = <2>;
411 };
412
413 uart1: serial@4806a000 {
414 compatible = "ti,omap4-uart";
415 reg = <0x4806a000 0x100>;
416 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
417 ti,hwmods = "uart1";
418 clock-frequency = <48000000>;
419 };
420
421 uart2: serial@4806c000 {
422 compatible = "ti,omap4-uart";
423 reg = <0x4806c000 0x100>;
424 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
425 ti,hwmods = "uart2";
426 clock-frequency = <48000000>;
427 };
428
429 uart3: serial@48020000 {
430 compatible = "ti,omap4-uart";
431 reg = <0x48020000 0x100>;
432 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
433 ti,hwmods = "uart3";
434 clock-frequency = <48000000>;
435 };
436
437 uart4: serial@4806e000 {
438 compatible = "ti,omap4-uart";
439 reg = <0x4806e000 0x100>;
440 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
441 ti,hwmods = "uart4";
442 clock-frequency = <48000000>;
443 };
444
445 hwspinlock: spinlock@4a0f6000 {
446 compatible = "ti,omap4-hwspinlock";
447 reg = <0x4a0f6000 0x1000>;
448 ti,hwmods = "spinlock";
449 #hwlock-cells = <1>;
450 };
451
452 i2c1: i2c@48070000 {
453 compatible = "ti,omap4-i2c";
454 reg = <0x48070000 0x100>;
455 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 ti,hwmods = "i2c1";
459 };
460
461 i2c2: i2c@48072000 {
462 compatible = "ti,omap4-i2c";
463 reg = <0x48072000 0x100>;
464 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
466 #size-cells = <0>;
467 ti,hwmods = "i2c2";
468 };
469
470 i2c3: i2c@48060000 {
471 compatible = "ti,omap4-i2c";
472 reg = <0x48060000 0x100>;
473 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 ti,hwmods = "i2c3";
477 };
478
479 i2c4: i2c@48350000 {
480 compatible = "ti,omap4-i2c";
481 reg = <0x48350000 0x100>;
482 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 ti,hwmods = "i2c4";
486 };
487
488 mcspi1: spi@48098000 {
489 compatible = "ti,omap4-mcspi";
490 reg = <0x48098000 0x200>;
491 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 ti,hwmods = "mcspi1";
495 ti,spi-num-cs = <4>;
496 dmas = <&sdma 35>,
497 <&sdma 36>,
498 <&sdma 37>,
499 <&sdma 38>,
500 <&sdma 39>,
501 <&sdma 40>,
502 <&sdma 41>,
503 <&sdma 42>;
504 dma-names = "tx0", "rx0", "tx1", "rx1",
505 "tx2", "rx2", "tx3", "rx3";
506 };
507
508 mcspi2: spi@4809a000 {
509 compatible = "ti,omap4-mcspi";
510 reg = <0x4809a000 0x200>;
511 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 ti,hwmods = "mcspi2";
515 ti,spi-num-cs = <2>;
516 dmas = <&sdma 43>,
517 <&sdma 44>,
518 <&sdma 45>,
519 <&sdma 46>;
520 dma-names = "tx0", "rx0", "tx1", "rx1";
521 };
522
523 mcspi3: spi@480b8000 {
524 compatible = "ti,omap4-mcspi";
525 reg = <0x480b8000 0x200>;
526 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 ti,hwmods = "mcspi3";
530 ti,spi-num-cs = <2>;
531 dmas = <&sdma 15>, <&sdma 16>;
532 dma-names = "tx0", "rx0";
533 };
534
535 mcspi4: spi@480ba000 {
536 compatible = "ti,omap4-mcspi";
537 reg = <0x480ba000 0x200>;
538 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
539 #address-cells = <1>;
540 #size-cells = <0>;
541 ti,hwmods = "mcspi4";
542 ti,spi-num-cs = <1>;
543 dmas = <&sdma 70>, <&sdma 71>;
544 dma-names = "tx0", "rx0";
545 };
546
547 mmc1: mmc@4809c000 {
548 compatible = "ti,omap4-hsmmc";
549 reg = <0x4809c000 0x400>;
550 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
551 ti,hwmods = "mmc1";
552 ti,dual-volt;
553 ti,needs-special-reset;
554 dmas = <&sdma 61>, <&sdma 62>;
555 dma-names = "tx", "rx";
556 pbias-supply = <&pbias_mmc_reg>;
557 };
558
559 mmc2: mmc@480b4000 {
560 compatible = "ti,omap4-hsmmc";
561 reg = <0x480b4000 0x400>;
562 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
563 ti,hwmods = "mmc2";
564 ti,needs-special-reset;
565 dmas = <&sdma 47>, <&sdma 48>;
566 dma-names = "tx", "rx";
567 };
568
569 mmc3: mmc@480ad000 {
570 compatible = "ti,omap4-hsmmc";
571 reg = <0x480ad000 0x400>;
572 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
573 ti,hwmods = "mmc3";
574 ti,needs-special-reset;
575 dmas = <&sdma 77>, <&sdma 78>;
576 dma-names = "tx", "rx";
577 };
578
579 mmc4: mmc@480d1000 {
580 compatible = "ti,omap4-hsmmc";
581 reg = <0x480d1000 0x400>;
582 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
583 ti,hwmods = "mmc4";
584 ti,needs-special-reset;
585 dmas = <&sdma 57>, <&sdma 58>;
586 dma-names = "tx", "rx";
587 };
588
589 mmc5: mmc@480d5000 {
590 compatible = "ti,omap4-hsmmc";
591 reg = <0x480d5000 0x400>;
592 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
593 ti,hwmods = "mmc5";
594 ti,needs-special-reset;
595 dmas = <&sdma 59>, <&sdma 60>;
596 dma-names = "tx", "rx";
597 };
598
599 mmu_dsp: mmu@4a066000 {
600 compatible = "ti,omap4-iommu";
601 reg = <0x4a066000 0x100>;
602 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
603 ti,hwmods = "mmu_dsp";
604 #iommu-cells = <0>;
605 };
606
607 mmu_ipu: mmu@55082000 {
608 compatible = "ti,omap4-iommu";
609 reg = <0x55082000 0x100>;
610 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
611 ti,hwmods = "mmu_ipu";
612 #iommu-cells = <0>;
613 ti,iommu-bus-err-back;
614 };
615
616 wdt2: wdt@4a314000 {
617 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
618 reg = <0x4a314000 0x80>;
619 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
620 ti,hwmods = "wd_timer2";
621 };
622
623 mcpdm: mcpdm@40132000 {
624 compatible = "ti,omap4-mcpdm";
625 reg = <0x40132000 0x7f>, /* MPU private access */
626 <0x49032000 0x7f>; /* L3 Interconnect */
627 reg-names = "mpu", "dma";
628 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
629 ti,hwmods = "mcpdm";
630 dmas = <&sdma 65>,
631 <&sdma 66>;
632 dma-names = "up_link", "dn_link";
633 status = "disabled";
634 };
635
636 dmic: dmic@4012e000 {
637 compatible = "ti,omap4-dmic";
638 reg = <0x4012e000 0x7f>, /* MPU private access */
639 <0x4902e000 0x7f>; /* L3 Interconnect */
640 reg-names = "mpu", "dma";
641 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
642 ti,hwmods = "dmic";
643 dmas = <&sdma 67>;
644 dma-names = "up_link";
645 status = "disabled";
646 };
647
648 mcbsp1: mcbsp@40122000 {
649 compatible = "ti,omap4-mcbsp";
650 reg = <0x40122000 0xff>, /* MPU private access */
651 <0x49022000 0xff>; /* L3 Interconnect */
652 reg-names = "mpu", "dma";
653 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
654 interrupt-names = "common";
655 ti,buffer-size = <128>;
656 ti,hwmods = "mcbsp1";
657 dmas = <&sdma 33>,
658 <&sdma 34>;
659 dma-names = "tx", "rx";
660 status = "disabled";
661 };
662
663 mcbsp2: mcbsp@40124000 {
664 compatible = "ti,omap4-mcbsp";
665 reg = <0x40124000 0xff>, /* MPU private access */
666 <0x49024000 0xff>; /* L3 Interconnect */
667 reg-names = "mpu", "dma";
668 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
669 interrupt-names = "common";
670 ti,buffer-size = <128>;
671 ti,hwmods = "mcbsp2";
672 dmas = <&sdma 17>,
673 <&sdma 18>;
674 dma-names = "tx", "rx";
675 status = "disabled";
676 };
677
678 mcbsp3: mcbsp@40126000 {
679 compatible = "ti,omap4-mcbsp";
680 reg = <0x40126000 0xff>, /* MPU private access */
681 <0x49026000 0xff>; /* L3 Interconnect */
682 reg-names = "mpu", "dma";
683 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
684 interrupt-names = "common";
685 ti,buffer-size = <128>;
686 ti,hwmods = "mcbsp3";
687 dmas = <&sdma 19>,
688 <&sdma 20>;
689 dma-names = "tx", "rx";
690 status = "disabled";
691 };
692
693 mcbsp4: mcbsp@48096000 {
694 compatible = "ti,omap4-mcbsp";
695 reg = <0x48096000 0xff>; /* L4 Interconnect */
696 reg-names = "mpu";
697 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
698 interrupt-names = "common";
699 ti,buffer-size = <128>;
700 ti,hwmods = "mcbsp4";
701 dmas = <&sdma 31>,
702 <&sdma 32>;
703 dma-names = "tx", "rx";
704 status = "disabled";
705 };
706
707 keypad: keypad@4a31c000 {
708 compatible = "ti,omap4-keypad";
709 reg = <0x4a31c000 0x80>;
710 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
711 reg-names = "mpu";
712 ti,hwmods = "kbd";
713 };
714
715 dmm@4e000000 {
716 compatible = "ti,omap4-dmm";
717 reg = <0x4e000000 0x800>;
718 interrupts = <0 113 0x4>;
719 ti,hwmods = "dmm";
720 };
721
722 emif1: emif@4c000000 {
723 compatible = "ti,emif-4d";
724 reg = <0x4c000000 0x100>;
725 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
726 ti,hwmods = "emif1";
727 ti,no-idle-on-init;
728 phy-type = <1>;
729 hw-caps-read-idle-ctrl;
730 hw-caps-ll-interface;
731 hw-caps-temp-alert;
732 };
733
734 emif2: emif@4d000000 {
735 compatible = "ti,emif-4d";
736 reg = <0x4d000000 0x100>;
737 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
738 ti,hwmods = "emif2";
739 ti,no-idle-on-init;
740 phy-type = <1>;
741 hw-caps-read-idle-ctrl;
742 hw-caps-ll-interface;
743 hw-caps-temp-alert;
744 };
745
746 ocp2scp@4a0ad000 {
747 compatible = "ti,omap-ocp2scp";
748 reg = <0x4a0ad000 0x1f>;
749 #address-cells = <1>;
750 #size-cells = <1>;
751 ranges;
752 ti,hwmods = "ocp2scp_usb_phy";
753 usb2_phy: usb2phy@4a0ad080 {
754 compatible = "ti,omap-usb2";
755 reg = <0x4a0ad080 0x58>;
756 ctrl-module = <&omap_control_usb2phy>;
757 clocks = <&usb_phy_cm_clk32k>;
758 clock-names = "wkupclk";
759 #phy-cells = <0>;
760 };
761 };
762
763 mailbox: mailbox@4a0f4000 {
764 compatible = "ti,omap4-mailbox";
765 reg = <0x4a0f4000 0x200>;
766 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
767 ti,hwmods = "mailbox";
768 #mbox-cells = <1>;
769 ti,mbox-num-users = <3>;
770 ti,mbox-num-fifos = <8>;
771 mbox_ipu: mbox_ipu {
772 ti,mbox-tx = <0 0 0>;
773 ti,mbox-rx = <1 0 0>;
774 };
775 mbox_dsp: mbox_dsp {
776 ti,mbox-tx = <3 0 0>;
777 ti,mbox-rx = <2 0 0>;
778 };
779 };
780
781 timer1: timer@4a318000 {
782 compatible = "ti,omap3430-timer";
783 reg = <0x4a318000 0x80>;
784 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
785 ti,hwmods = "timer1";
786 ti,timer-alwon;
787 };
788
789 timer2: timer@48032000 {
790 compatible = "ti,omap3430-timer";
791 reg = <0x48032000 0x80>;
792 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
793 ti,hwmods = "timer2";
794 };
795
796 timer3: timer@48034000 {
797 compatible = "ti,omap4430-timer";
798 reg = <0x48034000 0x80>;
799 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
800 ti,hwmods = "timer3";
801 };
802
803 timer4: timer@48036000 {
804 compatible = "ti,omap4430-timer";
805 reg = <0x48036000 0x80>;
806 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
807 ti,hwmods = "timer4";
808 };
809
810 timer5: timer@40138000 {
811 compatible = "ti,omap4430-timer";
812 reg = <0x40138000 0x80>,
813 <0x49038000 0x80>;
814 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
815 ti,hwmods = "timer5";
816 ti,timer-dsp;
817 };
818
819 timer6: timer@4013a000 {
820 compatible = "ti,omap4430-timer";
821 reg = <0x4013a000 0x80>,
822 <0x4903a000 0x80>;
823 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
824 ti,hwmods = "timer6";
825 ti,timer-dsp;
826 };
827
828 timer7: timer@4013c000 {
829 compatible = "ti,omap4430-timer";
830 reg = <0x4013c000 0x80>,
831 <0x4903c000 0x80>;
832 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
833 ti,hwmods = "timer7";
834 ti,timer-dsp;
835 };
836
837 timer8: timer@4013e000 {
838 compatible = "ti,omap4430-timer";
839 reg = <0x4013e000 0x80>,
840 <0x4903e000 0x80>;
841 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
842 ti,hwmods = "timer8";
843 ti,timer-pwm;
844 ti,timer-dsp;
845 };
846
847 timer9: timer@4803e000 {
848 compatible = "ti,omap4430-timer";
849 reg = <0x4803e000 0x80>;
850 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
851 ti,hwmods = "timer9";
852 ti,timer-pwm;
853 };
854
855 timer10: timer@48086000 {
856 compatible = "ti,omap3430-timer";
857 reg = <0x48086000 0x80>;
858 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
859 ti,hwmods = "timer10";
860 ti,timer-pwm;
861 };
862
863 timer11: timer@48088000 {
864 compatible = "ti,omap4430-timer";
865 reg = <0x48088000 0x80>;
866 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
867 ti,hwmods = "timer11";
868 ti,timer-pwm;
869 };
870
871 usbhstll: usbhstll@4a062000 {
872 compatible = "ti,usbhs-tll";
873 reg = <0x4a062000 0x1000>;
874 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
875 ti,hwmods = "usb_tll_hs";
876 };
877
878 usbhshost: usbhshost@4a064000 {
879 compatible = "ti,usbhs-host";
880 reg = <0x4a064000 0x800>;
881 ti,hwmods = "usb_host_hs";
882 #address-cells = <1>;
883 #size-cells = <1>;
884 ranges;
885 clocks = <&init_60m_fclk>,
886 <&xclk60mhsp1_ck>,
887 <&xclk60mhsp2_ck>;
888 clock-names = "refclk_60m_int",
889 "refclk_60m_ext_p1",
890 "refclk_60m_ext_p2";
891
892 usbhsohci: ohci@4a064800 {
893 compatible = "ti,ohci-omap3";
894 reg = <0x4a064800 0x400>;
895 interrupt-parent = <&gic>;
896 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
897 };
898
899 usbhsehci: ehci@4a064c00 {
900 compatible = "ti,ehci-omap";
901 reg = <0x4a064c00 0x400>;
902 interrupt-parent = <&gic>;
903 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
904 };
905 };
906
907 omap_control_usb2phy: control-phy@4a002300 {
908 compatible = "ti,control-phy-usb2";
909 reg = <0x4a002300 0x4>;
910 reg-names = "power";
911 };
912
913 omap_control_usbotg: control-phy@4a00233c {
914 compatible = "ti,control-phy-otghs";
915 reg = <0x4a00233c 0x4>;
916 reg-names = "otghs_control";
917 };
918
919 usb_otg_hs: usb_otg_hs@4a0ab000 {
920 compatible = "ti,omap4-musb";
921 reg = <0x4a0ab000 0x7ff>;
922 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "mc", "dma";
924 ti,hwmods = "usb_otg_hs";
925 usb-phy = <&usb2_phy>;
926 phys = <&usb2_phy>;
927 phy-names = "usb2-phy";
928 multipoint = <1>;
929 num-eps = <16>;
930 ram-bits = <12>;
931 ctrl-module = <&omap_control_usbotg>;
932 };
933
934 aes1: aes@4b501000 {
935 compatible = "ti,omap4-aes";
936 ti,hwmods = "aes1";
937 reg = <0x4b501000 0xa0>;
938 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
939 dmas = <&sdma 111>, <&sdma 110>;
940 dma-names = "tx", "rx";
941 };
942
943 aes2: aes@4b701000 {
944 compatible = "ti,omap4-aes";
945 ti,hwmods = "aes2";
946 reg = <0x4b701000 0xa0>;
947 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
948 dmas = <&sdma 114>, <&sdma 113>;
949 dma-names = "tx", "rx";
950 };
951
952 des: des@480a5000 {
953 compatible = "ti,omap4-des";
954 ti,hwmods = "des";
955 reg = <0x480a5000 0xa0>;
956 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
957 dmas = <&sdma 117>, <&sdma 116>;
958 dma-names = "tx", "rx";
959 };
960
961 sham: sham@4b100000 {
962 compatible = "ti,omap4-sham";
963 ti,hwmods = "sham";
964 reg = <0x4b100000 0x300>;
965 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
966 dmas = <&sdma 119>;
967 dma-names = "rx";
968 };
969
970 abb_mpu: regulator-abb-mpu {
971 compatible = "ti,abb-v2";
972 regulator-name = "abb_mpu";
973 #address-cells = <0>;
974 #size-cells = <0>;
975 ti,tranxdone-status-mask = <0x80>;
976 clocks = <&sys_clkin_ck>;
977 ti,settling-time = <50>;
978 ti,clock-cycles = <16>;
979
980 status = "disabled";
981 };
982
983 abb_iva: regulator-abb-iva {
984 compatible = "ti,abb-v2";
985 regulator-name = "abb_iva";
986 #address-cells = <0>;
987 #size-cells = <0>;
988 ti,tranxdone-status-mask = <0x80000000>;
989 clocks = <&sys_clkin_ck>;
990 ti,settling-time = <50>;
991 ti,clock-cycles = <16>;
992
993 status = "disabled";
994 };
995
996 dss: dss@58000000 {
997 compatible = "ti,omap4-dss";
998 reg = <0x58000000 0x80>;
999 status = "disabled";
1000 ti,hwmods = "dss_core";
1001 clocks = <&dss_dss_clk>;
1002 clock-names = "fck";
1003 #address-cells = <1>;
1004 #size-cells = <1>;
1005 ranges;
1006
1007 dispc@58001000 {
1008 compatible = "ti,omap4-dispc";
1009 reg = <0x58001000 0x1000>;
1010 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1011 ti,hwmods = "dss_dispc";
1012 clocks = <&dss_dss_clk>;
1013 clock-names = "fck";
1014 };
1015
1016 rfbi: encoder@58002000 {
1017 compatible = "ti,omap4-rfbi";
1018 reg = <0x58002000 0x1000>;
1019 status = "disabled";
1020 ti,hwmods = "dss_rfbi";
1021 clocks = <&dss_dss_clk>, <&l3_div_ck>;
1022 clock-names = "fck", "ick";
1023 };
1024
1025 venc: encoder@58003000 {
1026 compatible = "ti,omap4-venc";
1027 reg = <0x58003000 0x1000>;
1028 status = "disabled";
1029 ti,hwmods = "dss_venc";
1030 clocks = <&dss_tv_clk>;
1031 clock-names = "fck";
1032 };
1033
1034 dsi1: encoder@58004000 {
1035 compatible = "ti,omap4-dsi";
1036 reg = <0x58004000 0x200>,
1037 <0x58004200 0x40>,
1038 <0x58004300 0x20>;
1039 reg-names = "proto", "phy", "pll";
1040 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1041 status = "disabled";
1042 ti,hwmods = "dss_dsi1";
1043 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1044 clock-names = "fck", "sys_clk";
1045 };
1046
1047 dsi2: encoder@58005000 {
1048 compatible = "ti,omap4-dsi";
1049 reg = <0x58005000 0x200>,
1050 <0x58005200 0x40>,
1051 <0x58005300 0x20>;
1052 reg-names = "proto", "phy", "pll";
1053 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1054 status = "disabled";
1055 ti,hwmods = "dss_dsi2";
1056 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1057 clock-names = "fck", "sys_clk";
1058 };
1059
1060 hdmi: encoder@58006000 {
1061 compatible = "ti,omap4-hdmi";
1062 reg = <0x58006000 0x200>,
1063 <0x58006200 0x100>,
1064 <0x58006300 0x100>,
1065 <0x58006400 0x1000>;
1066 reg-names = "wp", "pll", "phy", "core";
1067 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1068 status = "disabled";
1069 ti,hwmods = "dss_hdmi";
1070 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1071 clock-names = "fck", "sys_clk";
1072 dmas = <&sdma 76>;
1073 dma-names = "audio_tx";
1074 };
1075 };
1076 };
1077 };
1078
1079 /include/ "omap44xx-clocks.dtsi"
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