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[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / omap5.dtsi
1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
13 #include <dt-bindings/clock/omap5.h>
14
15 / {
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 compatible = "ti,omap5";
20 interrupt-parent = <&wakeupgen>;
21 chosen { };
22
23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <0x0>;
45
46 operating-points = <
47 /* kHz uV */
48 1000000 1060000
49 1500000 1250000
50 >;
51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 clock-latency = <300000>; /* From omap-cpufreq driver */
56
57 /* cooling options */
58 #cooling-cells = <2>; /* min followed by max */
59 };
60 cpu@1 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <0x1>;
64
65 operating-points = <
66 /* kHz uV */
67 1000000 1060000
68 1500000 1250000
69 >;
70
71 clocks = <&dpll_mpu_ck>;
72 clock-names = "cpu";
73
74 clock-latency = <300000>; /* From omap-cpufreq driver */
75
76 /* cooling options */
77 #cooling-cells = <2>; /* min followed by max */
78 };
79 };
80
81 thermal-zones {
82 #include "omap4-cpu-thermal.dtsi"
83 #include "omap5-gpu-thermal.dtsi"
84 #include "omap5-core-thermal.dtsi"
85 };
86
87 timer {
88 compatible = "arm,armv7-timer";
89 /* PPI secure/nonsecure IRQ */
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
94 interrupt-parent = <&gic>;
95 };
96
97 pmu {
98 compatible = "arm,cortex-a15-pmu";
99 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
101 };
102
103 gic: interrupt-controller@48211000 {
104 compatible = "arm,cortex-a15-gic";
105 interrupt-controller;
106 #interrupt-cells = <3>;
107 reg = <0 0x48211000 0 0x1000>,
108 <0 0x48212000 0 0x2000>,
109 <0 0x48214000 0 0x2000>,
110 <0 0x48216000 0 0x2000>;
111 interrupt-parent = <&gic>;
112 };
113
114 wakeupgen: interrupt-controller@48281000 {
115 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
116 interrupt-controller;
117 #interrupt-cells = <3>;
118 reg = <0 0x48281000 0 0x1000>;
119 interrupt-parent = <&gic>;
120 };
121
122 /*
123 * The soc node represents the soc top level view. It is used for IPs
124 * that are not memory mapped in the MPU view or for the MPU itself.
125 */
126 soc {
127 compatible = "ti,omap-infra";
128 mpu {
129 compatible = "ti,omap4-mpu";
130 ti,hwmods = "mpu";
131 sram = <&ocmcram>;
132 };
133 };
134
135 /*
136 * XXX: Use a flat representation of the OMAP3 interconnect.
137 * The real OMAP interconnect network is quite complex.
138 * Since it will not bring real advantage to represent that in DT for
139 * the moment, just use a fake OCP bus entry to represent the whole bus
140 * hierarchy.
141 */
142 ocp {
143 compatible = "ti,omap5-l3-noc", "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0 0 0 0xc0000000>;
147 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
148 reg = <0 0x44000000 0 0x2000>,
149 <0 0x44800000 0 0x3000>,
150 <0 0x45000000 0 0x4000>;
151 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
153
154 l4_cfg: l4@4a000000 {
155 compatible = "ti,omap5-l4-cfg", "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges = <0 0x4a000000 0x22a000>;
159
160 scm_core: scm@2000 {
161 compatible = "ti,omap5-scm-core", "simple-bus";
162 reg = <0x2000 0x1000>;
163 #address-cells = <1>;
164 #size-cells = <1>;
165 ranges = <0 0x2000 0x800>;
166
167 scm_conf: scm_conf@0 {
168 compatible = "syscon";
169 reg = <0x0 0x800>;
170 #address-cells = <1>;
171 #size-cells = <1>;
172 };
173 };
174
175 scm_padconf_core: scm@2800 {
176 compatible = "ti,omap5-scm-padconf-core",
177 "simple-bus";
178 #address-cells = <1>;
179 #size-cells = <1>;
180 ranges = <0 0x2800 0x800>;
181
182 omap5_pmx_core: pinmux@40 {
183 compatible = "ti,omap5-padconf",
184 "pinctrl-single";
185 reg = <0x40 0x01b6>;
186 #address-cells = <1>;
187 #size-cells = <0>;
188 #pinctrl-cells = <1>;
189 #interrupt-cells = <1>;
190 interrupt-controller;
191 pinctrl-single,register-width = <16>;
192 pinctrl-single,function-mask = <0x7fff>;
193 };
194
195 omap5_padconf_global: omap5_padconf_global@5a0 {
196 compatible = "syscon",
197 "simple-bus";
198 reg = <0x5a0 0xec>;
199 #address-cells = <1>;
200 #size-cells = <1>;
201 ranges = <0 0x5a0 0xec>;
202
203 pbias_regulator: pbias_regulator@60 {
204 compatible = "ti,pbias-omap5", "ti,pbias-omap";
205 reg = <0x60 0x4>;
206 syscon = <&omap5_padconf_global>;
207 pbias_mmc_reg: pbias_mmc_omap5 {
208 regulator-name = "pbias_mmc_omap5";
209 regulator-min-microvolt = <1800000>;
210 regulator-max-microvolt = <3300000>;
211 };
212 };
213 };
214 };
215
216 cm_core_aon: cm_core_aon@4000 {
217 compatible = "ti,omap5-cm-core-aon",
218 "simple-bus";
219 reg = <0x4000 0x2000>;
220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges = <0 0x4000 0x2000>;
223
224 cm_core_aon_clocks: clocks {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 };
228
229 cm_core_aon_clockdomains: clockdomains {
230 };
231 };
232
233 cm_core: cm_core@8000 {
234 compatible = "ti,omap5-cm-core", "simple-bus";
235 reg = <0x8000 0x3000>;
236 #address-cells = <1>;
237 #size-cells = <1>;
238 ranges = <0 0x8000 0x3000>;
239
240 cm_core_clocks: clocks {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 };
244
245 cm_core_clockdomains: clockdomains {
246 };
247 };
248 };
249
250 l4_wkup: l4@4ae00000 {
251 compatible = "ti,omap5-l4-wkup", "simple-bus";
252 #address-cells = <1>;
253 #size-cells = <1>;
254 ranges = <0 0x4ae00000 0x2b000>;
255
256 counter32k: counter@4000 {
257 compatible = "ti,omap-counter32k";
258 reg = <0x4000 0x40>;
259 ti,hwmods = "counter_32k";
260 };
261
262 prm: prm@6000 {
263 compatible = "ti,omap5-prm", "simple-bus";
264 reg = <0x6000 0x3000>;
265 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
266 #address-cells = <1>;
267 #size-cells = <1>;
268 ranges = <0 0x6000 0x3000>;
269
270 prm_clocks: clocks {
271 #address-cells = <1>;
272 #size-cells = <0>;
273 };
274
275 prm_clockdomains: clockdomains {
276 };
277 };
278
279 scrm: scrm@a000 {
280 compatible = "ti,omap5-scrm";
281 reg = <0xa000 0x2000>;
282
283 scrm_clocks: clocks {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 };
287
288 scrm_clockdomains: clockdomains {
289 };
290 };
291
292 omap5_pmx_wkup: pinmux@c840 {
293 compatible = "ti,omap5-padconf",
294 "pinctrl-single";
295 reg = <0xc840 0x003c>;
296 #address-cells = <1>;
297 #size-cells = <0>;
298 #pinctrl-cells = <1>;
299 #interrupt-cells = <1>;
300 interrupt-controller;
301 pinctrl-single,register-width = <16>;
302 pinctrl-single,function-mask = <0x7fff>;
303 };
304
305 omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 {
306 compatible = "ti,omap5-scm-wkup-pad-conf",
307 "simple-bus";
308 reg = <0xcda0 0x60>;
309 #address-cells = <1>;
310 #size-cells = <1>;
311 ranges = <0 0xcda0 0x60>;
312
313 scm_wkup_pad_conf: scm_conf@0 {
314 compatible = "syscon", "simple-bus";
315 reg = <0x0 0x60>;
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0 0x0 0x60>;
319
320 scm_wkup_pad_conf_clocks: clocks@0 {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 };
324 };
325 };
326 };
327
328 ocmcram: ocmcram@40300000 {
329 compatible = "mmio-sram";
330 reg = <0x40300000 0x20000>; /* 128k */
331 };
332
333 sdma: dma-controller@4a056000 {
334 compatible = "ti,omap4430-sdma";
335 reg = <0x4a056000 0x1000>;
336 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
340 #dma-cells = <1>;
341 dma-channels = <32>;
342 dma-requests = <127>;
343 ti,hwmods = "dma_system";
344 };
345
346 gpio1: gpio@4ae10000 {
347 compatible = "ti,omap4-gpio";
348 reg = <0x4ae10000 0x200>;
349 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
350 ti,hwmods = "gpio1";
351 ti,gpio-always-on;
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 };
357
358 gpio2: gpio@48055000 {
359 compatible = "ti,omap4-gpio";
360 reg = <0x48055000 0x200>;
361 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
362 ti,hwmods = "gpio2";
363 gpio-controller;
364 #gpio-cells = <2>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
367 };
368
369 gpio3: gpio@48057000 {
370 compatible = "ti,omap4-gpio";
371 reg = <0x48057000 0x200>;
372 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
373 ti,hwmods = "gpio3";
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 };
379
380 gpio4: gpio@48059000 {
381 compatible = "ti,omap4-gpio";
382 reg = <0x48059000 0x200>;
383 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
384 ti,hwmods = "gpio4";
385 gpio-controller;
386 #gpio-cells = <2>;
387 interrupt-controller;
388 #interrupt-cells = <2>;
389 };
390
391 gpio5: gpio@4805b000 {
392 compatible = "ti,omap4-gpio";
393 reg = <0x4805b000 0x200>;
394 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
395 ti,hwmods = "gpio5";
396 gpio-controller;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 };
401
402 gpio6: gpio@4805d000 {
403 compatible = "ti,omap4-gpio";
404 reg = <0x4805d000 0x200>;
405 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
406 ti,hwmods = "gpio6";
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 };
412
413 gpio7: gpio@48051000 {
414 compatible = "ti,omap4-gpio";
415 reg = <0x48051000 0x200>;
416 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
417 ti,hwmods = "gpio7";
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 };
423
424 gpio8: gpio@48053000 {
425 compatible = "ti,omap4-gpio";
426 reg = <0x48053000 0x200>;
427 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
428 ti,hwmods = "gpio8";
429 gpio-controller;
430 #gpio-cells = <2>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 };
434
435 gpmc: gpmc@50000000 {
436 compatible = "ti,omap4430-gpmc";
437 reg = <0x50000000 0x1000>;
438 #address-cells = <2>;
439 #size-cells = <1>;
440 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
441 dmas = <&sdma 4>;
442 dma-names = "rxtx";
443 gpmc,num-cs = <8>;
444 gpmc,num-waitpins = <4>;
445 ti,hwmods = "gpmc";
446 clocks = <&l3_iclk_div>;
447 clock-names = "fck";
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 gpio-controller;
451 #gpio-cells = <2>;
452 };
453
454 i2c1: i2c@48070000 {
455 compatible = "ti,omap4-i2c";
456 reg = <0x48070000 0x100>;
457 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
458 #address-cells = <1>;
459 #size-cells = <0>;
460 ti,hwmods = "i2c1";
461 };
462
463 i2c2: i2c@48072000 {
464 compatible = "ti,omap4-i2c";
465 reg = <0x48072000 0x100>;
466 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 ti,hwmods = "i2c2";
470 };
471
472 i2c3: i2c@48060000 {
473 compatible = "ti,omap4-i2c";
474 reg = <0x48060000 0x100>;
475 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 ti,hwmods = "i2c3";
479 };
480
481 i2c4: i2c@4807a000 {
482 compatible = "ti,omap4-i2c";
483 reg = <0x4807a000 0x100>;
484 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
485 #address-cells = <1>;
486 #size-cells = <0>;
487 ti,hwmods = "i2c4";
488 };
489
490 i2c5: i2c@4807c000 {
491 compatible = "ti,omap4-i2c";
492 reg = <0x4807c000 0x100>;
493 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
495 #size-cells = <0>;
496 ti,hwmods = "i2c5";
497 };
498
499 hwspinlock: spinlock@4a0f6000 {
500 compatible = "ti,omap4-hwspinlock";
501 reg = <0x4a0f6000 0x1000>;
502 ti,hwmods = "spinlock";
503 #hwlock-cells = <1>;
504 };
505
506 mcspi1: spi@48098000 {
507 compatible = "ti,omap4-mcspi";
508 reg = <0x48098000 0x200>;
509 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 ti,hwmods = "mcspi1";
513 ti,spi-num-cs = <4>;
514 dmas = <&sdma 35>,
515 <&sdma 36>,
516 <&sdma 37>,
517 <&sdma 38>,
518 <&sdma 39>,
519 <&sdma 40>,
520 <&sdma 41>,
521 <&sdma 42>;
522 dma-names = "tx0", "rx0", "tx1", "rx1",
523 "tx2", "rx2", "tx3", "rx3";
524 };
525
526 mcspi2: spi@4809a000 {
527 compatible = "ti,omap4-mcspi";
528 reg = <0x4809a000 0x200>;
529 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 ti,hwmods = "mcspi2";
533 ti,spi-num-cs = <2>;
534 dmas = <&sdma 43>,
535 <&sdma 44>,
536 <&sdma 45>,
537 <&sdma 46>;
538 dma-names = "tx0", "rx0", "tx1", "rx1";
539 };
540
541 mcspi3: spi@480b8000 {
542 compatible = "ti,omap4-mcspi";
543 reg = <0x480b8000 0x200>;
544 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 ti,hwmods = "mcspi3";
548 ti,spi-num-cs = <2>;
549 dmas = <&sdma 15>, <&sdma 16>;
550 dma-names = "tx0", "rx0";
551 };
552
553 mcspi4: spi@480ba000 {
554 compatible = "ti,omap4-mcspi";
555 reg = <0x480ba000 0x200>;
556 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 ti,hwmods = "mcspi4";
560 ti,spi-num-cs = <1>;
561 dmas = <&sdma 70>, <&sdma 71>;
562 dma-names = "tx0", "rx0";
563 };
564
565 uart1: serial@4806a000 {
566 compatible = "ti,omap4-uart";
567 reg = <0x4806a000 0x100>;
568 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
569 ti,hwmods = "uart1";
570 clock-frequency = <48000000>;
571 };
572
573 uart2: serial@4806c000 {
574 compatible = "ti,omap4-uart";
575 reg = <0x4806c000 0x100>;
576 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
577 ti,hwmods = "uart2";
578 clock-frequency = <48000000>;
579 };
580
581 uart3: serial@48020000 {
582 compatible = "ti,omap4-uart";
583 reg = <0x48020000 0x100>;
584 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
585 ti,hwmods = "uart3";
586 clock-frequency = <48000000>;
587 };
588
589 uart4: serial@4806e000 {
590 compatible = "ti,omap4-uart";
591 reg = <0x4806e000 0x100>;
592 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
593 ti,hwmods = "uart4";
594 clock-frequency = <48000000>;
595 };
596
597 uart5: serial@48066000 {
598 compatible = "ti,omap4-uart";
599 reg = <0x48066000 0x100>;
600 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
601 ti,hwmods = "uart5";
602 clock-frequency = <48000000>;
603 };
604
605 uart6: serial@48068000 {
606 compatible = "ti,omap4-uart";
607 reg = <0x48068000 0x100>;
608 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
609 ti,hwmods = "uart6";
610 clock-frequency = <48000000>;
611 };
612
613 mmc1: mmc@4809c000 {
614 compatible = "ti,omap4-hsmmc";
615 reg = <0x4809c000 0x400>;
616 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
617 ti,hwmods = "mmc1";
618 ti,dual-volt;
619 ti,needs-special-reset;
620 dmas = <&sdma 61>, <&sdma 62>;
621 dma-names = "tx", "rx";
622 pbias-supply = <&pbias_mmc_reg>;
623 };
624
625 mmc2: mmc@480b4000 {
626 compatible = "ti,omap4-hsmmc";
627 reg = <0x480b4000 0x400>;
628 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
629 ti,hwmods = "mmc2";
630 ti,needs-special-reset;
631 dmas = <&sdma 47>, <&sdma 48>;
632 dma-names = "tx", "rx";
633 };
634
635 mmc3: mmc@480ad000 {
636 compatible = "ti,omap4-hsmmc";
637 reg = <0x480ad000 0x400>;
638 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
639 ti,hwmods = "mmc3";
640 ti,needs-special-reset;
641 dmas = <&sdma 77>, <&sdma 78>;
642 dma-names = "tx", "rx";
643 };
644
645 mmc4: mmc@480d1000 {
646 compatible = "ti,omap4-hsmmc";
647 reg = <0x480d1000 0x400>;
648 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
649 ti,hwmods = "mmc4";
650 ti,needs-special-reset;
651 dmas = <&sdma 57>, <&sdma 58>;
652 dma-names = "tx", "rx";
653 };
654
655 mmc5: mmc@480d5000 {
656 compatible = "ti,omap4-hsmmc";
657 reg = <0x480d5000 0x400>;
658 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
659 ti,hwmods = "mmc5";
660 ti,needs-special-reset;
661 dmas = <&sdma 59>, <&sdma 60>;
662 dma-names = "tx", "rx";
663 };
664
665 mmu_dsp: mmu@4a066000 {
666 compatible = "ti,omap4-iommu";
667 reg = <0x4a066000 0x100>;
668 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
669 ti,hwmods = "mmu_dsp";
670 #iommu-cells = <0>;
671 };
672
673 mmu_ipu: mmu@55082000 {
674 compatible = "ti,omap4-iommu";
675 reg = <0x55082000 0x100>;
676 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
677 ti,hwmods = "mmu_ipu";
678 #iommu-cells = <0>;
679 ti,iommu-bus-err-back;
680 };
681
682 keypad: keypad@4ae1c000 {
683 compatible = "ti,omap4-keypad";
684 reg = <0x4ae1c000 0x400>;
685 ti,hwmods = "kbd";
686 };
687
688 mcpdm: mcpdm@40132000 {
689 compatible = "ti,omap4-mcpdm";
690 reg = <0x40132000 0x7f>, /* MPU private access */
691 <0x49032000 0x7f>; /* L3 Interconnect */
692 reg-names = "mpu", "dma";
693 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
694 ti,hwmods = "mcpdm";
695 dmas = <&sdma 65>,
696 <&sdma 66>;
697 dma-names = "up_link", "dn_link";
698 status = "disabled";
699 };
700
701 dmic: dmic@4012e000 {
702 compatible = "ti,omap4-dmic";
703 reg = <0x4012e000 0x7f>, /* MPU private access */
704 <0x4902e000 0x7f>; /* L3 Interconnect */
705 reg-names = "mpu", "dma";
706 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
707 ti,hwmods = "dmic";
708 dmas = <&sdma 67>;
709 dma-names = "up_link";
710 status = "disabled";
711 };
712
713 mcbsp1: mcbsp@40122000 {
714 compatible = "ti,omap4-mcbsp";
715 reg = <0x40122000 0xff>, /* MPU private access */
716 <0x49022000 0xff>; /* L3 Interconnect */
717 reg-names = "mpu", "dma";
718 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
719 interrupt-names = "common";
720 ti,buffer-size = <128>;
721 ti,hwmods = "mcbsp1";
722 dmas = <&sdma 33>,
723 <&sdma 34>;
724 dma-names = "tx", "rx";
725 status = "disabled";
726 };
727
728 mcbsp2: mcbsp@40124000 {
729 compatible = "ti,omap4-mcbsp";
730 reg = <0x40124000 0xff>, /* MPU private access */
731 <0x49024000 0xff>; /* L3 Interconnect */
732 reg-names = "mpu", "dma";
733 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
734 interrupt-names = "common";
735 ti,buffer-size = <128>;
736 ti,hwmods = "mcbsp2";
737 dmas = <&sdma 17>,
738 <&sdma 18>;
739 dma-names = "tx", "rx";
740 status = "disabled";
741 };
742
743 mcbsp3: mcbsp@40126000 {
744 compatible = "ti,omap4-mcbsp";
745 reg = <0x40126000 0xff>, /* MPU private access */
746 <0x49026000 0xff>; /* L3 Interconnect */
747 reg-names = "mpu", "dma";
748 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
749 interrupt-names = "common";
750 ti,buffer-size = <128>;
751 ti,hwmods = "mcbsp3";
752 dmas = <&sdma 19>,
753 <&sdma 20>;
754 dma-names = "tx", "rx";
755 status = "disabled";
756 };
757
758 mailbox: mailbox@4a0f4000 {
759 compatible = "ti,omap4-mailbox";
760 reg = <0x4a0f4000 0x200>;
761 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
762 ti,hwmods = "mailbox";
763 #mbox-cells = <1>;
764 ti,mbox-num-users = <3>;
765 ti,mbox-num-fifos = <8>;
766 mbox_ipu: mbox_ipu {
767 ti,mbox-tx = <0 0 0>;
768 ti,mbox-rx = <1 0 0>;
769 };
770 mbox_dsp: mbox_dsp {
771 ti,mbox-tx = <3 0 0>;
772 ti,mbox-rx = <2 0 0>;
773 };
774 };
775
776 timer1: timer@4ae18000 {
777 compatible = "ti,omap5430-timer";
778 reg = <0x4ae18000 0x80>;
779 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
780 ti,hwmods = "timer1";
781 ti,timer-alwon;
782 clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
783 clock-names = "fck";
784 };
785
786 timer2: timer@48032000 {
787 compatible = "ti,omap5430-timer";
788 reg = <0x48032000 0x80>;
789 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
790 ti,hwmods = "timer2";
791 };
792
793 timer3: timer@48034000 {
794 compatible = "ti,omap5430-timer";
795 reg = <0x48034000 0x80>;
796 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
797 ti,hwmods = "timer3";
798 };
799
800 timer4: timer@48036000 {
801 compatible = "ti,omap5430-timer";
802 reg = <0x48036000 0x80>;
803 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
804 ti,hwmods = "timer4";
805 };
806
807 timer5: timer@40138000 {
808 compatible = "ti,omap5430-timer";
809 reg = <0x40138000 0x80>,
810 <0x49038000 0x80>;
811 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
812 ti,hwmods = "timer5";
813 ti,timer-dsp;
814 ti,timer-pwm;
815 };
816
817 timer6: timer@4013a000 {
818 compatible = "ti,omap5430-timer";
819 reg = <0x4013a000 0x80>,
820 <0x4903a000 0x80>;
821 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
822 ti,hwmods = "timer6";
823 ti,timer-dsp;
824 ti,timer-pwm;
825 };
826
827 timer7: timer@4013c000 {
828 compatible = "ti,omap5430-timer";
829 reg = <0x4013c000 0x80>,
830 <0x4903c000 0x80>;
831 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
832 ti,hwmods = "timer7";
833 ti,timer-dsp;
834 };
835
836 timer8: timer@4013e000 {
837 compatible = "ti,omap5430-timer";
838 reg = <0x4013e000 0x80>,
839 <0x4903e000 0x80>;
840 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
841 ti,hwmods = "timer8";
842 ti,timer-dsp;
843 ti,timer-pwm;
844 };
845
846 timer9: timer@4803e000 {
847 compatible = "ti,omap5430-timer";
848 reg = <0x4803e000 0x80>;
849 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
850 ti,hwmods = "timer9";
851 ti,timer-pwm;
852 };
853
854 timer10: timer@48086000 {
855 compatible = "ti,omap5430-timer";
856 reg = <0x48086000 0x80>;
857 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
858 ti,hwmods = "timer10";
859 ti,timer-pwm;
860 };
861
862 timer11: timer@48088000 {
863 compatible = "ti,omap5430-timer";
864 reg = <0x48088000 0x80>;
865 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
866 ti,hwmods = "timer11";
867 ti,timer-pwm;
868 };
869
870 wdt2: wdt@4ae14000 {
871 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
872 reg = <0x4ae14000 0x80>;
873 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
874 ti,hwmods = "wd_timer2";
875 };
876
877 dmm@4e000000 {
878 compatible = "ti,omap5-dmm";
879 reg = <0x4e000000 0x800>;
880 interrupts = <0 113 0x4>;
881 ti,hwmods = "dmm";
882 };
883
884 emif1: emif@4c000000 {
885 compatible = "ti,emif-4d5";
886 ti,hwmods = "emif1";
887 ti,no-idle-on-init;
888 phy-type = <2>; /* DDR PHY type: Intelli PHY */
889 reg = <0x4c000000 0x400>;
890 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
891 hw-caps-read-idle-ctrl;
892 hw-caps-ll-interface;
893 hw-caps-temp-alert;
894 };
895
896 emif2: emif@4d000000 {
897 compatible = "ti,emif-4d5";
898 ti,hwmods = "emif2";
899 ti,no-idle-on-init;
900 phy-type = <2>; /* DDR PHY type: Intelli PHY */
901 reg = <0x4d000000 0x400>;
902 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
903 hw-caps-read-idle-ctrl;
904 hw-caps-ll-interface;
905 hw-caps-temp-alert;
906 };
907
908 usb3: omap_dwc3@4a020000 {
909 compatible = "ti,dwc3";
910 ti,hwmods = "usb_otg_ss";
911 reg = <0x4a020000 0x10000>;
912 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
913 #address-cells = <1>;
914 #size-cells = <1>;
915 utmi-mode = <2>;
916 ranges;
917 dwc3: dwc3@4a030000 {
918 compatible = "snps,dwc3";
919 reg = <0x4a030000 0x10000>;
920 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "peripheral",
924 "host",
925 "otg";
926 phys = <&usb2_phy>, <&usb3_phy>;
927 phy-names = "usb2-phy", "usb3-phy";
928 dr_mode = "peripheral";
929 };
930 };
931
932 ocp2scp@4a080000 {
933 compatible = "ti,omap-ocp2scp";
934 #address-cells = <1>;
935 #size-cells = <1>;
936 reg = <0x4a080000 0x20>;
937 ranges;
938 ti,hwmods = "ocp2scp1";
939 usb2_phy: usb2phy@4a084000 {
940 compatible = "ti,omap-usb2";
941 reg = <0x4a084000 0x7c>;
942 syscon-phy-power = <&scm_conf 0x300>;
943 clocks = <&usb_phy_cm_clk32k>,
944 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
945 clock-names = "wkupclk", "refclk";
946 #phy-cells = <0>;
947 };
948
949 usb3_phy: usb3phy@4a084400 {
950 compatible = "ti,omap-usb3";
951 reg = <0x4a084400 0x80>,
952 <0x4a084800 0x64>,
953 <0x4a084c00 0x40>;
954 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
955 syscon-phy-power = <&scm_conf 0x370>;
956 clocks = <&usb_phy_cm_clk32k>,
957 <&sys_clkin>,
958 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
959 clock-names = "wkupclk",
960 "sysclk",
961 "refclk";
962 #phy-cells = <0>;
963 };
964 };
965
966 usbhstll: usbhstll@4a062000 {
967 compatible = "ti,usbhs-tll";
968 reg = <0x4a062000 0x1000>;
969 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
970 ti,hwmods = "usb_tll_hs";
971 };
972
973 usbhshost: usbhshost@4a064000 {
974 compatible = "ti,usbhs-host";
975 reg = <0x4a064000 0x800>;
976 ti,hwmods = "usb_host_hs";
977 #address-cells = <1>;
978 #size-cells = <1>;
979 ranges;
980 clocks = <&l3init_60m_fclk>,
981 <&xclk60mhsp1_ck>,
982 <&xclk60mhsp2_ck>;
983 clock-names = "refclk_60m_int",
984 "refclk_60m_ext_p1",
985 "refclk_60m_ext_p2";
986
987 usbhsohci: ohci@4a064800 {
988 compatible = "ti,ohci-omap3";
989 reg = <0x4a064800 0x400>;
990 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
991 remote-wakeup-connected;
992 };
993
994 usbhsehci: ehci@4a064c00 {
995 compatible = "ti,ehci-omap";
996 reg = <0x4a064c00 0x400>;
997 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
998 };
999 };
1000
1001 bandgap: bandgap@4a0021e0 {
1002 reg = <0x4a0021e0 0xc
1003 0x4a00232c 0xc
1004 0x4a002380 0x2c
1005 0x4a0023C0 0x3c>;
1006 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1007 compatible = "ti,omap5430-bandgap";
1008
1009 #thermal-sensor-cells = <1>;
1010 };
1011
1012 /* OCP2SCP3 */
1013 ocp2scp@4a090000 {
1014 compatible = "ti,omap-ocp2scp";
1015 #address-cells = <1>;
1016 #size-cells = <1>;
1017 reg = <0x4a090000 0x20>;
1018 ranges;
1019 ti,hwmods = "ocp2scp3";
1020 sata_phy: phy@4a096000 {
1021 compatible = "ti,phy-pipe3-sata";
1022 reg = <0x4A096000 0x80>, /* phy_rx */
1023 <0x4A096400 0x64>, /* phy_tx */
1024 <0x4A096800 0x40>; /* pll_ctrl */
1025 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1026 syscon-phy-power = <&scm_conf 0x374>;
1027 clocks = <&sys_clkin>,
1028 <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1029 clock-names = "sysclk", "refclk";
1030 #phy-cells = <0>;
1031 };
1032 };
1033
1034 sata: sata@4a141100 {
1035 compatible = "snps,dwc-ahci";
1036 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1037 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1038 phys = <&sata_phy>;
1039 phy-names = "sata-phy";
1040 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1041 ti,hwmods = "sata";
1042 ports-implemented = <0x1>;
1043 };
1044
1045 dss: dss@58000000 {
1046 compatible = "ti,omap5-dss";
1047 reg = <0x58000000 0x80>;
1048 status = "disabled";
1049 ti,hwmods = "dss_core";
1050 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1051 clock-names = "fck";
1052 #address-cells = <1>;
1053 #size-cells = <1>;
1054 ranges;
1055
1056 dispc@58001000 {
1057 compatible = "ti,omap5-dispc";
1058 reg = <0x58001000 0x1000>;
1059 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1060 ti,hwmods = "dss_dispc";
1061 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1062 clock-names = "fck";
1063 };
1064
1065 rfbi: encoder@58002000 {
1066 compatible = "ti,omap5-rfbi";
1067 reg = <0x58002000 0x100>;
1068 status = "disabled";
1069 ti,hwmods = "dss_rfbi";
1070 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
1071 clock-names = "fck", "ick";
1072 };
1073
1074 dsi1: encoder@58004000 {
1075 compatible = "ti,omap5-dsi";
1076 reg = <0x58004000 0x200>,
1077 <0x58004200 0x40>,
1078 <0x58004300 0x40>;
1079 reg-names = "proto", "phy", "pll";
1080 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1081 status = "disabled";
1082 ti,hwmods = "dss_dsi1";
1083 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1084 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1085 clock-names = "fck", "sys_clk";
1086 };
1087
1088 dsi2: encoder@58005000 {
1089 compatible = "ti,omap5-dsi";
1090 reg = <0x58009000 0x200>,
1091 <0x58009200 0x40>,
1092 <0x58009300 0x40>;
1093 reg-names = "proto", "phy", "pll";
1094 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1095 status = "disabled";
1096 ti,hwmods = "dss_dsi2";
1097 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1098 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1099 clock-names = "fck", "sys_clk";
1100 };
1101
1102 hdmi: encoder@58060000 {
1103 compatible = "ti,omap5-hdmi";
1104 reg = <0x58040000 0x200>,
1105 <0x58040200 0x80>,
1106 <0x58040300 0x80>,
1107 <0x58060000 0x19000>;
1108 reg-names = "wp", "pll", "phy", "core";
1109 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1110 status = "disabled";
1111 ti,hwmods = "dss_hdmi";
1112 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
1113 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1114 clock-names = "fck", "sys_clk";
1115 dmas = <&sdma 76>;
1116 dma-names = "audio_tx";
1117 };
1118 };
1119
1120 abb_mpu: regulator-abb-mpu {
1121 compatible = "ti,abb-v2";
1122 regulator-name = "abb_mpu";
1123 #address-cells = <0>;
1124 #size-cells = <0>;
1125 clocks = <&sys_clkin>;
1126 ti,settling-time = <50>;
1127 ti,clock-cycles = <16>;
1128
1129 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1130 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1131 reg-names = "base-address", "int-address",
1132 "efuse-address", "ldo-address";
1133 ti,tranxdone-status-mask = <0x80>;
1134 /* LDOVBBMPU_MUX_CTRL */
1135 ti,ldovbb-override-mask = <0x400>;
1136 /* LDOVBBMPU_VSET_OUT */
1137 ti,ldovbb-vset-mask = <0x1F>;
1138
1139 /*
1140 * NOTE: only FBB mode used but actual vset will
1141 * determine final biasing
1142 */
1143 ti,abb_info = <
1144 /*uV ABB efuse rbb_m fbb_m vset_m*/
1145 1060000 0 0x0 0 0x02000000 0x01F00000
1146 1250000 0 0x4 0 0x02000000 0x01F00000
1147 >;
1148 };
1149
1150 abb_mm: regulator-abb-mm {
1151 compatible = "ti,abb-v2";
1152 regulator-name = "abb_mm";
1153 #address-cells = <0>;
1154 #size-cells = <0>;
1155 clocks = <&sys_clkin>;
1156 ti,settling-time = <50>;
1157 ti,clock-cycles = <16>;
1158
1159 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1160 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1161 reg-names = "base-address", "int-address",
1162 "efuse-address", "ldo-address";
1163 ti,tranxdone-status-mask = <0x80000000>;
1164 /* LDOVBBMM_MUX_CTRL */
1165 ti,ldovbb-override-mask = <0x400>;
1166 /* LDOVBBMM_VSET_OUT */
1167 ti,ldovbb-vset-mask = <0x1F>;
1168
1169 /*
1170 * NOTE: only FBB mode used but actual vset will
1171 * determine final biasing
1172 */
1173 ti,abb_info = <
1174 /*uV ABB efuse rbb_m fbb_m vset_m*/
1175 1025000 0 0x0 0 0x02000000 0x01F00000
1176 1120000 0 0x4 0 0x02000000 0x01F00000
1177 >;
1178 };
1179 };
1180 };
1181
1182 &cpu_thermal {
1183 polling-delay = <500>; /* milliseconds */
1184 coefficients = <65 (-1791)>;
1185 };
1186
1187 #include "omap54xx-clocks.dtsi"
1188
1189 &gpu_thermal {
1190 coefficients = <117 (-2992)>;
1191 };
1192
1193 &core_thermal {
1194 coefficients = <0 2000>;
1195 };
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