arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/bus/ti-sysc.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14 #include <dt-bindings/clock/omap5.h>
  15
  16 / {
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&wakeupgen>;
  22         chosen { };
  23
  24         aliases {
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 i2c4 = &i2c5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a15";
  45                         reg = <0x0>;
  46
  47                         operating-points = <
  48                                 /* kHz    uV */
  49                                 1000000 1060000
  50                                 1500000 1250000
  51                         >;
  52
  53                         clocks = <&dpll_mpu_ck>;
  54                         clock-names = "cpu";
  55
  56                         clock-latency = <300000>; /* From omap-cpufreq driver */
  57
  58                         /* cooling options */
  59                         #cooling-cells = <2>; /* min followed by max */
  60                 };
  61                 cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a15";
  64                         reg = <0x1>;
  65
  66                         operating-points = <
  67                                 /* kHz    uV */
  68                                 1000000 1060000
  69                                 1500000 1250000
  70                         >;
  71
  72                         clocks = <&dpll_mpu_ck>;
  73                         clock-names = "cpu";
  74
  75                         clock-latency = <300000>; /* From omap-cpufreq driver */
  76
  77                         /* cooling options */
  78                         #cooling-cells = <2>; /* min followed by max */
  79                 };
  80         };
  81
  82         thermal-zones {
  83                 #include "omap4-cpu-thermal.dtsi"
  84                 #include "omap5-gpu-thermal.dtsi"
  85                 #include "omap5-core-thermal.dtsi"
  86         };
  87
  88         timer {
  89                 compatible = "arm,armv7-timer";
  90                 /* PPI secure/nonsecure IRQ */
  91                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  93                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  94                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  95                 interrupt-parent = <&gic>;
  96         };
  97
  98         pmu {
  99                 compatible = "arm,cortex-a15-pmu";
 100                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 101                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 102         };
 103
 104         gic: interrupt-controller@48211000 {
 105                 compatible = "arm,cortex-a15-gic";
 106                 interrupt-controller;
 107                 #interrupt-cells = <3>;
 108                 reg = <0 0x48211000 0 0x1000>,
 109                       <0 0x48212000 0 0x2000>,
 110                       <0 0x48214000 0 0x2000>,
 111                       <0 0x48216000 0 0x2000>;
 112                 interrupt-parent = <&gic>;
 113         };
 114
 115         wakeupgen: interrupt-controller@48281000 {
 116                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 117                 interrupt-controller;
 118                 #interrupt-cells = <3>;
 119                 reg = <0 0x48281000 0 0x1000>;
 120                 interrupt-parent = <&gic>;
 121         };
 122
 123         /*
 124          * The soc node represents the soc top level view. It is used for IPs
 125          * that are not memory mapped in the MPU view or for the MPU itself.
 126          */
 127         soc {
 128                 compatible = "ti,omap-infra";
 129                 mpu {
 130                         compatible = "ti,omap4-mpu";
 131                         ti,hwmods = "mpu";
 132                         sram = <&ocmcram>;
 133                 };
 134         };
 135
 136         /*
 137          * XXX: Use a flat representation of the OMAP3 interconnect.
 138          * The real OMAP interconnect network is quite complex.
 139          * Since it will not bring real advantage to represent that in DT for
 140          * the moment, just use a fake OCP bus entry to represent the whole bus
 141          * hierarchy.
 142          */
 143         ocp {
 144                 compatible = "ti,omap5-l3-noc", "simple-bus";
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 ranges = <0 0 0 0xc0000000>;
 148                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 149                 reg = <0 0x44000000 0 0x2000>,
 150                       <0 0x44800000 0 0x3000>,
 151                       <0 0x45000000 0 0x4000>;
 152                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 154
 155                 l4_wkup: interconnect@4ae00000 {
 156                 };
 157
 158                 l4_cfg: interconnect@4a000000 {
 159                 };
 160
 161                 l4_per: interconnect@48000000 {
 162                 };
 163
 164                 ocmcram: ocmcram@40300000 {
 165                         compatible = "mmio-sram";
 166                         reg = <0x40300000 0x20000>; /* 128k */
 167                 };
 168
 169                 gpmc: gpmc@50000000 {
 170                         compatible = "ti,omap4430-gpmc";
 171                         reg = <0x50000000 0x1000>;
 172                         #address-cells = <2>;
 173                         #size-cells = <1>;
 174                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 175                         dmas = <&sdma 4>;
 176                         dma-names = "rxtx";
 177                         gpmc,num-cs = <8>;
 178                         gpmc,num-waitpins = <4>;
 179                         ti,hwmods = "gpmc";
 180                         clocks = <&l3_iclk_div>;
 181                         clock-names = "fck";
 182                         interrupt-controller;
 183                         #interrupt-cells = <2>;
 184                         gpio-controller;
 185                         #gpio-cells = <2>;
 186                 };
 187
 188                 mmu_dsp: mmu@4a066000 {
 189                         compatible = "ti,omap4-iommu";
 190                         reg = <0x4a066000 0x100>;
 191                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 192                         ti,hwmods = "mmu_dsp";
 193                         #iommu-cells = <0>;
 194                 };
 195
 196                 mmu_ipu: mmu@55082000 {
 197                         compatible = "ti,omap4-iommu";
 198                         reg = <0x55082000 0x100>;
 199                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 200                         ti,hwmods = "mmu_ipu";
 201                         #iommu-cells = <0>;
 202                         ti,iommu-bus-err-back;
 203                 };
 204
 205                 mcpdm: mcpdm@40132000 {
 206                         compatible = "ti,omap4-mcpdm";
 207                         reg = <0x40132000 0x7f>, /* MPU private access */
 208                               <0x49032000 0x7f>; /* L3 Interconnect */
 209                         reg-names = "mpu", "dma";
 210                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 211                         ti,hwmods = "mcpdm";
 212                         dmas = <&sdma 65>,
 213                                <&sdma 66>;
 214                         dma-names = "up_link", "dn_link";
 215                         status = "disabled";
 216                 };
 217
 218                 dmic: dmic@4012e000 {
 219                         compatible = "ti,omap4-dmic";
 220                         reg = <0x4012e000 0x7f>, /* MPU private access */
 221                               <0x4902e000 0x7f>; /* L3 Interconnect */
 222                         reg-names = "mpu", "dma";
 223                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 224                         ti,hwmods = "dmic";
 225                         dmas = <&sdma 67>;
 226                         dma-names = "up_link";
 227                         status = "disabled";
 228                 };
 229
 230                 mcbsp1: mcbsp@40122000 {
 231                         compatible = "ti,omap4-mcbsp";
 232                         reg = <0x40122000 0xff>, /* MPU private access */
 233                               <0x49022000 0xff>; /* L3 Interconnect */
 234                         reg-names = "mpu", "dma";
 235                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 236                         interrupt-names = "common";
 237                         ti,buffer-size = <128>;
 238                         ti,hwmods = "mcbsp1";
 239                         dmas = <&sdma 33>,
 240                                <&sdma 34>;
 241                         dma-names = "tx", "rx";
 242                         status = "disabled";
 243                 };
 244
 245                 mcbsp2: mcbsp@40124000 {
 246                         compatible = "ti,omap4-mcbsp";
 247                         reg = <0x40124000 0xff>, /* MPU private access */
 248                               <0x49024000 0xff>; /* L3 Interconnect */
 249                         reg-names = "mpu", "dma";
 250                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 251                         interrupt-names = "common";
 252                         ti,buffer-size = <128>;
 253                         ti,hwmods = "mcbsp2";
 254                         dmas = <&sdma 17>,
 255                                <&sdma 18>;
 256                         dma-names = "tx", "rx";
 257                         status = "disabled";
 258                 };
 259
 260                 mcbsp3: mcbsp@40126000 {
 261                         compatible = "ti,omap4-mcbsp";
 262                         reg = <0x40126000 0xff>, /* MPU private access */
 263                               <0x49026000 0xff>; /* L3 Interconnect */
 264                         reg-names = "mpu", "dma";
 265                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 266                         interrupt-names = "common";
 267                         ti,buffer-size = <128>;
 268                         ti,hwmods = "mcbsp3";
 269                         dmas = <&sdma 19>,
 270                                <&sdma 20>;
 271                         dma-names = "tx", "rx";
 272                         status = "disabled";
 273                 };
 274
 275                 timer5: timer@40138000 {
 276                         compatible = "ti,omap5430-timer";
 277                         reg = <0x40138000 0x80>,
 278                               <0x49038000 0x80>;
 279                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 280                         ti,hwmods = "timer5";
 281                         ti,timer-dsp;
 282                         ti,timer-pwm;
 283                 };
 284
 285                 timer6: timer@4013a000 {
 286                         compatible = "ti,omap5430-timer";
 287                         reg = <0x4013a000 0x80>,
 288                               <0x4903a000 0x80>;
 289                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 290                         ti,hwmods = "timer6";
 291                         ti,timer-dsp;
 292                         ti,timer-pwm;
 293                 };
 294
 295                 timer7: timer@4013c000 {
 296                         compatible = "ti,omap5430-timer";
 297                         reg = <0x4013c000 0x80>,
 298                               <0x4903c000 0x80>;
 299                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 300                         ti,hwmods = "timer7";
 301                         ti,timer-dsp;
 302                 };
 303
 304                 timer8: timer@4013e000 {
 305                         compatible = "ti,omap5430-timer";
 306                         reg = <0x4013e000 0x80>,
 307                               <0x4903e000 0x80>;
 308                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 309                         ti,hwmods = "timer8";
 310                         ti,timer-dsp;
 311                         ti,timer-pwm;
 312                 };
 313
 314                 dmm@4e000000 {
 315                         compatible = "ti,omap5-dmm";
 316                         reg = <0x4e000000 0x800>;
 317                         interrupts = <0 113 0x4>;
 318                         ti,hwmods = "dmm";
 319                 };
 320
 321                 emif1: emif@4c000000 {
 322                         compatible      = "ti,emif-4d5";
 323                         ti,hwmods       = "emif1";
 324                         ti,no-idle-on-init;
 325                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 326                         reg = <0x4c000000 0x400>;
 327                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 328                         hw-caps-read-idle-ctrl;
 329                         hw-caps-ll-interface;
 330                         hw-caps-temp-alert;
 331                 };
 332
 333                 emif2: emif@4d000000 {
 334                         compatible      = "ti,emif-4d5";
 335                         ti,hwmods       = "emif2";
 336                         ti,no-idle-on-init;
 337                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 338                         reg = <0x4d000000 0x400>;
 339                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 340                         hw-caps-read-idle-ctrl;
 341                         hw-caps-ll-interface;
 342                         hw-caps-temp-alert;
 343                 };
 344
 345                 bandgap: bandgap@4a0021e0 {
 346                         reg = <0x4a0021e0 0xc
 347                                0x4a00232c 0xc
 348                                0x4a002380 0x2c
 349                                0x4a0023C0 0x3c>;
 350                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 351                         compatible = "ti,omap5430-bandgap";
 352
 353                         #thermal-sensor-cells = <1>;
 354                 };
 355
 356                 /* OCP2SCP3 */
 357                 sata: sata@4a141100 {
 358                         compatible = "snps,dwc-ahci";
 359                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 360                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 361                         phys = <&sata_phy>;
 362                         phy-names = "sata-phy";
 363                         clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
 364                         ti,hwmods = "sata";
 365                         ports-implemented = <0x1>;
 366                 };
 367
 368                 dss: dss@58000000 {
 369                         compatible = "ti,omap5-dss";
 370                         reg = <0x58000000 0x80>;
 371                         status = "disabled";
 372                         ti,hwmods = "dss_core";
 373                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 374                         clock-names = "fck";
 375                         #address-cells = <1>;
 376                         #size-cells = <1>;
 377                         ranges;
 378
 379                         dispc@58001000 {
 380                                 compatible = "ti,omap5-dispc";
 381                                 reg = <0x58001000 0x1000>;
 382                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 383                                 ti,hwmods = "dss_dispc";
 384                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 385                                 clock-names = "fck";
 386                         };
 387
 388                         rfbi: encoder@58002000  {
 389                                 compatible = "ti,omap5-rfbi";
 390                                 reg = <0x58002000 0x100>;
 391                                 status = "disabled";
 392                                 ti,hwmods = "dss_rfbi";
 393                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
 394                                 clock-names = "fck", "ick";
 395                         };
 396
 397                         dsi1: encoder@58004000 {
 398                                 compatible = "ti,omap5-dsi";
 399                                 reg = <0x58004000 0x200>,
 400                                       <0x58004200 0x40>,
 401                                       <0x58004300 0x40>;
 402                                 reg-names = "proto", "phy", "pll";
 403                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 404                                 status = "disabled";
 405                                 ti,hwmods = "dss_dsi1";
 406                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
 407                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
 408                                 clock-names = "fck", "sys_clk";
 409                         };
 410
 411                         dsi2: encoder@58005000 {
 412                                 compatible = "ti,omap5-dsi";
 413                                 reg = <0x58009000 0x200>,
 414                                       <0x58009200 0x40>,
 415                                       <0x58009300 0x40>;
 416                                 reg-names = "proto", "phy", "pll";
 417                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 418                                 status = "disabled";
 419                                 ti,hwmods = "dss_dsi2";
 420                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
 421                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
 422                                 clock-names = "fck", "sys_clk";
 423                         };
 424
 425                         hdmi: encoder@58060000 {
 426                                 compatible = "ti,omap5-hdmi";
 427                                 reg = <0x58040000 0x200>,
 428                                       <0x58040200 0x80>,
 429                                       <0x58040300 0x80>,
 430                                       <0x58060000 0x19000>;
 431                                 reg-names = "wp", "pll", "phy", "core";
 432                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 433                                 status = "disabled";
 434                                 ti,hwmods = "dss_hdmi";
 435                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
 436                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
 437                                 clock-names = "fck", "sys_clk";
 438                                 dmas = <&sdma 76>;
 439                                 dma-names = "audio_tx";
 440                         };
 441                 };
 442
 443                 abb_mpu: regulator-abb-mpu {
 444                         compatible = "ti,abb-v2";
 445                         regulator-name = "abb_mpu";
 446                         #address-cells = <0>;
 447                         #size-cells = <0>;
 448                         clocks = <&sys_clkin>;
 449                         ti,settling-time = <50>;
 450                         ti,clock-cycles = <16>;
 451
 452                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
 453                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
 454                         reg-names = "base-address", "int-address",
 455                                     "efuse-address", "ldo-address";
 456                         ti,tranxdone-status-mask = <0x80>;
 457                         /* LDOVBBMPU_MUX_CTRL */
 458                         ti,ldovbb-override-mask = <0x400>;
 459                         /* LDOVBBMPU_VSET_OUT */
 460                         ti,ldovbb-vset-mask = <0x1F>;
 461
 462                         /*
 463                          * NOTE: only FBB mode used but actual vset will
 464                          * determine final biasing
 465                          */
 466                         ti,abb_info = <
 467                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 468                         1060000         0       0x0     0 0x02000000 0x01F00000
 469                         1250000         0       0x4     0 0x02000000 0x01F00000
 470                         >;
 471                 };
 472
 473                 abb_mm: regulator-abb-mm {
 474                         compatible = "ti,abb-v2";
 475                         regulator-name = "abb_mm";
 476                         #address-cells = <0>;
 477                         #size-cells = <0>;
 478                         clocks = <&sys_clkin>;
 479                         ti,settling-time = <50>;
 480                         ti,clock-cycles = <16>;
 481
 482                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
 483                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
 484                         reg-names = "base-address", "int-address",
 485                                     "efuse-address", "ldo-address";
 486                         ti,tranxdone-status-mask = <0x80000000>;
 487                         /* LDOVBBMM_MUX_CTRL */
 488                         ti,ldovbb-override-mask = <0x400>;
 489                         /* LDOVBBMM_VSET_OUT */
 490                         ti,ldovbb-vset-mask = <0x1F>;
 491
 492                         /*
 493                          * NOTE: only FBB mode used but actual vset will
 494                          * determine final biasing
 495                          */
 496                         ti,abb_info = <
 497                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 498                         1025000         0       0x0     0 0x02000000 0x01F00000
 499                         1120000         0       0x4     0 0x02000000 0x01F00000
 500                         >;
 501                 };
 502         };
 503 };
 504
 505 &cpu_thermal {
 506         polling-delay = <500>; /* milliseconds */
 507         coefficients = <65 (-1791)>;
 508 };
 509
 510 #include "omap5-l4.dtsi"
 511 #include "omap54xx-clocks.dtsi"
 512
 513 &gpu_thermal {
 514         coefficients = <117 (-2992)>;
 515 };
 516
 517 &core_thermal {
 518         coefficients = <0 2000>;
 519 };