arch/arm/boot/dts/ox820.dtsi

   1 /*
   2  * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
   3  *
   4  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   5  *
   6  * Licensed under GPLv2 or later
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/oxsemi,ox820.h>
  11 #include <dt-bindings/reset/oxsemi,ox820.h>
  12
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16         compatible = "oxsemi,ox820";
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 enable-method = "oxsemi,ox820-smp";
  22
  23                 cpu@0 {
  24                         device_type = "cpu";
  25                         compatible = "arm,arm11mpcore";
  26                         clocks = <&armclk>;
  27                         reg = <0>;
  28                 };
  29
  30                 cpu@1 {
  31                         device_type = "cpu";
  32                         compatible = "arm,arm11mpcore";
  33                         clocks = <&armclk>;
  34                         reg = <1>;
  35                 };
  36         };
  37
  38         memory {
  39                 device_type = "memory";
  40                 /* Max 512MB @ 0x60000000 */
  41                 reg = <0x60000000 0x20000000>;
  42         };
  43
  44         clocks {
  45                 osc: oscillator {
  46                         compatible = "fixed-clock";
  47                         #clock-cells = <0>;
  48                         clock-frequency = <25000000>;
  49                 };
  50
  51                 gmacclk: gmacclk {
  52                         compatible = "fixed-clock";
  53                         #clock-cells = <0>;
  54                         clock-frequency = <125000000>;
  55                 };
  56
  57                 sysclk: sysclk {
  58                         compatible = "fixed-factor-clock";
  59                         #clock-cells = <0>;
  60                         clock-div = <4>;
  61                         clock-mult = <1>;
  62                         clocks = <&osc>;
  63                 };
  64
  65                 plla: plla {
  66                         compatible = "fixed-clock";
  67                         #clock-cells = <0>;
  68                         clock-frequency = <850000000>;
  69                 };
  70
  71                 armclk: armclk {
  72                         compatible = "fixed-factor-clock";
  73                         #clock-cells = <0>;
  74                         clock-div = <2>;
  75                         clock-mult = <1>;
  76                         clocks = <&plla>;
  77                 };
  78         };
  79
  80         soc {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 compatible = "simple-bus";
  84                 ranges;
  85                 interrupt-parent = <&gic>;
  86
  87                 nandc: nand-controller@41000000 {
  88                         compatible = "oxsemi,ox820-nand";
  89                         reg = <0x41000000 0x100000>;
  90                         clocks = <&stdclk CLK_820_NAND>;
  91                         resets = <&reset RESET_NAND>;
  92                         #address-cells = <1>;
  93                         #size-cells = <0>;
  94                         status = "disabled";
  95                 };
  96
  97                 etha: ethernet@40400000 {
  98                         compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
  99                         reg = <0x40400000 0x2000>;
 100                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 101                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 102                         interrupt-names = "macirq", "eth_wake_irq";
 103                         mac-address = [000000000000]; /* Filled in by U-Boot */
 104                         phy-mode = "rgmii";
 105
 106                         clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
 107                         clock-names = "gmac", "stmmaceth";
 108                         resets = <&reset RESET_MAC>;
 109
 110                         /* Regmap for sys registers */
 111                         oxsemi,sys-ctrl = <&sys>;
 112
 113                         status = "disabled";
 114                 };
 115
 116                 apb-bridge@44000000 {
 117                         #address-cells = <1>;
 118                         #size-cells = <1>;
 119                         compatible = "simple-bus";
 120                         ranges = <0 0x44000000 0x1000000>;
 121
 122                         pinctrl: pinctrl {
 123                                 compatible = "oxsemi,ox820-pinctrl";
 124
 125                                 /* Regmap for sys registers */
 126                                 oxsemi,sys-ctrl = <&sys>;
 127
 128                                 pinctrl_uart0: uart0 {
 129                                         uart0 {
 130                                                 pins = "gpio30", "gpio31";
 131                                                 function = "fct5";
 132                                         };
 133                                 };
 134
 135                                 pinctrl_uart0_modem: uart0_modem {
 136                                         uart0_modem_a {
 137                                                 pins = "gpio24", "gpio24", "gpio26", "gpio27";
 138                                                 function = "fct4";
 139                                         };
 140                                         uart0_modem_b {
 141                                                 pins = "gpio28", "gpio29";
 142                                                 function = "fct5";
 143                                         };
 144                                 };
 145
 146                                 pinctrl_uart1: uart1 {
 147                                         uart1 {
 148                                                 pins = "gpio7", "gpio8";
 149                                                 function = "fct4";
 150                                         };
 151                                 };
 152
 153                                 pinctrl_uart1_modem: uart1_modem {
 154                                         uart1_modem {
 155                                                 pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
 156                                                 function = "fct4";
 157                                         };
 158                                 };
 159
 160                                 pinctrl_etha_mdio: etha_mdio {
 161                                         etha_mdio {
 162                                                 pins = "gpio3", "gpio4";
 163                                                 function = "fct1";
 164                                         };
 165                                 };
 166
 167                                 pinctrl_nand: nand {
 168                                         nand {
 169                                                 pins = "gpio12", "gpio13", "gpio14", "gpio15",
 170                                                      "gpio16", "gpio17", "gpio18", "gpio19",
 171                                                      "gpio20", "gpio21", "gpio22", "gpio23",
 172                                                      "gpio24";
 173                                                 function = "fct1";
 174                                         };
 175                                 };
 176                         };
 177
 178                         gpio0: gpio@0 {
 179                                 compatible = "oxsemi,ox820-gpio";
 180                                 reg = <0x000000 0x100000>;
 181                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 182                                 #gpio-cells = <2>;
 183                                 gpio-controller;
 184                                 interrupt-controller;
 185                                 #interrupt-cells = <2>;
 186                                 ngpios = <32>;
 187                                 oxsemi,gpio-bank = <0>;
 188                                 gpio-ranges = <&pinctrl 0 0 32>;
 189                         };
 190
 191                         gpio1: gpio@100000 {
 192                                 compatible = "oxsemi,ox820-gpio";
 193                                 reg = <0x100000 0x100000>;
 194                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 195                                 #gpio-cells = <2>;
 196                                 gpio-controller;
 197                                 interrupt-controller;
 198                                 #interrupt-cells = <2>;
 199                                 ngpios = <18>;
 200                                 oxsemi,gpio-bank = <1>;
 201                                 gpio-ranges = <&pinctrl 0 32 18>;
 202                         };
 203
 204                         uart0: serial@200000 {
 205                                compatible = "ns16550a";
 206                                reg = <0x200000 0x100000>;
 207                                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 208                                reg-shift = <0>;
 209                                fifo-size = <16>;
 210                                reg-io-width = <1>;
 211                                current-speed = <115200>;
 212                                no-loopback-test;
 213                                status = "disabled";
 214                                clocks = <&sysclk>;
 215                                resets = <&reset RESET_UART1>;
 216                         };
 217
 218                         uart1: serial@300000 {
 219                                compatible = "ns16550a";
 220                                reg = <0x200000 0x100000>;
 221                                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 222                                reg-shift = <0>;
 223                                fifo-size = <16>;
 224                                reg-io-width = <1>;
 225                                current-speed = <115200>;
 226                                no-loopback-test;
 227                                status = "disabled";
 228                                clocks = <&sysclk>;
 229                                resets = <&reset RESET_UART2>;
 230                         };
 231
 232                         rps@400000 {
 233                                 #address-cells = <1>;
 234                                 #size-cells = <1>;
 235                                 compatible = "simple-bus";
 236                                 ranges = <0 0x400000 0x100000>;
 237
 238                                 intc: interrupt-controller@0 {
 239                                         compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
 240                                         interrupt-controller;
 241                                         reg = <0 0x200>;
 242                                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 243                                         #interrupt-cells = <1>;
 244                                         valid-mask = <0xFFFFFFFF>;
 245                                         clear-mask = <0>;
 246                                 };
 247
 248                                 timer0: timer@200 {
 249                                         compatible = "oxsemi,ox820-rps-timer";
 250                                         reg = <0x200 0x40>;
 251                                         clocks = <&sysclk>;
 252                                         interrupt-parent = <&intc>;
 253                                         interrupts = <4>;
 254                                 };
 255                         };
 256
 257                         sys: sys-ctrl@e00000 {
 258                                 compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
 259                                 reg = <0xe00000 0x200000>;
 260
 261                                 reset: reset-controller {
 262                                         compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
 263                                         #reset-cells = <1>;
 264                                 };
 265
 266                                 stdclk: stdclk {
 267                                         compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
 268                                         #clock-cells = <1>;
 269                                 };
 270                         };
 271                 };
 272
 273                 apb-bridge@47000000 {
 274                         #address-cells = <1>;
 275                         #size-cells = <1>;
 276                         compatible = "simple-bus";
 277                         ranges = <0 0x47000000 0x1000000>;
 278
 279                         scu: scu@0 {
 280                                 compatible = "arm,arm11mp-scu";
 281                                 reg = <0x0 0x100>;
 282                         };
 283
 284                         local-timer@600 {
 285                                 compatible = "arm,arm11mp-twd-timer";
 286                                 reg = <0x600 0x20>;
 287                                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
 288                                 clocks = <&armclk>;
 289                         };
 290
 291                         gic: gic@1000 {
 292                                 compatible = "arm,arm11mp-gic";
 293                                 interrupt-controller;
 294                                 #interrupt-cells = <3>;
 295                                 reg = <0x1000 0x1000>,
 296                                       <0x100 0x500>;
 297                         };
 298                 };
 299         };
 300 };